JPS62204304A - Signal processor - Google Patents

Abstract

PURPOSE:To process the changing degree of the natural world having at least two different changes at a time and also at a prescribed time point, by selecting the analog signal that is processed based on the time points stored in a storing means and having different changes out of at least two analog signal having different changes. CONSTITUTION:A signal processor can select the scan priority of a fast A/D input port 6. Then the input value is compared with the basic value set previously with no intervention of a fast CPU 2. Thus an interruption is applied to the CPU 2 only when a change is detected in case a certain external state is sampled and detected. Therefore the duty ratio of the output value of a fast PWM output port 8 can be changed by setting the target value after check of the data at the relevant time point. While the port 6 can set optionally the cycle and speed of conversion by changing the fast scan mode and the clock rate of a scan limiter. Thus the port 6 can freely change the modes in accordance with the external change.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a signal IA management device.

In particular, it relates to a signal processing device that processes analog signals.

[Background Art] In recent years, there has been remarkable progress in all industrial fields, including OA, FA, and LA. This can be said to be the result of a successful fusion of electronics and mechanics. Needless to say, the basis for this will depend to a large extent on the remarkable progress in semiconductor integration technology and the synergistic results with computer technology.

In order to disseminate products in large quantities at low prices, the L of the system is essential.
SI conversion is necessary. However, there is still a lot of waste at the interface between the mechanism and the electronics that control it.

Currently, a microcomputer or microcontroller (one-chip microcomputer including memory, Ilo) is used for the contact.

By the way, phenomena in machines and especially in the natural world are continuous changes in analog information. Currently, some one-chip microcomputers are equipped with an A/D converter on-chip to accommodate this. However, the on-chip A/D converter operates in scan mode and select mode, and its speed is fixed.

In addition to the CPU and memory, current microcontrollers also have counters/timers, A/D converters, and PWM.
Output 1 Display device interface, for example, LC
Only those with a built-in D interface driver have been announced. This alone is insufficient to capture and process changes in various analog quantities in the natural world and provide feedback in the form of analog quantities; in reality, controllers dedicated to each device are provided externally. Therefore, the cost is correspondingly high.

Furthermore, many mechatronic controls control the load periodically according to the timing of the sequence. For example, let's assume that the motor that performs positioning has three glaze controls for the x, y, and z axes. The three-axis motors are controlled simultaneously only during a certain period of time, and in many other cases, the x, y, and z motors operate mutually. When operating three axes at the same time, the controller requires maximum speed, but when operating in other directions,
You should be able to afford other jobs.

[Problems to be Solved by the Invention] The present invention provides a signal processing device that processes at least two different amounts of change in the natural world simultaneously and at a predetermined time.

Furthermore, the present invention eliminates the conventional waste as much as possible, incorporates various amounts of change and points of contact with electronics into the structure of semiconductors and LSIs, and further strengthens the integration and fusion with mechanics. The present invention provides a signal processing device according to the present invention.

[Means for solving the problem] As a means for solving this problem, for example, the signal processing device of the embodiment shown in FIG. 2 includes a microprogram controller 1, a high-speed processor 2, a general-purpose communication interface 3, Input boat 4, output boat 5, and high speed A/
D input capolo and 1. /O controller 7, high speed PWM output port 8, memory 9, and low speed co-processor 10.

As shown in FIG. 3, the high-speed A/D input port 8 includes a control logic 30, a control register 31, a multiplexer 32, an A/D conversion circuit 33,
The data register 34 is also provided.

[Operation] In the configurations shown in FIGS. 2 and 3, the signal processing device can select the scanning priority of the high-speed A/D input port. For example, if there are 8 channels,
In addition to manually scanning channels 0 to 7 in order from 0 to 7, it is also possible to repeatedly scan from 0 to 4, or from 4 to 7.

Then, a judgment is made between the human power value and a preset basic value without the intervention of the high-speed CPU 2, and if the value deviates from a certain range, the high-speed CPU 2 is interrupted. Therefore, when sampling and detecting a certain external state,
Since the high-speed CPU 2 is interrupted only when there is a change, the duty ratio of the output value from the high-speed PWM output port 8 can be changed so that the data is checked and set to the target value at that time.

These series of operations, i.e., high-speed A/D controller → check by high-speed CPU 2 → feedback of duty ratio by high-speed PWM output port 8 (pulse width modulation), are performed by the microprogram controller 1 in 1 to 2 μS.
You can do it with eC.

On the other hand, the high-speed A/D input captro has 8 channels of input, and this input is selected by the multiplexer 32, A/D converted by the A/D conversion circuit 33, and the conversion result is sent to the 8 data registers 34. is maintained.

The high speed A/D input port is controlled by control logic 30 based on control register 31. High speed A/
With the D input captro, the conversion cycle and speed can be set arbitrarily by changing the fast scan mode, scan limiter, and clock rate, and the mode can be changed freely in response to external changes.

Furthermore, since the amount of change to be checked at a predetermined time is programmed in advance, unnecessary checks can be avoided and the signal processing device can have more leeway.

[Example] First, let's give an overview of the controller as a whole.

FIG. 1 shows a layer (hierarchical) structure diagram of a signal processing device.

The structure in Figure 1 consists of at least 5 layers a''-'e.
It is divided into two layers. Layer a is a microprogram controller, and layer b is a C for high-speed calculation.
PU, Layer C is memory including general-purpose ROM, RAM,
Contains high-speed CPU memory for layer b. Layer d is a group of independently operating co-processors that performs sequence control and other controls in cooperation with various T10 devices. Here, a number of CO-processors corresponding to Ilo are required to perform various types of handling. The lowest layer e includes various Ilo's necessary for controlling mechatronics. Like this,
Having a hierarchical structure gives characteristics to high-speed control of mechatronics, especially analog control.

FIG. 2 shows a block diagram of the signal processing device.

In this example, several hundred bytes of instructions are executed in one cycle (1 to 2μ5e) for controlling mechatronics that handles analog quantities.
In c), there is a microprogram controller 1 that performs pipeline control, a high-speed processor 2 that operates at 20M) (3 to 4 times faster than a normal dPU), and a general-purpose processor 2 that performs communication with the outside. Communication interface 3
, an input port 4, an output port 5, a high-speed A/D input port, an I10 controller 7, a high-speed pwM output port 8, a memory 9, and a low-speed CO-processor 10. Among these, the microprogram controller 1. The high-speed processor 2, the general-purpose communication interface 3, and the like may be combined on one substrate, or it is more cost-effective to use them as a super-L'SI as one chip on silicon.

High speed processor 2 is at least 400-600μsea
/Instruction works. It also has a register bank in CPtJ, accesses input port 4 and output port 5 in bit units, and has 16 channels of 16-bit timer/counters, that is, a timer array.

The high-speed A/D input port with a zero-cross detector for zero-cross point detection has eight channels, and the scan priority can be selected using a register. For example, in addition to sequentially scanning the inputs of channels 0 to 7 from 0 to 7, it is also possible to repeatedly scan from 0 to 4, or from 4 to 7. That is, there is a data storage RAM corresponding to each channel, and the size determination from a preset basic value is performed without the intervention of the CPU. If the value deviates from a certain range, an interrupt is generated to the CPU. Therefore, when sampling and detecting a certain external state, the CPU is interrupted only when there is a change, so at that time,
Check the data and change the PWM duty ratio to set it to the target value.

These series of operations, namely A/D manual operation → CPU check and duty ratio feedback using PWM (pulse width modulation), are performed by the microprogram controller 1.
This can be done in 1 to 2 μSec. For example, by storing light intensity, density, motor speed, and power supply stabilization as one macro code, and calling and executing it, a series of these operations can be executed with one command.

Conventionally, it has been impossible to detect and feed back analog quantities using a general-purpose processor because it requires several hundred steps of instructions and there are physical response time problems. Therefore, a dedicated controller was installed externally. As in this embodiment, the above-mentioned impossibility has become possible by providing a microprogram controller.

The I10 controller 7 includes a pulse generator for the pulse motor, a PLL for the servo motor, a high-speed PWM (approximately 8-bit resolution of 40KH2), an external clock input port (servo motor's encoder input), a one-shot pulse generator, a zero-cross detector, It includes analog, quantity-based controllers such as free-run timers, and mechatronic control functions.

General-purpose communication interface 3 is Celetronix or R5.
It is equipped with a globally standardized general-purpose interface such as -232C.

Next, let us discuss the structure of the high-speed A/D input captro.

As mentioned earlier, all physical quantities in the natural world are analog, and when controlling these, the AD converter is the gateway, and only after digitizing the signal can it be controlled by the processor. .

High-precision AD converters, especially those with high speed, are expensive and cannot be installed in very cheap mass-produced equipment. Therefore, in this embodiment, A/D converters with several channels are provided, and those that can handle a large number of analog inputs and require high-speed conversion are
This is an attempt to adapt to the characteristics of external signals by changing the scan order or changing the machine state.

When designing a single device, four or more channels are usually required to process analog values.

For example, in the case of a copying machine, which is the star type of OA type equipment, the recognition of the density pattern of the original, the output stabilization motor of the low-voltage power supply,
There are output stabilization motors, light source monitors, temperature monitors for temperature control, etc. for high voltage power supplies.
There are ~3 types, so you will need 8 channels just for this. Furthermore, an image processing device that handles images requires a high-speed, several-channel A/D converter that performs gradation control.

FIG. 3 shows a functional block diagram of the high-speed A/D driver.

The high-speed A/D converter of this example employs a successive approximation method in order to keep the structure simple and inexpensive. This high IA/
The D input captro has 8 channels of input. Let this input be ADIO~7. The human power is selected by the multiplexer 32, and the A/D conversion circuit 33 selects the A/D signal.
After D conversion, the conversion results are held in eight data registers 34. The data registers 34 are designated ADRO-7 in channel order. The high speed A/D input port is controlled by control logic 30 based on control register 31.

Next, the format of the control register 31 is illustrated in FIG. Let 8 bits of the control register 31 be ADCO~7.

By setting bits in the control register 31, the high-speed A/D driver can be controlled. The 8th bits A and DC7 of the control register 31 start and stop the high speed A/D input port.

The scan mode is selected using two bits of ADC6 and ADC5. This is a normal scan mode in which all eight channels are repeatedly scanned, or a priority is determined in which a specific channel is always scanned from the beginning, and the four channels excluded by the scan limiter are of course omitted.

The three bits of ADC4, ADC3, and ADC2 determine the scan limiter. That is, this is a channel for specifying one of eight A/D converter channels, and can specify from all channels to a single scan of channel 0. A
DC2 specifies the clock of the A'D converter, and the conversion time per channel can be specified with two clocks.

The two bits ADCI and ADCO determine whether or not to interrupt the CPU when the A/D conversion result is input into the data register 34 in Figure 3. Can be specified individually.

As mentioned above, devices that require high speed perform A/D conversion only on specific channels, and control the conversion speed by controlling the 3103rd bit of the control register.
Double the conversion speed by setting 1 to 2 (30
μsec→15μ5ec).

Mechatronics control controls various control objects based on timing, so when high speed is required at a certain timing, it is possible to respond to that request by changing the conversion speed and applying a scan limiter.

Now, by incorporating the functions described above into the signal processing device, it has become possible to concentrate the functions of the individual control units into the signal processing device.

However, as mentioned in the section of the prior art, it is rare for the entire analog control amount to operate at the same timing. - Let's explain the control of a copying machine as an example.

FIG. 5 is a system configuration diagram of the copying machine. Among these, from the left in Fig. 5, the one that performs analog control is the original m concentration recognition i@54. Text heater 56. Lamp 55. Electrostatic charger (CC) 51. Transfer charger (TC)52. A separate charger (QC) 53 and a DC low voltage power supply 50.

Although these analog controls can be centrally performed by the controller 59, the sampling period must be made high-speed in order to maintain accuracy.

FIG. 6 is a block diagram of an analog control device for a copying machine in which only the analog control portion of the system configuration of the copying machine shown in FIG. 5 is highlighted. Here, 7 of CHO~CH6
Using a real A/D converter, P as feedback
The load is stabilized by controlling the width of seven pulses, WMO to PWM6 (PWM4 is bias).

FIG. 8 is a timing chart of the copying machine. Among the items on the left, the underlined items indicate examples of analog control, and the red stamped items require particularly high precision. Therefore, the timing for accelerating the sampling period is determined naturally.

The most critical timing is when the original is being scanned, when the DC low voltage power supply is turned off at 50. Electrostatic charger 51. The lamp 55, the transfer charger 521, the separation charger 53, and the original density recognition 54 are overlapped. At this timing, a predetermined priority must be determined and sampling must be performed. At this time,
It is sufficient to fill in the IA for the amount of change with the highest priority in the first scan mode, then apply scan limit to prepare for the amount of change that has the next priority.

Figure 7 is a flowchart of analog signal control of a copying machine.
Show the diagram. This flowchart also shows the control status of the A/D converter. Let's explain step by step.

Step 5701: Power is turned on.

Step 5702: The output monitor and PWM control for generating the DC low voltage power supply 5o is performed, and the scholar heater 56 is turned on. Therefore, 2 of CHO, CH6
Perform two limit scans. CH6 needs to be sampled frequently until it starts up, and a DC low voltage power supply of 5o is required.
Perform similar monitoring.

Step 5703: The scholar heater 56 has risen to a predetermined temperature. From now on, CH6 can be monitored infrequently.

Step S704. : The copy start key is pressed and the copy process begins.

Step 5705 Since the registration roller is turned on, DC
Fluctuations in the low voltage power supply 50 are large. Therefore, CHO is set to fast scan and CH3 to CH6 are set to limit scan for monitoring.

Step 5706: Perform the most critical monitoring of the first copy. With all loads on, CHI is set to fast scan to double the conversion speed. CHO, CH5° CH6, CH3, CH4 are set to limit scan in this order.

Step 5707: The first process is turned off. However, since the scan motor starts to reverse and the paper for the second copy is moved, the load fluctuation of the DC low voltage power supply 50 is large. CHO performs fast scan and double speed, and CH2, CH3 and CH6 perform limit scan in order. .

Step 8708 Almost the same as step 5706. Since the transfer paper enters the charger 51, the lamp 55, and the fixing roller, the load on the DC low voltage power source 50 varies greatly. In this example, DC motors are used as the main motor and scan motor.

Step 5709: This is the OFF timing for the entire copy process, but since the paper repeatedly enters the fixing roller, the amount of fluctuation in the DC low voltage power supply 50 is large. Therefore, CHO
As the first scan mode, the priority is increased.

As mentioned above, priority is given to the order of sampling according to the external load condition, and it is now possible to centrally control digital processing of analog amounts in the controller 59 (one chip), which was previously impossible. did.

This reduces costs and downsizes the packaging. By programming analog control, flexibility is achieved, and the traditional unit-by-unit packaging is replaced by chip-by-chip packaging. Ta. Furthermore, by preparing a program library using microprograms, it is possible to control many analog quantities.

In this example, the scanning order was changed by inputting a periodic trigger pulse from the outside (for example, a zero-crossing pulse), but the purpose of the present invention is to change the order of channels depending on the timing of the sequence. Since the priority is to be changed, a macro instruction may be prepared and an internal pulse may be generated at each timing to change the scan sampling order.

[Effects of the Invention] According to the present invention, it is possible to provide a signal processing device that processes at least two different amounts of change in the natural world simultaneously and at a predetermined time.

In addition, by incorporating various changes and points of contact with electronics into the structure of semiconductors and LSIs, we can integrate them with mechanics,
It is possible to provide a signal processing device that can perform fine-grained control that follows the magnitude of load fluctuations and has more robust integration.

Furthermore, the signal IA embedding device of the present invention can quickly respond to changes in the external world and can achieve digital processing of analog signals, which was impossible until now, at low cost, so it can now be applied to popular machines for consumer use. Ta.

[Brief explanation of drawings]

Fig. 1 is a layer structure diagram of the signal processing device, Fig. 2 is a block diagram of the signal processing device, Fig. 3 is a functional block diagram of the high-speed A/D input port, Fig. 4 is a format diagram of the control register, Fig. 5 Figure 6 is a block diagram of the copying machine's analog control device, and Figure 8 is a timing chart of the copying machine. In the figure, 1... micro program controller, 2...
...High speed processor, 3...General purpose communication interface, 4...Input port, 5...Output port, 6...
・High-speed A/D, J port, 7...-I10 controller, 8... High-speed PWM output port, 9... Memory,
DESCRIPTION OF SYMBOLS 10...Low speed co-processor, 30...Control logic, 31...Control register, 32...Multiplexer, 33...-A/D conversion circuit,
34...Data register.

Claims (13)

[Claims] (1) In a signal processing device that processes analog signals,
Storage means for storing changing timings of at least two analog signals that change differently; and selection for selecting an analog signal to be processed from the at least two analog signals that change differently based on the timings stored in the storage means. A signal processing device comprising: means. (2) The signal processing device according to claim 1, wherein the analog signal is converted into a digital signal and processed by an A/D converter. (3) A second device for selecting an analog signal to be processed in a predetermined order from among the analog signals selected by the selection means.
selection means, and the second selection means corresponding to a change in the analog signal.
2. The signal processing device according to claim 1, further comprising changing means for changing the order of selection by the selecting means. (4) The signal processing device according to claim 3, wherein the priority order is changed depending on the magnitude of the rate of change. (5) The signal processing device according to claim 3, wherein the priority order is changed depending on the magnitude of the change period. (6) The signal processing device according to claim 3, wherein when the amount of change is larger than a predetermined threshold, processing is performed with a higher priority. (7) In a signal processing device that processes analog signals,
storage means for storing change timings of at least two analog signals that change differently; and processing based on the timings and changes in the analog signals stored in the storage means from the at least two analog signals that change differently. A signal processing device comprising: selection means for selecting an analog signal. (8) The signal processing device according to claim 7, wherein the analog signal is converted into a digital signal and processed by an A/D converter. (9) The signal processing device according to claim 7, wherein the selection means selects the analog signal when the amount of change in the analog signal is larger than a predetermined value. (10) a second selection means for selecting an analog signal to be processed in a predetermined order from among the analog signals selected by the selection means; and selection by the second selection means in response to a change in the analog signal. 8. The signal processing device according to claim 7, further comprising: changing means for changing the order of the signals. (11) The signal processing device according to claim 10, wherein the priority order is changed depending on the magnitude of the rate of change. (12) The signal processing device according to claim 10, wherein the priority order is changed depending on the magnitude of the change period. (13) The signal processing device according to claim 10, wherein when the amount of change is larger than a predetermined threshold, processing is performed with a higher priority.