JPS62203521U - - Google Patents
Info
- Publication number
- JPS62203521U JPS62203521U JP9184286U JP9184286U JPS62203521U JP S62203521 U JPS62203521 U JP S62203521U JP 9184286 U JP9184286 U JP 9184286U JP 9184286 U JP9184286 U JP 9184286U JP S62203521 U JPS62203521 U JP S62203521U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- flip
- outputs
- flop
- logic gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Manipulation Of Pulses (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9184286U JPS62203521U (it) | 1986-06-18 | 1986-06-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9184286U JPS62203521U (it) | 1986-06-18 | 1986-06-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62203521U true JPS62203521U (it) | 1987-12-25 |
Family
ID=30952993
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9184286U Pending JPS62203521U (it) | 1986-06-18 | 1986-06-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62203521U (it) |
-
1986
- 1986-06-18 JP JP9184286U patent/JPS62203521U/ja active Pending