JPS62200597A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the area of a memory array by forming a memory element with two pieces of transistors having a two-bit information connected in series to reduce by half the number of pieces of the contact holes on bit lines. CONSTITUTION:When the output N1 of a NOR circuit decoder 5 is turned in a low level, a transistor TR12 causes the gate voltage of the two memory transistors to come in the low level. The transistor TR12 is set so that the above said low level of the gate voltage goes lower than the lower one of the thresholds of the memory transistors. Thus one of addresses that relate to a word line is used for determining the combination of the gate voltage of the two transistors in series connection. The write of the two-bit storage information is executed in a way that, one of the four kinds of write information that are unequivocally determined by the two-bit information relating to one address, is stored. As a result, the number of pieces of the contact holes on the bit line is reduced to half, and the memory array area is also reduced.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention is a semiconductor integrated circuit read-only memory t2 ROM (Read OnlFMemor) with high density.
y).

[Conventional technology]

An example of a conventional semiconductor memory device is shown in FIG. 4 and explained as follows.
(a) shows an example of a pattern layout diagram of a memory array of a conventional MO8 type ROM, and (b) shows an example of a circuit diagram of the memory array.

1. In FIG. 4(a), Wt, W2...W8 are word lines made of polycrystalline silicon, for example.
This is also used as the gate of a memory transistor. The part 1 is the channel region of the memo IJ l-transistor. In addition, bl l 1) 1...b6 is a bit line wired with aluminum gold, for example, and this is a part where a memory transistor is formed. It is connected to the diffusion layer 3 forming the . 4 is a diffusion layer forming the source gold of the memory transistor;
This diffusion layer 4 is connected to the source metal interconnection Sl through the entire contact hole 2.

Next, in FIG. 4(b), W, , W, , W are word lines, and bhb2Hbs is a bit line. Then, the gate of the memory transistor is connected to the word line W1.
~W3 and the drain are connected to the bit lines b1 to b3, respectively, and the source is connected to GND (in this circuit diagram).
Ov).

To read out the memory array arranged in this way, one line is selected from each of the plurality of word lines Wl, W2... and bit lines b,, b,..., and the selected line is read out. The memory transistor at the intersection of the word line and bit line matrices is 1
be redeemed. Then, depending on whether the threshold voltage of the selected memory transistor is lower or higher than the gate voltage, whether the memory transistor is in a bad conduction state or not.
This is done by reading 1-bit information of 10'' or 11# corresponding to whether the communication is OFF or not.

L, Taka, Memo IJ Transistor writing is,
This is done by setting a threshold voltage that is either lower or higher than the gate voltage.

[Problem that the invention seeks to solve]

Since the memory array of a conventional semiconductor memory device, that is, a ROM, is configured as described above, when reducing the memory array area, it is necessary to change the manufacturing process parameters, such as the width of polysilicon and metal wiring, and the mutual There was a problem in that the reduction rate could only be reduced by improving the manufacturing precision of the spacing between the contact holes or the size of the contact holes, but the reduction rate did not increase beyond the proportional reduction due to the improvement of the manufacturing precision.

On the other hand, the increase in memory capacity in recent years has been very rapid, and the rate of increase is greater than the rate of decrease in memory arrays mentioned above.As a result, the area of the entire storage device, of which the memory array occupies most It also showed a tendency to increase.

And eventually, as the area of the integrated circuit chip increases,
The yield rate per unit of Ueno decreases, and finally, 1
There was a problem in that the manufacturing cost per elongated product was high.

Now, if we examine the problems in reducing the total area of the memory array described above more deeply, we will find the following.

In other words, when reducing the memory array area, the most difficult part to reduce is the connection between the bit line and the diffusion layer that forms the drain of the memory transistor. This is the contact part where yGe is used. The contact hole is located at the mirror position of the two memory transistors that are symmetrical on the border, and also serves as the drain of the memory transistor that is symmetrical on the border. The size of the contact hole itself and the distance between the contact hole and the gate are relatively difficult to reduce compared to other manufacturing parameters, and since it is used for only two memory transistors, the contact hole connected to the bit line The number of holes is required to be several times the number of word lines, and as the number of word lines increases as the memory capacity increases, the number simply increases proportionally.

This invention was made in order to solve this problem, and has a memory array configuration in which the number of contact holes connected to the memory bit line is reduced, and the memory array area is proportionally reduced by improving the manufacturing accuracy of Ueno 1 process. It is an object of the present invention to obtain a semiconductor memory device that is dramatically reduced in size.

[Means for Solving the Problems] A semiconductor memory device according to the present invention has a structure of a memory element arranged at the intersection of a word line and a bit line. The memory element is read out by connecting the drain of one of the serially connected transistors to the bit line, and one of the addresses related to the word line is one of the two addresses mentioned above. It is used to determine the combination of two types of voltages applied to the gates of the series-connected transistors, and the writing of the above 2-bit memory information is uniquely determined by the 2-bit information related to the 1 address above. This is done by storing all the written information for one of the classes.

[Effect]

In this invention, the number of contact holes connected to the bit lines is one for every four word lines, which is reduced by half compared to the conventional case of one for every two word lines. By dramatically reducing the length of the memory array, the area of the memory array can be dramatically reduced.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of a semiconductor memory device according to the present invention, in which (a) shows a pattern layout diagram of a memory array, and (b) shows a circuit diagram of a memory array. be.

First, in FIG. 1(a), from wl&, WIb to W4
Word lines a and Wg are word lines W1a and Wlb, respectively, which are also used for the gates of memory transistors connected in columns on two sides. bl to b6 are bit lines, which are connected to the drain diffusion layer 3 through the entire contact hole 2 at one of the memory IJ transistors connected in series. The repetition of the contact hole 2 on the bit line is because a pair of two memory transistors connected in a row also serves as the contact hole 2 and are arranged in mirror symmetry, so in the end, there are four word lines. This results in one repetition, and the number of contact holes on the bit line is halved compared to the prior art shown in FIG. 4 described above. Sl is a metal wiring, and this metal wiring S is a contact hole 2 that is completely passed through the diffusion layer 4 that forms the source of the other memory transistor where the contact hole of the drain of the two memory transistors connected in a row is not taken. It is wired.

Next, in FIG. 1(b) which is a circuit diagram of a memory array which is an embodiment of the present invention, from W, a, Wlb to W
3alW3b is a word line, and b to b3 are bit lines. In the example shown in this figure, the source of the transistor on the side not connected to the bit line of the two side column-connected memory transistors is at ground level (GND).

Then, the memory element placed at the intersection of the word line and the bit line is composed of two transistors connected in series with a 2-bit storage information sound, and the drain of one of the series-connected transistors is connected to the bit line. The memory element is configured to read data from the memory element.

Next, the operation of the embodiment shown in FIG. 1 will be explained with full reference to FIG. 2.

FIG. 2 is a circuit diagram including a memory array and a gate voltage signal generation circuit.

In FIG. 2, which includes this memory transistor gate input circuit, a portion 5 surrounded by a broken line is a conventionally commonly used NOR circuit decoder for selecting word lines, and the number of outputs varies from address signal a1 to Assuming that the address signal is a NOR circuit decoder,
There are 2n outputs, and only the output of the selected one out of these 2n outputs is at sH'' level (the voltage level of the power supply voltage, e.g. 5V
), and the other (2n1) book is 'L' level (GN
DL/Hell).

Then, the one selected by this NOR circuit decoder 5 selects two series-connected memory transistors, and the other address (aO in FIG. 2) selects two series-connected memory transistors.
By determining two types of combinations of gate voltages of series-connected transistors, 2-bit (0 or 1) memory information is
9] information will be obtained.

Therefore, from one bit line b+, the total (2
nK2=2n+1) bits of memory information are obtained. In the case of the conventional example shown in FIG. 4(b), a total of 2n+1 decoder outputs from address signals aO to anma serve as word lines as they are, and the memory transistor 1
Since 1-bit information can be obtained for each item, the total (2!l+
1X1=2n+1) bit number, which is naturally the same number of bits as memory information from one bit line.

Next, we will specifically explain the operation of obtaining 2-bit information from two parallel-connected memory II transistors. One example is a bit information combination table.

This table is a table of input signals and threshold voltage combinations of memory transistor gate voltages for explaining the present invention in detail.

And in this table, E, = lV, E, = 3
V, L1=2V, H+=5V.

First, if the output N of the NOR circuit decoder 5 is a selected line and is set to 'H level, then the two-manufactured NAND circuit T based on the output Nl and the address signal a0 will have an output N of the NOR circuit decoder 5 of 1H. “Since it is a level input, it becomes an inverter circuit determined by the input of the address signal a0.

Then, the output 8 and the output 10 of the inverter circuit 9 which receives the output 8 as inputs are respectively input to the gates of the two memory transistors. Therefore, address signal a
, H, the two types of memory transistor gate voltages are
(■I, Ll) or (L, ,) shown in the table above, respectively.
H wealth) is determined. Here, the important point of this invention is the voltage level of Ll. H, is the conventional s
It is 5V in H level, but the %L# level voltage of IJI needs to be higher than the voltage E+ (El=lV in this example) on the lower side of the threshold voltage of the transistor shown below. And the voltage at Ll level is NA
This can be realized relatively easily by adjusting the transistor sizes of the transistors constituting the ND circuit T and the inverter 9. In this example, H, = 5V and L, = 2V. Furthermore, the threshold voltage of the memory transistor was set to E I =1vrEl""3v. This threshold voltage can also be achieved relatively easily by, for example, the degree of ion implantation.

Now, as mentioned above, by combining the gate voltage levels of the two parallel-connected memory transistors I3 and the combination of the threshold voltage levels of the memory transistors, the memory transistors can be connected to the desired memory as shown in the table above. When setting information, that is, when writing, the following precautions are required.

That is, in the conventional memory element configuration of one transistor and one bit of information, it is sufficient to determine the threshold value of one corresponding memory transistor based on one bit of memory information of 0 or l, but the memory array configuration of the present invention So,
One of the four combinations of threshold voltages of the two memory transistors is uniquely determined by two bits of memory information determined by the address signal a0.

The threshold voltage setting method for one combination of these four types, that is, the embedding method is shown in the example of a mask ROM using the ion implantation method. I want to memorize the combination table of 4 and write it into all memory transistors based on the implantation amount that can be set to the threshold value of tuna.
Depending on one of the types, a complete mask is made so that ion implantation can be applied only to transistors that require a threshold value of E2. In the end, one out of four types can be set with one injection mask.

Next, the operation of the memory transistors on non-selected lines will be explained.

First, the output N! of the unselected NOR circuit decoder 5! is SL
' level, the inverter 11 of the memory gate voltage generation circuit 6 in the part surrounded by the broken line is passed through the 1. The gate voltage of the two memory transistors becomes %L# level due to the transistor 12, and the second
The memory transistors are completely unselected and do not affect the selected memory transistors on the same bit line.

Next, the SL' level of this gate voltage is Memo+7
Transistor 12 is selected such that the lower transistor threshold voltage, in this embodiment, is always lower than E, = lV.
The gate width and gate length must be set.

In this way, one of the addresses associated with the word line is used to determine the combination of two voltages applied to the gates of the two series-connected transistors, and the two bits of memory information are stored in the memory. Writing is performed by storing one of four types of write information %i that is uniquely determined by the 2-bit information related to one address.

Note that the configuration of the circuit w5 of the memory gate voltage generation circuit 6 shown in FIG. 2 is one example, and the combination of gate voltages of the two memory transistors based on the address signal a0 is limited to the above table.

Various circuit configurations are possible.

All that is required is to obtain 2-bit information by combining the gate input and threshold voltage of the memory transistor.

As an example of another circuit configuration, an example of a NAND circuit decoder is shown in FIG.

In FIG. 3, the same symbols as in FIG. 2 indicate corresponding parts, bl is a bit line, W1B, Wlb, W2
B+W2b represents the word 6 line, &t, l@鵞@@@@@n represents the address signal.

The combinations of ON and OFF in the case of the circuit example shown in the third factor are the same as those in the table above. Although the threshold voltage of the IJ transistor is set using the ion implantation method in the explanation of FIG. 2, it is not limited to ion implantation as long as there is a method that can change the threshold voltage.

Furthermore, the signal combinations in the table above and Hl + Ll
As for setting the voltage level of rE 11 E snow, as long as 2-bit information is obtained, various combinations and voltage levels can be considered, and it is possible to have the same effect 1.

〔Effect of the invention〕

As explained above, according to the present invention, the memory element ti
As a result, the number of contact holes on the bit line can be reduced to one-fourth of the number of word lines.
The number can be dramatically reduced by half compared to the conventional case, and the length of the memory array in the bit line direction will be extremely short, resulting in a dramatic reduction in the memory array area. , the practical effect is extremely large.

Furthermore, according to the present invention, the number of contact holes in the memory play is reduced, thereby reducing defects caused by contact holes in the wafer manufacturing process, and increasing the yield of non-defective products. It is extremely effective in terms of connecting.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a circuit diagram showing an extracted main part of the invention, and FIG. 3 is a circuit diagram showing another embodiment of the invention. FIG. 4 is a diagram showing an example of a conventional semiconductor memory device. 1...Memory transistor channel region, 2#Φφ
O contact hole, 3...-Drain diffusion layer, 4.
... Source diffusion layer, 5... NOR circuit decoder,
6...-Memory gate voltage generation circuit, 7-...NA
ND circuit inverter, 9.11...Inverter, 1
2・e... Transistor, bI-b6 ・Autumn... Bit line, Wl a+ W1b~W4a, W4b −
---Word line, Sl...source metal wiring.

Claims (2)

[Claims] (1) In a semiconductor integrated circuit read-only memory device in which a memory element is arranged at the intersection of a word line and a bit line, the memory element has a configuration of two transistors connected in series having 2 bits of storage information, and A semiconductor memory device characterized in that reading of a memory element is performed by connecting one drain of series-connected transistors to a bit line. (2) In a semiconductor integrated circuit read-only memory device in which a memory element is arranged at the intersection of a word line and a bit line, the memory element is composed of two transistors connected in series having 2 bits of memory information, A drain of one of the series-connected transistors is connected to a bit line to allow reading of the storage element, and one address of the addresses related to the word line is applied to the gates of the two series-connected transistors. The writing of the 2-bit memory information is performed by writing one of the four types of writing information uniquely determined by the 2-bit information related to the one address. A semiconductor memory device characterized in that a semiconductor memory device performs storage by storing data.