JPS6220015A - Control circuit of integrated circuit - Google Patents

Abstract

PURPOSE:To reduce frequencies of clock signals distributed to individual microprocessors by inputting a single pulse to generate control pulses in an integrated circuit by gate delay logic circuits. CONSTITUTION:A clock (c) with a one-cycle time as the period is inputted to an input pin 1 of an integrated microprocessor M. An internal clock (d) is obtained as the output signal of an inverter aN by propagation delay of inverter groups a1, a2,...aN. Internal clocks (e) and (f) are obtained similarly by inverter groups b1, b2,...bN and c1, c2,...cN. The clock (c) and internal clocks (d), (e), and (f) are allowed to pass logic circuits (NOR gates) aNOR, bNOR, and cNOR to obtain control pulses, and these control pulses are led to a control circuit 2. The control circuit 2 controls circuits like an operating circuit 3.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a control circuit for an integrated circuit, and more particularly to the creation of a control clock for a digital signal processing LSI.

Conventional technology Due to the miniaturization of semiconductor processing technology, LSI (Large Scale
Integration) elements are being manufactured. For example, an LSI commonly called a microcomputer
The devices are internally equipped with a program memory, an arithmetic circuit, a data memory, etc., and are configured to be able to exchange digital signals with each other via a bus, and process signals input from the outside according to the program. A pulse called a clock temporally controls the signal processing of a microcomputer. As explained in Iwahi Lecture Microelectronics Microcomputer Hardware by Iwao Morishita, published by Iwanami Shoten, pages 8 to 19, four clocks (Figure 3a) perform one cycle of operation. That is, the address (FIG. 3b) is sent to the bus, and the output data of the arithmetic unit (FIG. 3C) is obtained in the latter half of one cycle. Control pulse (a), (b), (c),
2) is a pulse generated from the clock (FIG. 3a), which controls the RAM, arithmetic unit, control circuit, etc.

As microcomputers become cheaper and digital signal processing becomes larger and faster, systems employing a plurality of microcomputers are often designed.

In such systems, in order to efficiently transmit and receive data signals between microprocessors, it is generally adopted to operate them using the same clock. A clock is distributed from a reference oscillator or from a host computer to a plurality of microprocessors, and each microprocessor operates by generating control pulses within the LSI from this clock.

Problems to be Solved by the Invention Due to advances in semiconductor microfabrication technology, the operating speed of microprocessors has increased significantly. Along with this, the clock frequency has increased from several MHz to approximately 20 MHz, and it is expected that the clock frequency will become even faster. When a clock signal of several tens of MHz is distributed to multiple microprocessors, the following problem occurs.

(b) There is a strong possibility that the clock signal will propagate through space and affect other devices. As a countermeasure against this, strict shielding is required.

(b) Clock signal distribution requires the use of coaxial cables or printed circuit boards whose patterns are designed in consideration of distributed constants, which is complicated and requires consideration of impedance matching of signal lines.

(c) The clock signal sending circuit requires a large amount of power. As the frequency increases, the following problems arise regarding synchronization between multiple microprocessors.

That is, as explained with reference to FIG. 3, the clock signal (FIG. 3a) drives one cycle with four pulses. Even if the same clock signal is distributed to multiple microprocessors to operate them, the start and end times of one cycle do not match in each microprocessor. For this reason, data transmission and reception between microprocessors is inefficient.

The present invention has been made in view of these points, and allows the use of a clock with a lower frequency than conventional clocks, and allows multiple microprocessors to operate by synchronizing the start and end times of one cycle. The purpose is to provide a circuit that can obtain

Means for Solving the Problems The present invention delays a pulse applied to one input pin of an integrated circuit that processes digital signals by passing it through a circuit in which a plurality of gates are connected in series to generate an internal pulse. This is a control circuit for an integrated circuit configured to control signal processing of the integrated circuit using pulses applied to input pins and internal pulses.

Operation According to the above-described structure of the present invention, the frequency of the clock signal delivered to each microprocessor can be adjusted by taking a single pulse as input and creating a control pulse using gate delays and logic circuits inside the integrated circuit. is reduced to 74 compared to the conventional one.

Embodiment FIG. 1 shows an embodiment of the present invention, and FIG. 2 is a timing chart explaining its operation. A clock (FIG. 2C) whose period is one cycle is input to input pin 1 of the integrated microprocessor M. Inverter group 11
, 1L21 &5+... Song + ILN (Due to the propagation delay, the output signal of the inverter aH is output from the internal clock (
b) (Fig. 2 d) is obtained. Similarly, other inverter groups b1. b2. b3. ......, bN and' + +
' 2 + ' 3 + """ T CM has internal clocks (b) and (b) shown in Figure 2 (e) and (f).
C) is obtained.

Clock and internal clock (a), (b), (/→ signals to logic circuit (NOR gate) 'NOR+ bNO
By passing R+0yon, the control pulses shown in FIGS. 3(d) to 3(g) can be obtained, and these control pulses are introduced into the control circuit 2. The control circuit 2 controls circuits such as the arithmetic circuit 3.

Effects of the Invention According to the present invention, it is only necessary to deliver the V40 frequency of the conventional clock to each microprocessor, so unnecessary side radiation to other circuits 9 equipment is reduced, and the design of the printed circuit board is also facilitated. Further, the period of the clock used in the present invention corresponds to one cycle of the microprocessor, and since the head of the clock is the starting point of one cycle, data transmission and reception between a plurality of microprocessors can be synchronized.

Furthermore, although the gate delay time varies in accordance with process variations, this does not pose any problem since the processing time within the integrated circuit also varies at the same rate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a control circuit of an integrated circuit according to an embodiment of the present invention, FIG. 2 is a timing diagram explaining its operation, and FIG. 3 is a timing diagram explaining the operation of a conventional microprocessor. . 1...--Input pin, 2...Control circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure

Claims (1)

[Claims] A pulse applied to one input pin of an integrated circuit containing at least an arithmetic circuit and a memory is passed through a circuit in which a plurality of gates are connected in series and delayed to create an internal pulse. A control circuit for an integrated circuit configured to control signal processing of the integrated circuit using an applied pulse and the internal pulse.