JPS62199870U - - Google Patents
Info
- Publication number
- JPS62199870U JPS62199870U JP8807086U JP8807086U JPS62199870U JP S62199870 U JPS62199870 U JP S62199870U JP 8807086 U JP8807086 U JP 8807086U JP 8807086 U JP8807086 U JP 8807086U JP S62199870 U JPS62199870 U JP S62199870U
- Authority
- JP
- Japan
- Prior art keywords
- section
- circuit
- arithmetic
- switching
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010354 integration Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Amplifiers (AREA)
- Filters That Use Time-Delay Elements (AREA)
- Feedback Control In General (AREA)
Description
第１図は本考案のアナログ演算処理回路の構成
ブロツク図、第２図は本考案の第一実施例図、第
３図は本考案の第二実施例図である。
第１図、第２図において、１は演算部、１ａは
加算回路、１ｂは減算回路、１ｃは積分回路、１
ｄは微分回路、２は入力切り換え部、３は出力切
り換え部、４は制御部である。
FIG. 1 is a block diagram of the configuration of an analog arithmetic processing circuit of the present invention, FIG. 2 is a diagram of a first embodiment of the present invention, and FIG. 3 is a diagram of a second embodiment of the present invention. 1 and 2, 1 is an arithmetic unit, 1a is an addition circuit, 1b is a subtraction circuit, 1c is an integration circuit, 1
d is a differential circuit, 2 is an input switching section, 3 is an output switching section, and 4 is a control section.
Claims (1)
微分回路１ｄ等の演算回路からなる演算部１と、 該演算部１の入力部を切り換え、上記の加算回
路１ａ、減算回路１ｂ、積分回路１ｃ、微分回路
１ｄ等の演算回路を選択する入力切り換え部２と
、 該演算部１の演算回路の出力部を入力切り換え
部２と連動して切り換える出力切り換え部３と、 該入力切り換え部２と該出力切り換え部３の切
り換え動作を行わせる制御部４を設け、 制御部４により、入力切り換え部２と出力切り
換え部３の切り換え動作を行うことを特徴とする
アナログ演算処理回路。[Claims for Utility Model Registration] Addition circuit 1a, subtraction circuit 1b, integration circuit 1c,
An arithmetic section 1 consisting of an arithmetic circuit such as a differentiating circuit 1d, and an input switch for switching the input section of the arithmetic section 1 and selecting an arithmetic circuit such as the above-mentioned adding circuit 1a, subtracting circuit 1b, integrating circuit 1c, differentiating circuit 1d, etc. section 2; an output switching section 3 that switches the output section of the arithmetic circuit of the arithmetic section 1 in conjunction with the input switching section 2; and a control section 4 that causes the input switching section 2 and the output switching section 3 to perform switching operations. An analog arithmetic processing circuit characterized in that the control section 4 performs a switching operation between the input switching section 2 and the output switching section 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8807086U JPS62199870U (en) | 1986-06-09 | 1986-06-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8807086U JPS62199870U (en) | 1986-06-09 | 1986-06-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62199870U true JPS62199870U (en) | 1987-12-19 |
Family
ID=30945852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8807086U Pending JPS62199870U (en) | 1986-06-09 | 1986-06-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62199870U (en) |
-
1986
- 1986-06-09 JP JP8807086U patent/JPS62199870U/ja active Pending