JPS62198221A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To obtain a frequency synthesizer to be operated stably and small in phase noise by using a voltage controlled oscillator outputting plural different frequency ranges according to an external switching signal, and a frequency multiplier outputting plural different multiples according to an external switching signal. CONSTITUTION:An output (output frequency = f0) of a voltage controlled oscilla tor 15 and an output (output frequency = f3) of a frequency multiplier 17 are mixed by a mixer 18, from which its difference signal (f0-f3) is outputted. The difference signal (f0-f3) is subject to 1/N division by the 2nd frequency divider 16, from which a frequency (f0-f3)/N is obtained and supplied to a phase comparator 13 as one input. Further, the output of a reference oscillator 11 is subject to 1/M frequency division by the 1st frequency divider 12, the frequency is a frequency fr, which is supplied to the other input of the phase comparator 13, which feeds the comparison output of the said two inputs to a control terminal 1501 of the voltage controlled oscillator 15 via an LPF 14 to constitute a PLL as a whole.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a frequency synthesizer used as an oscillation source in communication equipment and the like.

2. Description of the Related Art A conventional frequency synthesizer will be described below with reference to the drawings. FIG. 4 is a block diagram of a conventional frequency synthesizer, where l is a reference signal oscillator, 2 is a first frequency divider that divides the output of the reference oscillator l, 3 is a phase comparator,
4 is an LPF which is a loop filter; 5 is a voltage controlled oscillator having a control terminal 501 for controlling the oscillation frequency; 6 is a second
7 is a frequency multiplier, and 8 is a mixer.

The operation of the frequency synthesizer configured as described above will be explained below with reference to FIGS. 4, 5, and 6. The oscillation frequency of the voltage controlled oscillator 5 is determined by the control terminal 5.
The frequency multiplier 7 multiplies the output of the reference oscillator 1 and increases the output frequency rn as shown in FIG. Output a fixed frequency. The output of the voltage controlled oscillator 5 (output frequency - ro) and the output of the multiplier 7 (output frequency - f
n) is frequency mixed in the mixer 8, and the difference signal, (
fo-fn) is output. This difference signal output (fo-f
n) is divided by N by the second frequency divider 6, and the frequency <ro-
r. )/N, which becomes the manual power of one side of the phase comparator 3.

Further, the output of the reference oscillator 1 is divided by M by the first frequency divider 2, and the frequency becomes 0, which is the other input of the phase comparator 3. The comparison output is sent to the control terminal 501 of the voltage controlled oscillator 5 via the LPF 4
The PLL is configured as a whole, and the voltage controlled oscillator 5
The output frequency f0 is fo−fn+f,XN. By varying the frequency division number N of the second frequency divider 6, an arbitrary output frequency f can be obtained in the frequency variable step fr. is obtained. (For example, “Telecommunications Research Institute, Research and Practical Application Report” 2nd
Vol. 6, No. 7 (1977) P. 183) Problems to be Solved by the Invention However, in the above configuration, there is a large difference between the frequency division number N for high channels and the frequency division number N for low channels. Therefore, the closed loop transfer characteristics of the PLL are different between the high channel and the low channel, resulting in a problem that the PLL does not operate stably. Furthermore, when the channel is high, the frequency division number N becomes large, so there is a problem in that phase noise due to circuit flicker noise and white noise, which increases in proportion to the square of N, becomes large.

The present invention provides a frequency synthesizer that operates stably over all channels and has low phase noise.

Means for Solving the Problems In order to solve the above problems, the frequency synthesizer of the present invention includes a voltage controlled oscillator that outputs a plurality of different frequency ranges according to an external switching signal, and a plurality of different frequency synthesizers. A frequency multiplier that outputs a multiple is used, and the PLL is selected so that the frequency difference between the outputs of the two devices is minimized.
It constitutes.

Effect of the Invention With the above-described configuration, the present invention reduces the change in the frequency division number N in all channels, thereby stably operating the circuit, and also reduces the maximum value of the frequency division number N, thereby reducing phase noise.

Example Below, regarding a frequency synthesizer according to an example of the present invention,
This will be explained with reference to the drawings.

FIG. 1 is a block diagram of a frequency synthesizer in one embodiment of the present invention, in which 11 is a reference oscillator, 12 is a first frequency divider that divides the output of the reference oscillator 11, 13 is a phase comparator, and 14 is a block diagram of a frequency synthesizer according to an embodiment of the present invention. 15 is a voltage controlled oscillator and a control terminal 1501 is used to control the oscillation frequency.
and a switching terminal 1502 for switching the oscillation frequency range.

16 is a second frequency divider, 17 is a frequency multiplier, and has a switching terminal 1701 for switching the multiplier.

18 is a mixer.

The operation of the frequency synthesizer configured as described above will be explained below with reference to FIGS. 1, 2, and 3. Figure 2 shows the voltage controlled oscillation of Figure 1! This is an example showing the characteristics of aH15, and A and B for the switching signal applied to the switching terminal 1502.

It has three oscillation frequency ranges of C9, and the control terminal 1501
FIG. 3 is an example showing the characteristics of the frequency multiplier 17 shown in FIG. For the signal, the multiple is switched and the output frequency f1
．． f,,f,.

In the following explanation, the voltage controlled oscillator 15 and the multiplier 17 with the characteristics shown in FIGS. 2 and 3 will be used. Do0
For example, the output frequency f shown in FIGS. 2 and 3. In order to obtain
According to the switching signal given to 02, state C in FIG. 2 is set. Further, the frequency multiplier 17 is set to a state C' in which the difference signal frequency between the output frequency of the voltage controlled oscillator 15 and the output frequency of the multiplier W17 is the smallest, according to the switching signal applied to the switching terminal 1701.

Voltage controlled oscillator W! 15 outputs (output frequency - f.) and frequency doubling! The output of 17 (output frequency = r3) is
The frequency is mixed in the mixer 18, and the difference signal (for-r
8) is output, and its difference signal (“.-f8) is the second
The frequency is divided by N by the frequency divider 16, and the frequency (“.-f3)/
N, which becomes one input of the phase comparator 13.

Further, the output of the reference oscillator 11 is input to the first frequency divider 12 by M
The 6-phase comparator 13, which is frequency-divided and becomes the frequency fr and serves as the other one of the phase comparators 13, gives the comparison output of the two inputs to the control terminal 1501 of the voltage-controlled oscillator 15 via the LPF 14, and The output frequency r of the voltage controlled oscillator 15 is configured as a PLL. is f. -f8+fL
It is given as xN. Similarly, other output frequencies f. ′, its output frequency [. ', the state of the voltage controlled oscillator 15 is selected, and the frequency multiplier 17 is set to the state where the difference signal frequency between the output frequency wave number of the voltage controlled oscillator and the frequency multiplier 17 is the smallest. For iA, state Fbf, A ' ka, state gBkJ
IL [fllB'h<, state C' corresponds to state ac) The PLL shown in FIG. 1 is constructed as a whole, and the output frequency f0' of the voltage controlled oscillator 15 is f0'-
It is given as rn4r,×N (n=1 to 3).

As described above, according to this embodiment, a voltage controlled oscillator that outputs a plurality of different frequency ranges according to an external switching signal and a frequency multiplier that outputs a plurality of different frequency ranges according to an external switching signal are used to generate a frequency By configuring the synthesizer, the difference in the number of frequency division numbers N is small in all channels, and the maximum value thereof is also suppressed to a small value, so that it is possible to realize a frequency synthesizer that operates stably and has small phase noise.

In this embodiment, an example is given in which the voltage controlled oscillator and the frequency multiplier have three states, but the present invention is not limited to this.

Effects of the Invention As described above, according to the present invention, it is possible to realize a frequency synthesizer that operates stably over all channels and has low phase noise.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a frequency synthesizer according to an embodiment of the present invention, FIG. 2 is a characteristic diagram of the voltage controlled oscillator shown in FIG. 1, and FIG. 3 is a characteristic diagram of the frequency multiplier shown in FIG.
Figure 4 is a block diagram of a conventional frequency synthesizer, Figure 5 is a block diagram of a conventional frequency synthesizer.
This figure is a characteristic diagram of the voltage controlled oscillator shown in FIG. 4, and FIG. 6 is a characteristic diagram of the frequency multiplier 7 shown in FIG. 5... Voltage controlled oscillator, 7... Frequency multiplier, 15... Voltage controlled oscillator, 17.
...Frequency multiplication device. Name of agent: Patent attorney Toshio Nakao (1 person) Figure 2 Figure 3

Claims (1)

[Claims] The voltage controlled oscillator has a voltage controlled oscillator that outputs a plurality of different frequency ranges according to an external switching signal, and a frequency multiplier that outputs a plurality of different frequency ranges for a reference signal that is input according to an external switching signal. The output frequency of the oscillation device and the output frequency of the frequency multiplier are selected by an external switching signal so that the frequency difference between them is minimized, and the output of the voltage control device and the output of the frequency multiplier are selected by a mixer. A frequency synthesizer characterized in that a signal phase obtained by frequency mixing and dividing the frequency difference signal by N is compared with a signal phase obtained by dividing a reference signal by M, and the comparison output is used as a control voltage of the voltage controlled oscillator. .