JPS62196705A - Method and device for digital sequence control - Google Patents

Method and device for digital sequence control

Info

Publication number
JPS62196705A
JPS62196705A JP3785786A JP3785786A JPS62196705A JP S62196705 A JPS62196705 A JP S62196705A JP 3785786 A JP3785786 A JP 3785786A JP 3785786 A JP3785786 A JP 3785786A JP S62196705 A JPS62196705 A JP S62196705A
Authority
JP
Japan
Prior art keywords
bit
signal
state
execution cycle
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3785786A
Other languages
Japanese (ja)
Inventor
Nobuyuki Yokogawa
横川 信幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3785786A priority Critical patent/JPS62196705A/en
Publication of JPS62196705A publication Critical patent/JPS62196705A/en
Pending legal-status Critical Current

Links

Landscapes

  • Programmable Controllers (AREA)

Abstract

PURPOSE:To execute necessarily and exactly enough a verification of a control operation at every control dye by executing a comparison with a state of the previous execution cycle of a bit signal at every operation cycle of a digital sequence control, executing a report of a varied bit to the outside through communication, etc., and thereafter, executing a check mode operation for executing the next operation. CONSTITUTION:As for a contact point input signal 2, its state is reflected as 1 bit of a contact point input signal bit table 6, a sequence arithmetic unit 9 executes a sequence operation against various bit tables, and its result is reflected in a contact point output signal bit table 7, and becomes a contact point output in the end. By a CRT display device 5 which has been connected by a communication line, a bit signal, etc., of a digital sequence control device 1 are monitored. Also, the titled device is provided with a comparator circuit for detecting a difference of a state of the bit signal which has been monitored at every one execution cycle and a state of the bit signal of the previous execution cycle which has been stored in a retention circuit, and a controlling circuit for executing the next execution after the difference of the bit signal which has been detected by this comparator circuit, to the ontside through communication, etc., or the like.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、化学プロセスや電気設備の制御を行なうデジ
タルシーケンス制御方法及び装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a digital sequence control method and apparatus for controlling chemical processes and electrical equipment.

〔発明の背景〕[Background of the invention]

従来のデジタルシーケンス制御装置は、制御装置内のビ
ット信号の状態をCILT画面等でモニタし、オンであ
るかオフであるかを画面上で見ることによシ、@作の確
認を行なっていたが、制御装置からCRTへの通信速度
は制御演算速度に比して遅いため、信号変化を見逃した
り、CRT上に表示できる信号点数が少ないため全体の
監視が困難であり、完全な動作確認が困難であった。
Conventional digital sequence control devices monitor the status of bit signals within the control device on a CILT screen, etc., and check whether the bit signals are on or off on the screen. However, since the communication speed from the control device to the CRT is slow compared to the control calculation speed, signal changes may be overlooked, and the small number of signal points that can be displayed on the CRT makes overall monitoring difficult, making complete operation confirmation difficult. It was difficult.

〔発明の目的〕[Purpose of the invention]

本発明は、制御周期毎の制御演算の検証を必要かつ十分
正確に行表えるデジタルシーケンス制御方法、及び、こ
のようなチェック機能付のデジタルシーケンス:1il
J御装fiを提供可能とすることを目的とするものであ
る。
The present invention provides a digital sequence control method that can perform necessary and sufficiently accurate verification of control calculations for each control cycle, and a digital sequence control method with such a check function.
The purpose is to make it possible to provide J-style fi.

〔発明の峨要〕[The key to the invention]

本発明のデジタルシーケンス制御方法は、外部から接点
人力を取り込み、シーケンス演算を行ない、演算結果の
接点出力を外部に出力する制御を周期的に実行するデジ
タルシーケンス制御装置において、人力信号、出力信号
、演算中間信号などのビット信号を、一実行周期毎にモ
ニタし、モニタした該ビット信号の状態と前実行周期の
ビット信号の状態との差を通信等を介して外部に報告し
た後、次の実行を行なうことを特徴とし1本発明のデジ
タルシーケンス制御装置は、外部から接点入力を取り込
み、シーケンス演算を行ない、演算結束の接点出力を外
部に出力する制御を周期的に実行するデジタルンーケン
ス!!+11?KI装置においで、人力信号、出力信号
、演算中間イg号などのビット信号を、一実行周期ごと
に記憶してpく記憶回路と、一実行周期ごとにモニタし
た前記ビット信号の状態と前記記憶回路に記憶されてい
る前実行周期のビット信号の状態との差を検出する比較
回路と、該比較回路で検出された前記ビット信号の差を
通信等を介して外部に報告し丸後次の実行を行なり制御
回路と、該制御回路への切換えを行なう切替スイッチと
全−有することを%微とするものである。
The digital sequence control method of the present invention is a digital sequence control device that periodically executes control to take in human contact power from the outside, perform sequence calculations, and output the contact outputs of the calculation results to the outside. Bit signals such as calculation intermediate signals are monitored every execution cycle, and the difference between the monitored bit signal state and the bit signal state of the previous execution cycle is reported to the outside via communication, etc., and then the next 1. The digital sequence control device of the present invention is a digital sequence control device that periodically executes control that takes in contact input from the outside, performs sequence calculation, and outputs the contact output of the calculation unit to the outside! ! +11? In the KI device, there is a storage circuit that stores bit signals such as human input signals, output signals, and calculation intermediate signals for each execution cycle, and a storage circuit that stores bit signals such as human input signals, output signals, and operation intermediate signals, and stores the states of the bit signals monitored every execution cycle and the A comparison circuit detects the difference between the state of the bit signal of the previous execution cycle stored in the memory circuit, and the difference between the bit signal detected by the comparison circuit is reported to the outside via communication etc. It is assumed that the control circuit includes a control circuit for carrying out the execution of the control circuit, and a changeover switch for switching to the control circuit.

本発明は、デジタルシーケンス制御の演算周期毎にビッ
ト信号の前実行周期の状態との比較を行ない、変化した
ビットの報告を過信等を経由して外部に行なった後に1
次の演JIを行なうようなチェックモード動作を実行し
、目的を達成するようにしたものである。
The present invention compares the bit signal with the state of the previous execution cycle every calculation cycle of digital sequence control, reports changed bits to the outside via overconfidence, etc.
The purpose is achieved by executing check mode operations such as performing the next JI.

〔発明の実施例〕[Embodiments of the invention]

以下、実施例について説明する。 Examples will be described below.

第1〜第3図は一実施例の説明図で、第1図はデジタル
シーケンス制御装置とCRTメツセージ表示装置が通信
で接続されている状態を示し、第2図は第1図のデジタ
ルシーケンス制御装置の内部構成を示し、第3図は制御
演算とチェックモード時の動作の関係を示している。こ
れらの図で。
1 to 3 are explanatory diagrams of one embodiment, in which FIG. 1 shows a state in which a digital sequence control device and a CRT message display device are connected through communication, and FIG. 2 shows the digital sequence control of FIG. 1. The internal configuration of the device is shown, and FIG. 3 shows the relationship between control calculations and operations in check mode. In these diagrams.

1はデジタルシーケンス制御装置、2は接点入力信号、
3け接点出力信号、4は通信回線、5はCRT表示装置
tを示しており、6,7.8及び9は、それぞれ、デジ
タルシーケンス制御装置1の接点入力信号ビットテーブ
ル、接点出力信号ビットテーブル、中間信号ビットテー
ブル及びシーケンス演保装崖金示している。
1 is a digital sequence control device, 2 is a contact input signal,
3 contact output signals, 4 is a communication line, 5 is a CRT display device t, 6, 7, 8 and 9 are a contact input signal bit table and a contact output signal bit table of the digital sequence control device 1, respectively. , the intermediate signal bit table and sequence performance information are shown.

このデジタルシーケンス制御装[11では、接点入力信
号2は接点人力信号ビットテーブル6の1ビツトとして
状態が反映され、シーケンス演算装[9は各種ビットテ
ーブルとの間でシーケンス演)!Lを行ない、結果を接
点出力信号ビットテーブル7に反映し、最終的に接点出
力となる。そして。
In this digital sequence control device [11], the state of the contact input signal 2 is reflected as one bit of the contact manual signal bit table 6, and the sequence operation device [9 performs sequence operations with various bit tables]! L is performed, the result is reflected in the contact output signal bit table 7, and finally becomes a contact output. and.

通信回線で接続されたCR,T表示装置t5でデジタル
シーケンス制御装置lのビット信号等を監視することか
できる。
The bit signals etc. of the digital sequence control device 1 can be monitored using the CR and T display device t5 connected through a communication line.

そして、このシーケンス、演算装置は、例えば。This sequence and arithmetic device are, for example.

人力信号、出力信号、演算中間信号などのビット信号ヲ
ー寿行周期ごとに記憶しておく保存回路と、一実行周期
ごとにモニタしたビット信号の状態と保存回路に記憶さ
れている前実行周期のビット信号の状態との差を検出す
る比較回路と、この比較回路で検出されたビット信号の
差を通信等を介して外部に報告した後1次の実行を行な
う制御回路と、この制御回路のオン・オフを行なうチェ
ックスイッチとから構成されるが、コンピューターを用
いて実施することもできる。、 次に、このデジタルシーケンス1ffll m装置を用
いた制御方法における制御演算を第3図を用いて説明す
る。チェックスイッチが、オフの時(a)は通常の制御
が行なわれ、 1ttlJffll演K(b)の結果は
そのままCR,T表示装置5に送られる。チェ、ツクス
イッチがオンの1寺(C)には、この発明のデジタルノ
ーケンス制御方法が行なわれる。すなわち、チェックス
イッチがオンの時(C)には、接点入出力及び中間借号
ビットテーブル6.7.8の前回値からの変化をすべて
とらえ、どのビットがどう変ったかをCRT表示袈置装
に報告しくd)、報告が完了してから次の制御演算が行
なわれる。
A storage circuit that stores bit signals such as human input signals, output signals, and calculation intermediate signals for each execution cycle, and the state of the bit signal monitored for each execution cycle and the bits of the previous execution cycle that are stored in the storage circuit. A comparison circuit that detects the difference in the state of the signal, a control circuit that performs the first execution after reporting the difference between the bit signals detected by this comparison circuit to the outside via communication, etc., and a control circuit that performs the first execution of the control circuit - It consists of a check switch that turns off the system, but it can also be implemented using a computer. Next, the control calculations in the control method using this digital sequence 1ffllm device will be explained using FIG. When the check switch is off (a), normal control is performed, and the result of the 1ttlJffll operation K (b) is sent as is to the CR,T display device 5. The digital no-kense control method of the present invention is carried out in the case (C) where the check switch is on. In other words, when the check switch is on (C), all changes from the previous values in the contact input/output and intermediate bit table 6.7.8 are captured, and the CRT display shows which bits have changed and how. d), and the next control calculation is performed after the reporting is completed.

このデジタルシーケンス制御方法によれば、外部からの
入力が変化した時、どのような変化がどの信号に発生し
たかを完全にメツセージで確認できるため1人間がラン
プやCRT上での信号状態表示によって状況を確認する
のに比較して、完全に確認することができ、さらに確認
の能率が大幅に向上するなどの効果がある。
According to this digital sequence control method, when an external input changes, it is possible to completely check what kind of change has occurred in which signal using messages, so one person can check the signal status by displaying the signal status on a lamp or CRT. Compared to checking the situation, it can be completely confirmed, and the efficiency of confirmation is greatly improved.

〔発明の効果〕〔Effect of the invention〕

本発明は、制御周期毎の制御演算の検証を必要かつ十分
正確に行なえるデジタルシーケンス制御方法、及び、こ
のようなチェック機能付のデジタルシーケンス制御装置
を提供可能とするもので、産業上の効果の犬なるもので
ある。
The present invention makes it possible to provide a digital sequence control method that can perform necessary and sufficiently accurate verification of control calculations for each control cycle, and a digital sequence control device with such a check function, and has industrial effects. It is a dog.

【図面の簡単な説明】[Brief explanation of drawings]

8g1図は、本発明のデジタルシーケンス制御装置の一
実施例の説明図、第2図は同じく内部構成を示す説明図
、第3図は同じく制御演算とチェックモード時の動作の
関係を示す説明図である。 ■・・・デジタルシーケンス制御装置、2・・・接点入
力信号、3・・・接点出力信号、4・・・通信回線、5
・・・CRT表示装置、6・・・接点入力信号ビットテ
ーブル、7・・・接点出力信号ビットテーブル、8・・
・中間(ほか1名)
Fig. 8g1 is an explanatory diagram of an embodiment of the digital sequence control device of the present invention, Fig. 2 is an explanatory diagram showing the internal configuration, and Fig. 3 is an explanatory diagram showing the relationship between control calculations and operations in check mode. It is. ■...Digital sequence control device, 2...Contact input signal, 3...Contact output signal, 4...Communication line, 5
. . . CRT display device, 6 . . Contact input signal bit table, 7 . . . Contact output signal bit table, 8 . .
・Intermediate (1 other person)

Claims (1)

【特許請求の範囲】 1、外部から接点入力を取り込み、シーケンス演算を行
ない、演算結果の接点出力を外部に出力する制御を周期
的に実行するデジタルシーケンス制御装置において、入
力信号、出力信号、演算中間信号などのビット信号を、
一実行周期毎にモニタし、モニタした該ビット信号の状
態と前実行周期のビット信号の状態との差を通信等を介
して外部に報告した後、次の実行を行なうことを特徴と
するデジタルシーケンス制御方法。 2、外部から接点入力を取り込み、シーケンス演算を行
ない、演算結果の接点出力を外部に出力する制御を周期
的に実行するデジタルシーケンス制御装置において、入
力信号、出力信号、演算中間信号などのビット信号を、
一実行周期ごとに記憶しておく保存回路と、一実行周期
ごとにモニタした前記ビット信号の状態と前記保存回路
に記憶されている前実行周期のビット信号の状態との差
を検出する比較回路と、該比較回路で検出された前記ビ
ット信号の差を通信等を介して外部に報告した後次の実
行を行なう制御回路と該制御回路への切換えを行なう切
換スイッチとを有することを特徴とするデジタルシーケ
ンス制御装置。
[Claims] 1. In a digital sequence control device that periodically executes control to take in contact input from the outside, perform sequence calculation, and output contact output as a result of the calculation to the outside, input signal, output signal, calculation bit signals such as intermediate signals,
A digital device characterized in that it monitors every execution cycle, reports the difference between the monitored bit signal state and the bit signal state of the previous execution cycle to the outside via communication, etc., and then performs the next execution. Sequence control method. 2. In a digital sequence control device that periodically executes control that takes in contact input from the outside, performs sequence calculation, and outputs the contact output of the calculation result to the outside, bit signals such as input signals, output signals, calculation intermediate signals, etc. of,
A storage circuit that stores information for each execution cycle; and a comparison circuit that detects the difference between the state of the bit signal monitored for each execution cycle and the state of the bit signal of the previous execution cycle that is stored in the storage circuit. and a control circuit that performs the next execution after reporting the difference between the bit signals detected by the comparison circuit to the outside via communication, etc., and a changeover switch that switches to the control circuit. Digital sequence control device.
JP3785786A 1986-02-22 1986-02-22 Method and device for digital sequence control Pending JPS62196705A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3785786A JPS62196705A (en) 1986-02-22 1986-02-22 Method and device for digital sequence control

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3785786A JPS62196705A (en) 1986-02-22 1986-02-22 Method and device for digital sequence control

Publications (1)

Publication Number Publication Date
JPS62196705A true JPS62196705A (en) 1987-08-31

Family

ID=12509212

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3785786A Pending JPS62196705A (en) 1986-02-22 1986-02-22 Method and device for digital sequence control

Country Status (1)

Country Link
JP (1) JPS62196705A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010195204A (en) * 2009-02-25 2010-09-09 Toyo Tire & Rubber Co Ltd Pneumatic tire

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5659397A (en) * 1979-10-19 1981-05-22 Hitachi Ltd Status change detection in information monitor system
JPS58103021A (en) * 1981-12-15 1983-06-18 Fujitsu Ltd Status display system for teminal machine
JPS58169256A (en) * 1982-03-31 1983-10-05 Nec Corp Operation analyzing device
JPS60229117A (en) * 1984-04-25 1985-11-14 Omron Tateisi Electronics Co Programmable controller

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5659397A (en) * 1979-10-19 1981-05-22 Hitachi Ltd Status change detection in information monitor system
JPS58103021A (en) * 1981-12-15 1983-06-18 Fujitsu Ltd Status display system for teminal machine
JPS58169256A (en) * 1982-03-31 1983-10-05 Nec Corp Operation analyzing device
JPS60229117A (en) * 1984-04-25 1985-11-14 Omron Tateisi Electronics Co Programmable controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010195204A (en) * 2009-02-25 2010-09-09 Toyo Tire & Rubber Co Ltd Pneumatic tire

Similar Documents

Publication Publication Date Title
JPS62196705A (en) Method and device for digital sequence control
CN211018860U (en) Novel network switch
CN108444660B (en) Nitrogen leakage fault diagnosis method, device and system
JP2757455B2 (en) Transmission line switching device
JPH0391005A (en) Monitor device for programmable controller
JPS58116897A (en) Time-division multiplex transmission system
JP3550442B2 (en) Encoder signal communication method
JPH0731308Y2 (en) Duplex device
JPH04329098A (en) Remote monitor
JPH04284540A (en) Data check circuit
JPS61169036A (en) System supervisory device
SU1448338A1 (en) Programmable controller
JPS6265199A (en) Fault display unit
JPS6013591B2 (en) Multi-point scanning method
JPS6316275A (en) Integrated circuit with internal state monitoring output circuit
JPH03201845A (en) Abnormality generating position detector for serial controller
JPS5819097B2 (en) Computer system monitoring method
JPS6260439A (en) State detector
JPS61114344A (en) Fault diagnosis system
JPH03177193A (en) Digital control monitor system
JPS6358544A (en) Electronic computer system
JPH03260743A (en) Information generation/restoration detecting circuit
JPS63215139A (en) Detecting system for fault of signal in balanced double-current interchange
JPS63223808A (en) Trouble diagnosing device
JPH02228898A (en) Polling supervisory system