JPS62195923A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent latch up of a CMOS inverter circuit due to a surge voltage inputted from an external terminal by providing a transmission gate between an output terminal of the CMOS inverter circuit and an external terminal connected with the said inverter circuit and providing a clamp circuit between its external terminal and a ground potential. CONSTITUTION:The transmission gate comprising an N-channel MOSFET whose gate is connected to a power supply voltage Vcc is provided between the external terminal P2 and the output terminal of the CMOS inverter circuit comprising a P-channel MOSFET Q1 and an N-channel MOSFET Q2. Further, a clamp circuit comprising a MOSFET Q4 of diode connection is provided between the terminal P2 and the ground potential. With a surge voltage higher than the power supply voltage Vcc inputted to the terminal P2, the potential of the output terminal of the CMOS inverter circuit is limited to a voltage level of Vcc-Vth (Vth is a threshold voltage of a MOSFET Q5) and when a negative surge voltage is fed to the terminal P2, the voltage level is controlled to nearly the ground potential. Thus, the latchup of the CMOS inverter circuit is prevented.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, such as a one-chip microcomputer or gate array having an oscillation circuit configured by CMOS (complementary MO3). It is related to effective technology that can be used for.

[Conventional technology]

For connection circuits using CMO3, for example, 198
It is described on page 334 of the ``Hitachi 4-bit Single Chip Microcomputer Data Book J'' published by Hitachi, Ltd. in 1995.

FIG. 3 shows a connection circuit for constructing the oscillation circuit of the microcomputer.

In the figure, a P-channel MOSFET QI and an N-channel MOSFET Q2 constitute a CMOS inverter circuit. This CMOS inverter circuit has an oscillation circuit O
It operates as an inverting amplifier circuit constituting the SC. The above commercial
The input terminal and output terminal of the OS inverter circuit are coupled to external terminals PL and P2. These external terminals P1 and P2
A bias resistor Rf for setting the amplification operating point of the CMOS inverter circuit and a crystal resonator Xta are provided between
An external circuit network consisting of I and capacitors CL1 and Cl3 is provided, and constitutes an oscillation circuit together with the CMOS inverter circuit.

The output signal of the CMOS inverter circuit is passed through an inverter circuit IVI to a clock generation circuit CP (not shown).
This will be communicated to G.

[Problem that the invention seeks to solve]

As described above, the inventors of the present invention have found that conventional oscillation circuits in which the output terminal of the CMO 3 is directly connected to an external terminal have the following problems. That is, there is a possibility that the CMOS inverter circuit may enter a latch-up state due to a surge voltage or the like input via the external terminal P2. The reason for this is that the CMO in Figure 4
As shown in the schematic cross-sectional view of the three circuits, the parasitic PNP transistor Qa and the parasitic NPN transistor Qb are configured in the form of a parasitic transistor. That is, the above parasitic PNP) run risk Qa is formed on the surface of the semiconductor substrate N-3UB and is caused by the P+ region constituting the drain region of the P-channel MOSFET which is commonly connected to the drain region of the N-channel MOSFET, and the power supply voltage VC of the circuit.
The P+ region constituting the source region of the P-channel MO5FET connected to C is the emitter, and the semiconductor substrate N-5
The base is UB, and the well region P-WELL for forming an N-channel MOS FET is used as a collector. On the other hand, the parasitic NPN) run risk Qb is an N-channel M formed on the surface of the P-type well region P-WELL and connected to the ground potential point GND of the circuit.
The N middle region constituting the source region of the OS FET is used as an emitter, the well region P-WELL is used as a base, and the semiconductor substrate N-5UB is used as a collector.

Also, a bias voltage Vcc is applied to the semiconductor substrate N-3UB.
An equal-layer resistance Rs in the semiconductor substrate N-3UB is formed between the N medium region constituting the ohmic contact region for supplying the ohmic contact region and the base of the parasitic PNP l-run risk Qa. A well region P-WELL is located between the P+ region constituting an ohmic contact region for supplying the ground potential GND to the well region P-WELL and the base of the parasitic NPN l-run risk Qb.
An equal layer resistance Rw is formed at .

Therefore, in the above CMO3 input circuit, a surge voltage higher than the power supply voltage VCC is applied to the P-channel MO5FETQI and the N-channel MO5FETQ via the external terminal P2.
When input to common connection node a of 2, parasitic PNP)
The emitter and base of the run risk Qa are in a forward bias state. As a result, the parasitic PNP run risk Qa is turned on, a collector current flows through the equal-layer resistor Rw, and the parasitic NPNI transistor Qb is turned on. Therefore, the parasitic PNP transistor Qa continues to be in the on state due to the collector current of the parasitic NPN l-run risk Qb flowing through the equal-layer resistor Rs, resulting in a latch-up in which a current constantly flows from the power supply voltage VCC to the circuit ground potential GND. It becomes a state.

Such a rough lump is a P-channel MOSFET.
A similar problem occurs when a negative surge voltage is input to node a in a parasitic PNP l-run risk whose emitter is the source of the transistor and a parasitic NPN transistor whose emitter is the drain of the N-channel MOSFET.

In order to prevent the above latch amplifier, the above P-channel MOSFETQI and N-channel MOSFETQ
2, the required area on the semiconductor substrate for these circuits becomes so large that it cannot be ignored.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device that prevents rough drop using a simple circuit configuration.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows. That is,
Between the output terminal of the CMOS inverter circuit and the external terminal to which it is connected, its gate is connected to the power supply voltage VCC.
A transmission gate is provided using an N-channel MOSFET connected to the terminal, and a clamp circuit using a MOSFET in the form of a diode is provided between the external terminal and the ground potential.

[For production]

According to the above means, when a surge voltage higher than the power supply voltage VCC is input to the external terminal P2, the potential of the output terminal of the CMOS inverter circuit is Vcc-Vth (Vt
h is N provided between the output terminal of CMO5 and the external terminal.
If a negative surge voltage is input to the external terminal P2, the CMOS inverter circuit will latch. This can prevent the device from becoming in an up state.

〔Example〕

FIG. 2 shows a block diagram of an embodiment of a one-chip microcomputer to which the present invention is applied.

In the figure, the area surrounded by a broken line is a semiconductor LSI (Large Scale Integrated Circuit), and each circuit block formed here constitutes a 1-chip microcomputer as a whole, and is a known CMOS semiconductor integrated circuit. It is formed on a single semiconductor substrate, such as silicon, using the same manufacturing technology.

The symbol CPU indicates a microprocessor, which includes an arithmetic unit, an accumulator, various registers, and the like. Various devices are connected to this microprocessor CPU via an input/output bus BUS. This input/output bus BUS includes a data bus and an address bus.

The input/output port designated by the symbol I10 includes a data transmission direction register therein. Also,
Ports shown with symbols are input-only ports.

The symbol RAM is a random access memory, which is mainly used as a temporary storage circuit for a program being executed or data in the middle of an operation. The memory indicated by the symbol ROM is a read-only memory in which programs for various information processing, dictionary data, etc. are stored. The RAM and ROM include control circuits necessary for read and write operations of the storage elements.

The symbol oSC indicates an oscillation circuit, which forms an oscillation signal having a highly accurate oscillation frequency using a crystal resonator Xtal or the like externally connected to the CMOS inverter circuit, as will be described later. This oscillation signal is supplied to the clock generation circuit CPG, where the microprocessor C
The required clock pulses at the PU are formed.

FIG. 1 shows a circuit diagram of an embodiment of an oscillation circuit oSC including the CMOS inverter circuit. In the same figure, MOS F with an arrow added to the channel part
The ET is of the P-channel type, distinguishing it from the N-channel MO5FET, which has no arrow.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single crystal N-type silicon. P channel part
SFET consists of a source region, a drain region formed on the surface of a semiconductor substrate, and polysilicon formed on the surface of the semiconductor substrate between the source region and the drain region with a thin gate insulating film interposed therebetween. It consists of a gate electrode. N-channel MOS FET is
It is formed in a P-type well region formed on the surface of the semiconductor substrate. Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of P-channel MOSFETs formed thereon. The P-type well region constitutes the substrate gate of the N-channel MOSFET formed thereon.

Typically, a CMOS inverter circuit uses external terminals P1 and P
2, it is connected to an external circuitry consisting of an external crystal resonator Xtal, a bias resistor Rf, and load capacitances CLI and Cl3. As a result, the CMOS inverter circuit is brought into operation and performs an oscillation operation at an oscillation frequency set by the constants of the external circuitry such as the bias resistor Rf.

The output signal of the CMOS inverter circuit is inverter circuit I
Via VI, it is sent to the clock pulse generation circuit CPG,
A number of clock pulses required by a microprocessor CPU etc. are generated.

Between the external terminals P1 and P2 and the ground potential of the circuit, there is an N-channel MOSF in the form of a diode with its gate and source commonly connected to prevent electrostatic damage.
ETQ3 and Q4 are connected. In addition, external terminal P2
A transmission gate formed by an N-channel MO5FETQ5 whose base is connected to the power supply voltage VCC is provided between the output node a of the CMOS inverter circuit and the output node a of the CMOS inverter circuit.

These N-channel MOS FETs Q3 to Q5 use output circuits and protection circuits that are standardly provided in general gate arrays and the like.

Surge voltages at external terminals, high-voltage static electricity, etc., which cause the CMOS inverter circuit to enter a languid state, are clamped by these N-channel MOSFETs, and ruff-up can be prevented. That is,
Surge voltages higher than the power supply voltage VCC input to the external terminal P2 are removed by the N-channel MO5FET Q5 whose gate is connected to the power supply voltage VCC.
-V th (vth is N-channel MOSFETQ5
(threshold voltage). In addition, the negative surge voltage input to external terminals P1 and P2 is absorbed by diode-type N-channel MOSFETs Q3 and Q provided between each external terminal and the circuit ground potential.
4, it is clamped to the voltage level of ground potential. Thereby, it is possible to prevent the rough stub as described above with reference to the schematic cross-sectional view of the CMO3 integrated circuit shown in FIG.

As shown in the above embodiment, when the present invention is applied to an oscillation circuit of a one-chip microcomputer, the following effects can be obtained. That is, (11CM) A transmission gate formed by an N-channel MOSFET whose gate is connected to the power supply voltage VCC is provided between the output terminal of the 11CM OS inverter circuit and the external terminal to which it is to be connected, and the transmission gate is connected to the external terminal and ground. By providing a clamp circuit using a MOSFET in the form of a diode between the potential and the potential, the potential of the output terminal of the CMOS inverter circuit is set to the power supply voltage VC at the external terminal P2.
If a surge voltage higher than C is input, VCCVt
h (N provided between the output terminal of CMO8 and the external terminal
If a negative surge voltage is input to external terminal P2, it will be limited to the ground potential.
This has the effect of preventing the CMOS inverter circuit from entering a latch-up state.

(2) The N-channel MOSFET described in item 11 above can be easily realized because the output MOSFET and protection circuit that are standardly provided for each external terminal of a general gate array etc. can be used as they are. You can get the effect that you can.

(3) According to (1) and (2) above, P-channel MOS of CMOS inverter 1@ connected to external terminals
Since there is no need to increase the layout distance between the FET and the N-channel MOS FET, it is possible to improve the degree of integration of the integrated circuit.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in FIG. 1, N-channel MOSFET Q5 has external terminal P2
and the power supply voltage ■cc, the potential of external terminal P2 is VCC.
It may also be an N-channel MOS FET in the form of a diode, which conducts when the voltage is higher than .

In addition, the CMO3 circuit has all the conductivity types of the above embodiments reversed, that is, an N-channel MOSFET on a P-type substrate.
ET is formed and P channel MO5F is formed in the N type well region.
It may also form an ET. In this case, the polarity of the power supply voltage may be changed accordingly, and the conductivity type of the MOSFET constituting the latch-up prevention circuit may also be changed.

In the above explanation, the invention made by the present inventor was mainly explained in the case where it was applied to the oscillation circuit of a one-chip microcomputer, which is the field of application that formed the background of the invention, but the invention is not limited thereto. It can be used to prevent latch-up of CMO3 circuits in gate arrays, etc. The present invention can be used to prevent latch-up in a semiconductor integrated circuit device configured such that at least the output terminal of a CMOS inverter circuit is connected to an external terminal.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, the output terminal of the CMOS inverter circuit,
Between the external terminal to which it is connected, an N-channel MOS F whose gate is connected to the power supply voltage V CC
In addition to providing a transmission gate using ET, a MOS in the form of a diode is connected between the external terminal and the ground potential.
By providing a clamp circuit using FET, C
By limiting the potential of the output terminal of the MOS inverter circuit, CMO due to surge voltage input from the external terminal, etc.
This can prevent latch-up of the S inverter circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the oscillation circuit of a microcomputer to which the present invention is applied, FIG. 2 is a block diagram of a one-chip microcomputer including the oscillation circuit of FIG. 1, and FIG. , a circuit diagram of an oscillation circuit of a conventional one-chip microcomputer, and FIG. 4 is a schematic cross-sectional view of a CMO3 integrated circuit for explaining latch-up. Ql...P channel MOSFET, Q2~Q5...
・N-channel MOSFET, IVI...Inverter circuit, Xtal...Crystal resonator, Rf...Bias resistance, CLI, Cl3...-Load capacitance, Pl, P
2...external terminal, CPU...microprocessor,
OSC...Oscillation circuit, CPG...Clock pulse generation circuit, ROM--Read only memory, RA
M...Random access memory, Ilo...I/O port, ■...Input port, Figure 1, Figure 2

Claims (1)

[Claims] 1. P-channel MOSFET and N-channel MOSF
A CMOS inverter circuit consisting of ET and the above CMOS
provided between the commonly connected drains of two MOSFETs constituting the inverter circuit and the first external terminal,
a first voltage limiting circuit for suppressing the potential of the commonly connected drains below a first power supply voltage; and a second voltage limiting circuit for suppressing the potential of the commonly connected drains above a second power supply voltage. 1. A semiconductor integrated circuit device comprising: a latch-up prevention circuit constituted by a limiting circuit; 2. The first power supply voltage is a power supply voltage V_C_C such as +5 volts, the second power supply voltage is the ground potential of the circuit such as 0 volts, and the gate of the first voltage limiting circuit is connected to the power supply voltage. an N-channel M connected to the voltage V_C_C and whose source and drain are respectively connected to the first external terminal and the output terminal of the CMOS inverter circuit;
The second voltage limiting circuit is composed of a transmission gate using an OSFET, and the second voltage limiting circuit is an N-channel MOSFET in the form of a diode provided between the first external terminal and the circuit ground potential.
A semiconductor integrated circuit device according to claim 1, characterized in that the semiconductor integrated circuit device is comprised of: 3. Two MOs forming the above CMOS inverter circuit
The commonly connected gates of the SFETs are connected to a second external terminal, and an external circuit network forming an oscillation circuit is connected between the first and second external terminals. A semiconductor integrated circuit device according to claims 1 and 2.