JPS62195189A - Superconducting three-terminal device - Google Patents

Superconducting three-terminal device

Info

Publication number
JPS62195189A
JPS62195189A JP61035239A JP3523986A JPS62195189A JP S62195189 A JPS62195189 A JP S62195189A JP 61035239 A JP61035239 A JP 61035239A JP 3523986 A JP3523986 A JP 3523986A JP S62195189 A JPS62195189 A JP S62195189A
Authority
JP
Japan
Prior art keywords
layer
base
type
base layer
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61035239A
Other languages
Japanese (ja)
Inventor
Keiichi Tanabe
圭一 田辺
Osamu Michigami
修 道上
Yujiro Kato
加藤 雄二郎
Hidefumi Asano
秀文 浅野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP61035239A priority Critical patent/JPS62195189A/en
Publication of JPS62195189A publication Critical patent/JPS62195189A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/10Junction-based devices
    • H10N60/128Junction-based devices having three or more electrodes, e.g. transistor-like structures

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  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

PURPOSE:To improve a signal amplification factor by a method wherein a base layer is composed of an Nb or NbN layer provided on a collector layer composed of diamond structure Sn, GaSb, InSb, InAs, CdS, CdSe, PbTe and In1-xGaxAs mixed crystal or InSb1-yAsy mixed crystal. CONSTITUTION:An Nb layer is formed by CVD on a single crystal substrate 1 made of p-type GaSb, non-doped (n-type) InSb, p-type InAs, n-type CdS, n-type CdSe or n-type PbTe. Then a base pattern 2 composed of the Nb layer is formed from the Nb layer by reactive ion etching. Further, after an insulating layer 3 made of SiO2 is deposited over the whole surface of the substrate by vacuum evaporation, windows are formed in the insulating layer 3 on the base layer 2 and an emitter electrode 5 made of Nb is formed on the base layer 2 with a barrier layer 4 between by lifting-off and a base electrode 6 made of Nb is formed on the base layer 2 by lifting-off. Finally, a collector electrode 7 is formed in the window which is formed in the insulating layer 3 and exposes the substrate 1. With this constitution, a current transfer factor can be improved.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は半導体バイポーラトランジスタと類似の信号増
幅作用及びスイッチング動作を行なう超伝導デバイスに
関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a superconducting device that performs signal amplification and switching operations similar to semiconductor bipolar transistors.

〔従来の技術〕[Conventional technology]

超伝導を利用したスイッチングデバイスとしては、従来
ジョセフソントンネリング素子(ジョセフソン素子)が
その高速性のために集積回路への適用が検討されてきた
。しかしながら、ジョセフソン素子は2端子素子であり
、それ自体は信号増幅作用をもたないため、メモリ回路
や論理回路を構成する際、回路が半導体トランジスタを
使用した場合に較べ複雑になるばかりでなく、動作マー
ジンが小さいため大規模集積が困難であった。
As a switching device using superconductivity, Josephson tunneling devices (Josephson devices) have been considered for application to integrated circuits due to their high speed performance. However, the Josephson element is a two-terminal element and does not itself have a signal amplification effect, so when configuring a memory circuit or logic circuit, the circuit is not only more complicated than when semiconductor transistors are used. However, large-scale integration was difficult due to the small operating margin.

そこで、半導体トランジスタと類似の信号増幅作用、ス
イッチング動作を実現するため、超伝導体を使用した種
々の三端子デバイスが提案されている。例えば、第3図
に示すように、超伝導体層21に準粒子を注入するため
のエミッタ接合22(バリア層を介した超伝導体−常伝
導金属、超伝導体−超伝導体トンネル接合、あるいは超
伝導体−半導体接触で構成される)と、該超伝導体21
から準粒子を捕獲するためのコレクタ接合23(主とし
て超伝導体−半導体接触で構成される)を具備する超伝
導三端子デバイス(特開昭60−117691号公報、
あるいは特開昭60−231375号公報)が知られて
いる。これらのデバイスではエミッタから注入した準粒
子のコレクタへの流れを制御することにより、半導体バ
イポーラトランジスタと類似の動作をさせることができ
る。また、これらのデバイスは薄いベース層をキャリア
がパリスティックに走行するホットエレクトロントラン
ジスタ(例えば、ニス、エム、ツエ(S、M、5ZE)
; “フィジックス・オブ セミコンダクタ・デバイセ
ス(Physics of Sem1conducto
r Devices)”、 (ジョン ライレイ エン
ド サンプ インク)  (JohnVilley &
 5ons Inc、)、 N、 Y、、 pp、 5
87−613参照)のベース層に超伝導体を用いたもの
と考えられるが、準粒子のベース中での速度がフェルミ
速度(〜1010l1/5ee)に近いためベース走行
時間が短いのに加え、ベースには外部から超伝導電流が
いわば抵抗零の状態で流れるので、ベース抵抗とベース
−コレクタ間容量の積で表わされる信号遅延が非常に小
さく、ベース層を半導体や常伝導金属としたホットエレ
クトロントランジスタや通常のバイポーラトランジスタ
に比べて優れた高周波特性(高速スイッチング特性)が
期待できる。
Therefore, various three-terminal devices using superconductors have been proposed to achieve signal amplification and switching operations similar to those of semiconductor transistors. For example, as shown in FIG. 3, an emitter junction 22 for injecting quasi-particles into the superconductor layer 21 (superconductor-normal metal, superconductor-superconductor tunnel junction via a barrier layer, or a superconductor-semiconductor contact) and the superconductor 21
A superconducting three-terminal device comprising a collector junction 23 (mainly composed of a superconductor-semiconductor contact) for capturing quasiparticles from
JP-A No. 60-231375) is also known. These devices can operate similar to semiconductor bipolar transistors by controlling the flow of quasiparticles injected from the emitter to the collector. In addition, these devices are hot electron transistors (e.g., Niss, M, 5ZE) in which carriers travel pallistically through a thin base layer.
“Physics of Semiconductor Devices
r Devices)”, (John Riley End Sump Inc.) (John Villagey &
5ons Inc,), N, Y,, pp, 5
It is thought that a superconductor is used in the base layer of the base layer (see 87-613), but in addition to the fact that the velocity of the quasiparticle in the base is close to the Fermi velocity (~1010l1/5ee), the base transit time is short. Since a superconducting current flows from the outside into the base with zero resistance, the signal delay represented by the product of the base resistance and the base-collector capacitance is extremely small, and hot electrons with a semiconductor or normal metal base layer are It can be expected to have superior high-frequency characteristics (high-speed switching characteristics) compared to transistors and normal bipolar transistors.

一方、この種のデバイスの問題点は準粒子のコレクタ捕
獲率(電流伝達率α)がバイポーラトランジスタに比べ
、一般的に低いことである。準粒子のコレクタへの捕獲
を阻害する要因はベース超伝導体中での準粒子の散乱、
再結合と超伝導体−半導体界面での反射、散乱の2つに
まず大別することができる。この中で前者のベース中で
の再結合についてはその特性時間(緩和時間)が10〜
1.00psecと準粒子のベース走行時間(−0,1
psec)に比べ無視できる。また、準粒子の散乱につ
いては、電子−フォノン散乱、電子−電子衝突、格子欠
陥、不純物等による散乱などの要因が存在するが極低温
で準粒子の注入エネルギーが低い場合においては前2者
はほとんど無視することができる。
On the other hand, a problem with this type of device is that the collector capture rate (current transfer rate α) of quasiparticles is generally lower than that of bipolar transistors. The factors that inhibit the capture of quasiparticles into the collector are scattering of quasiparticles in the base superconductor,
It can be roughly divided into two types: recombination, and reflection and scattering at the superconductor-semiconductor interface. Among these, for the former recombination in the base, its characteristic time (relaxation time) is 10~
1.00 psec and the base travel time of the quasiparticle (-0,1
(psec) can be ignored. Regarding the scattering of quasiparticles, there are factors such as electron-phonon scattering, electron-electron collisions, lattice defects, scattering due to impurities, etc., but when the quasiparticle injection energy is low at an extremely low temperature, the former two are can be almost ignored.

一方、従来ベース超伝導層としては、半導体単結晶上に
スパッタリングや電子ビーム蒸着等で形成した多結晶薄
膜が用いられているが、堆積初期において100Å以下
と結晶粒径が非常に小さく、かつ相互拡散等により半導
体構成原子を不純物として取り込んだ層が100〜50
0人の厚みで形成されており、このような初期堆積層に
おいては準粒子の粒界や不純物による散乱が著しく、準
粒子のコレクタ界面への到達確率が低下してしまうとい
う問題点が存在した。
On the other hand, polycrystalline thin films formed on semiconductor single crystals by sputtering or electron beam evaporation are conventionally used as base superconducting layers, but in the initial stage of deposition, the crystal grain size is very small, less than 100 Å, and The number of layers containing semiconductor constituent atoms as impurities due to diffusion etc. is 100 to 50.
In such an initial deposited layer, scattering of quasiparticles due to grain boundaries and impurities is significant, reducing the probability of quasiparticles reaching the collector interface. .

次に、超伝導体−半導体界面においては、通常ポテンシ
ャルバリア(ショットキーバリア)が形成されているた
め、準粒子の量子力学的反射が生じるが、バリア高さが
低くなるような半導体(例えば、InSb、InAs等
の狭ギヤツプ半導体)を用いることで透過率の増大が図
られている。一方、従来のようにスパッタリングや電子
ビーム蒸着等でこれら半導体単結晶上に超伝導体薄膜を
堆積した場合、高エネルギー粒子の照射や熱輻射等によ
り半導体表面に結晶性の乱れた層や相互拡散層が形成さ
れる。これは半導体−超伝導体界面の平坦性の低下を意
味し、このポテンシャルの乱れにより準粒子の界面領域
での散乱が増大し、実効的な透過率が量子力学的理論値
より低下してしまうという問題が存在する。
Next, since a potential barrier (Schottky barrier) is normally formed at the superconductor-semiconductor interface, quantum mechanical reflection of quasiparticles occurs. The transmittance is increased by using narrow gap semiconductors such as InSb and InAs. On the other hand, when a superconductor thin film is conventionally deposited on these semiconductor single crystals by sputtering, electron beam evaporation, etc., a layer with disordered crystallinity or interdiffusion may appear on the semiconductor surface due to irradiation with high-energy particles or thermal radiation. A layer is formed. This means that the flatness of the semiconductor-superconductor interface decreases, and this potential disturbance increases scattering of quasiparticles at the interface region, reducing the effective transmittance below the quantum mechanical theoretical value. There is a problem.

これらの原因による電流伝達率αの低下のために従来の
デバイスでは半導体バイポーラトランジスタに比べ低い
電流利得(β=α/1−α)しか得られないという欠点
が存在した。
Due to the reduction in the current transfer rate α due to these causes, the conventional device has the disadvantage that only a lower current gain (β=α/1−α) can be obtained than that of a semiconductor bipolar transistor.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記した従来デバイスの欠点を解決し
た、半導体バイポーラトランジスタに匹敵する十分大き
な信号増幅率を有し、高速かつ低消費電力で動作する超
伝導デバイスを提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a superconducting device that solves the above-described drawbacks of conventional devices, has a sufficiently large signal amplification factor comparable to that of semiconductor bipolar transistors, and operates at high speed and with low power consumption.

〔発明の構成〕[Structure of the invention]

本発明は、超伝導体からなるベース層と、該ベース層の
一方の側に接し、該ベース層に準粒子を注入する常伝導
金属、超伝導体又は半導体からなるエミッタ層と、該ベ
ース層の他方の側に接し、該ベース層から準粒子を捕獲
する半導体からなるコレクタ層とを備えた超伝導三端子
デバイスにおいて、前記ベース層がダイヤモンド構造S
n。
The present invention includes a base layer made of a superconductor, an emitter layer made of a normal metal, a superconductor, or a semiconductor that is in contact with one side of the base layer and into which quasiparticles are injected into the base layer, and the base layer. a collector layer made of a semiconductor that is in contact with the other side of the base layer and captures quasiparticles from the base layer, wherein the base layer has a diamond structure S
n.

GaSb、InSb、InAs、CdS、CdSe。GaSb, InSb, InAs, CdS, CdSe.

P b T e HI nl −x G BXA s混
晶又はI n S b□−、As、混晶からなるコレク
タ層上にエピタキシャル成長させたNbあるいはNbN
層であることを最も主要な特徴とする。
P b T e HI nl -x GB
The most important feature is that it is a layer.

Nbは体心立方の結晶構造をもち、かつ第4図(表中、
aoは格子定数を示す)に図表で示すようにダイヤモン
ド構造Sn、GaSb、InSb。
Nb has a body-centered cubic crystal structure, and in Figure 4 (in the table,
diamond structure Sn, GaSb, InSb as shown in the diagram (ao indicates lattice constant).

InAs、CdS、CdSe、PbTeといった同じ立
方晶系の狭ギャップ(E g< 1 eV )半導体の
格子定数の1/2に近い格子定数をもつ。これらの半導
体単結晶上への第5図(A 、)に示すようなNb結晶
の成長を考えた場合、格子定数のミスマツチは最大で1
1%以下であり、半導体単結晶上へのへテロエピタキシ
ャル成長が可能である。また、例えばMOCVD法(有
機金属気相成長法)のように基板への高エネルギー粒子
照射や熱輻射による擾乱の非常に少さな方法でベース用
のNbを堆積すれば、結晶欠陥の少ない単結晶を堆積初
期から成長させることができると共に基板半導体単結晶
あるいは単結晶Nb上にさらにエピタキシャル成長させ
た上記半導体単結晶をコレクタ層とすることにより、ベ
ース−コレクタ界面の構造の乱れが非常に少ないデバイ
ス構成を得ることができる。
It has a lattice constant that is close to 1/2 of the lattice constant of the same cubic system narrow gap (E g < 1 eV) semiconductors such as InAs, CdS, CdSe, and PbTe. When considering the growth of Nb crystals as shown in Figure 5 (A,) on these semiconductor single crystals, the lattice constant mismatch is at most 1.
It is 1% or less, and heteroepitaxial growth on a semiconductor single crystal is possible. Furthermore, if Nb for the base is deposited using a method such as MOCVD (metal-organic chemical vapor deposition) that causes very little disturbance due to high-energy particle irradiation or thermal radiation on the substrate, it is possible to deposit Nb for the base using a method such as MOCVD (metal-organic chemical vapor deposition). A device in which the crystal can be grown from the initial stage of deposition, and the structure of the base-collector interface has very little disturbance by using the semiconductor single crystal as the collector layer, which is further epitaxially grown on the substrate semiconductor single crystal or single crystal Nb. You can get the configuration.

一方、NbNはBl(NaCu型)構造で立方晶系であ
ると共にその格子定数の「7倍が上記半導体の格子定数
に近く、第5図(B)に示すような半導体結晶に対して
45°の方位へのへテロエピタキシャル成長が可能であ
り、Nbの場合と同様のデバイス構成が得られる。
On the other hand, NbN has a Bl (NaCu type) structure and is a cubic system, and its lattice constant is 7 times close to the lattice constant of the semiconductor described above, and is 45° It is possible to perform heteroepitaxial growth in the direction of Nb, and a device configuration similar to that in the case of Nb can be obtained.

以上述べたように、本発明は従来のデバイスとはベース
超伝導体の作製方法及び構造、結晶性が異なる。
As described above, the present invention differs from conventional devices in the manufacturing method, structure, and crystallinity of the base superconductor.

〔発明の実施例〕[Embodiments of the invention]

実施例 1 第1図は本発明の第1の実施例を説明する概略断面図で
ある。
Embodiment 1 FIG. 1 is a schematic sectional view illustrating a first embodiment of the present invention.

P型GaSb、ノンドープ(n型)InSb、p型In
As、n型CdS、n型Cd S e、あるいはn型P
bTeからなる単結晶基板1の(100)面上にrf励
起CVD法により、それぞれNb層を500人の厚さに
形成した。このとき、グラファイトからなるサセプタを
用い、サセプタ温度を400〜650℃とし、反応ガス
にはNbcasを、キャリアガスとしてはH2を用いた
。全ガス流量は2Q/ll1in、反応ガス圧は0.1
気圧とした。この時、 2NbCL+5H2→ 2Nb+10HCaなる式で表
わされる熱分解反応により基板1上にはNb層が堆積さ
れる。
P-type GaSb, non-doped (n-type) InSb, p-type In
As, n-type CdS, n-type Cd S e, or n-type P
Each Nb layer was formed to a thickness of 500 nm on the (100) plane of a single crystal substrate 1 made of bTe by an RF-excited CVD method. At this time, a susceptor made of graphite was used, the susceptor temperature was set at 400 to 650°C, Nbcas was used as the reaction gas, and H2 was used as the carrier gas. Total gas flow rate is 2Q/ll1in, reaction gas pressure is 0.1
It was taken as atmospheric pressure. At this time, an Nb layer is deposited on the substrate 1 by a thermal decomposition reaction expressed by the formula: 2NbCL+5H2→2Nb+10HCa.

上記各基板1上に堆積されNb薄膜は良好なラウェパタ
ーンを示し、単結晶薄膜であることが確認できた。また
、超伝導転移温度Tcは9.4にで、室温とIOKでの
抵抗率の比(残留抵抗比ρ(300K)/ρ(10K)
)は100〜200であった。一方、同じ半導体単結晶
基板上にdcマグネトロンスパッタ法により室温で堆積
したNb薄膜は多結晶であり、Tcは9.0〜9.2K
、残留抵抗比は4〜6であった。
The Nb thin film deposited on each of the substrates 1 showed a good Laue pattern, and was confirmed to be a single crystal thin film. In addition, the superconducting transition temperature Tc is 9.4, and the ratio of resistivity at room temperature and IOK (residual resistance ratio ρ (300K) / ρ (10K)
) was 100-200. On the other hand, the Nb thin film deposited at room temperature by DC magnetron sputtering on the same semiconductor single crystal substrate is polycrystalline and has a Tc of 9.0 to 9.2K.
, the residual resistance ratio was 4-6.

次に、上記各基板1上のNb層から反応性イオンエッチ
ッグ(R,IE)によりNb層からなるベースパタン2
を形成した。エツチングには(CF4+5%02 )混
合ガスを用い、全ガス圧8Pa、rf放電のパワー20
Wの条件でエツチングを行なった。さらに、上記基板全
面上にSiOからなる絶縁層3を真空蒸着で堆積した後
、ベース層2上の絶縁層3に窓を開け、バリア層4を介
してNbからなるエミッタ電極5を、またNbからなる
ベース電極6をそれぞれリフトオフ法で形成した。
Next, a base pattern 2 made of the Nb layer is formed from the Nb layer on each substrate 1 by reactive ion etching (R, IE).
was formed. For etching, a (CF4+5%02) mixed gas was used, the total gas pressure was 8 Pa, and the RF discharge power was 20
Etching was performed under W conditions. Furthermore, after depositing an insulating layer 3 made of SiO on the entire surface of the substrate by vacuum evaporation, a window is opened in the insulating layer 3 on the base layer 2, and an emitter electrode 5 made of Nb is attached via a barrier layer 4. Each base electrode 6 was formed by a lift-off method.

バリア層はNb表面を(Ar+10%CF4)混合ガス
プラズマ中でクリーニングした後、(Ar+8%o2)
混合ガス中でのrf放電でプラズマ酸化して形成した。
After cleaning the Nb surface in (Ar+10% CF4) mixed gas plasma, the barrier layer was prepared using (Ar+8% O2).
It was formed by plasma oxidation using RF discharge in a mixed gas.

最後に、半導体基板1上の絶縁層3に形成した基板1に
通じる窓にAuからなるコレクタ電極7を形成した。
Finally, a collector electrode 7 made of Au was formed in a window formed in the insulating layer 3 on the semiconductor substrate 1 and communicating with the substrate 1.

このようにして作製した三端子素子のベース接地での電
流伝達率αを4.2にで測定した。ベース−コレクタ間
電圧が零の時のαを第6図に図表で示した。同図かられ
かるように、エミッターベース電圧30Q+nV (p
−GaSbの場合は10mV)の準粒子注入に対して、
多結晶Nbベースからなる素子の場合、0.05〜0.
25のαが得られるのに対して、ベースがエピタキシャ
ル成長Nb単結晶からなる素子では、αが0.25から
最大で0.7と大幅な伝達率の改善が見られた。ここで
、p−GaSbの場合、注入電圧が低くても大きなαが
得られたのは、ベース−コレクタ界面での界面準位密度
の低下によリオーミックに近い低いポテンシャルバリア
が形成されたためである。
The current transfer rate α of the three-terminal element thus produced with the base grounded was measured at 4.2. FIG. 6 graphically shows α when the base-collector voltage is zero. As can be seen from the figure, the emitter base voltage 30Q+nV (p
-10 mV for GaSb) for quasiparticle injection,
In the case of a device made of polycrystalline Nb base, the range is 0.05 to 0.0.
25 was obtained, whereas in the element whose base was made of epitaxially grown Nb single crystal, α was found to be significantly improved from 0.25 to a maximum of 0.7. Here, in the case of p-GaSb, the reason why a large α was obtained even when the injection voltage was low is because a low potential barrier close to rhiomic is formed due to the decrease in interface state density at the base-collector interface. .

実施例 2 実施例1と同様に、p型GaSb、ノンドープInSb
、 p型InAs、n型CdS、n型CdSe。
Example 2 Similar to Example 1, p-type GaSb, non-doped InSb
, p-type InAs, n-type CdS, n-type CdSe.

あるいはn型P b T e単結晶基板の(100)面
上にrf励起CVD法により、今度はNbN層を500
人の厚さに形成した。反応ガスとしてはNbCa、とN
H,を、キャリアガスとしてはH2を用い、サセプタ温
度は600℃とし、全ガス流量は3Q/min、反応ガ
ス圧は0.15気圧とした。この場合、NbCら+NH
3+H2−→NbN+5H(Jlの反応で、NbN層が
形成される。
Alternatively, a 500% NbN layer is deposited on the (100) plane of an n-type PbTe single crystal substrate using the RF-excited CVD method.
Formed to the thickness of a person. NbCa and N are used as reaction gases.
H2 was used as the carrier gas, the susceptor temperature was 600° C., the total gas flow rate was 3 Q/min, and the reaction gas pressure was 0.15 atm. In this case, NbC et al + NH
3+H2-→NbN+5H (A NbN layer is formed by the reaction of Jl.

上記各基板上に形成したNbN薄膜は良好なラウェパタ
ンを示し、単結晶薄膜であることが確認できた。また、
Tcは16.5〜17.2にであった。
The NbN thin film formed on each of the above substrates showed a good rawe pattern, and was confirmed to be a single crystal thin film. Also,
Tc was 16.5-17.2.

次に、実施例1と同じプロセスで第1図と同じ構造の素
子を作製した。また、上記各基板上に(A r + N
 2 )混合ガスを用いた反応性dcマグネ1〜ロンス
パッタにより形成した多結晶NbN (Tc=14〜1
5.5K)をベース層とする素子も作製した。
Next, an element having the same structure as that shown in FIG. 1 was manufactured using the same process as in Example 1. Moreover, on each of the above substrates (A r + N
2) Polycrystalline NbN (Tc = 14 to 1
A device having a base layer of 5.5K) was also fabricated.

これらの素子のベース−コレクタ電圧零の状態での電流
伝達率を4.2にで測定した。その結果、多結晶ベース
を用いた素子で0.01〜0.20のαが得られたのに
対し、エピタキシャル成長単結晶NbNをベースとした
素子のαは0.2〜0.75と大幅に改善された。
The current transfer rate of these elements in a state where the base-collector voltage is zero was measured at 4.2. As a result, while an α of 0.01 to 0.20 was obtained for a device using a polycrystalline base, an α of 0.2 to 0.75 was obtained for a device based on epitaxially grown single crystal NbN. Improved.

実施例 3 第2図は本発明の第三の実施例を示す概略断面図である
Embodiment 3 FIG. 2 is a schematic sectional view showing a third embodiment of the present invention.

半絶縁性のInP単結晶基板8の(100)面上に有機
金属気相成長法(MOCVD)により、Seをドープし
たn+型Ga、、1. I no、Ils As層9 
(厚さ5000人)とn型Gal+、1. I no、
65 Asからなるコレクタ層10(厚さ1000人)
を連続してエピタキシャル成長させた。この場合、有機
金属としては、トリメチルガリウム(TMG、(CHa
)aGa)とトリメチルインジウム(TM In、(C
H3)3 In)を、キャリアガスとしてH2を用い、
また、■族元素供給はアルシンA s H3をH2で1
0%に希釈した混合ガスを、ドープ用のSeはH2Se
の希釈ガスを用いた。結晶成長時の基板温度は650℃
、全キャリアガス流量は4Q/minとした。
n+ type Ga doped with Se by metal organic chemical vapor deposition (MOCVD) on the (100) plane of a semi-insulating InP single crystal substrate 8, 1. I no, Ils As layer 9
(thickness 5000 people) and n-type Gal+, 1. I no,
Collector layer 10 (1000 layers thick) consisting of 65 As
was continuously grown epitaxially. In this case, as the organic metal, trimethyl gallium (TMG, (CHa
) aGa) and trimethylindium (TM In, (C
H3) 3 In) using H2 as a carrier gas,
In addition, the supply of group Ⅰ elements is as follows: arsine A s H3 with H2
Mixed gas diluted to 0%, Se for doping is H2Se
dilution gas was used. Substrate temperature during crystal growth is 650℃
, the total carrier gas flow rate was 4Q/min.

次に、この半導体薄膜上に連続して、実施例1゜2と同
様なCVD法でNbあるいはNbNからなるベース層1
1を500人の厚みで成長させた。この場合の下地層1
0と超伝導体層11との格子定数のミスマツチはNbで
10%、NbNで4%であり、やはり単結晶層が得られ
る。
Next, a base layer 1 made of Nb or NbN is continuously formed on this semiconductor thin film by the same CVD method as in Example 1-2.
1 has grown to a depth of 500 people. Base layer 1 in this case
The mismatch in lattice constant between Nb and superconductor layer 11 is 10% for Nb and 4% for NbN, and a single crystal layer is also obtained.

次に、単結晶Nb、NbN層11の上に連続してMOC
VD法によりn+型G a A s層12を5000人
の厚さまでエピタキシャル成長させた。この場合の基板
温度はやはり650℃、キャリアガス流量は2Q/mi
nとした。このようにして形成した多層膜を外に取り出
し、化学エツチングとRIEでエミッタ接合部(この場
合は、Nb (またはNbN) −’n”型G a A
 sショットキ接合)とベースパタンの加工を行なった
後、SiOからなる絶縁層13を実施例1と同様に堆積
し、さらに、絶縁層13に設けた窓にNbからなるベー
ス電極14とAuからなるエミッタ電極15をリフトオ
フ法で形成した。最後に、さらに絶縁層13に設けたn
+型Ga、、15Inn、BgAs層9に達する別の窓
内にAuからなるオーミックコレクタ電極16を形成し
た。
Next, MOC is continuously formed on the single crystal Nb and NbN layers 11.
The n+ type GaAs layer 12 was epitaxially grown to a thickness of 5000 nm by the VD method. In this case, the substrate temperature is still 650°C, and the carrier gas flow rate is 2Q/mi.
It was set as n. The multilayer film thus formed was taken out and subjected to chemical etching and RIE to form the emitter junction (in this case, Nb (or NbN)-'n'' type Ga A
s Schottky junction) and base pattern processing, an insulating layer 13 made of SiO is deposited in the same manner as in Example 1, and a base electrode 14 made of Nb and a base electrode 14 made of Au are deposited in the window provided in the insulating layer 13. Emitter electrode 15 was formed by a lift-off method. Finally, the n
An ohmic collector electrode 16 made of Au was formed in another window reaching the +-type Ga, 15Inn, and BgAs layers 9.

以上のようにして作製した素子の4.2にでの電流伝達
率αは、エミッターベース間バイアスが20111vの
時に0.65〜0.85の値が得られ、ベース層にスパ
ッタで形成したNbまたはNbN多結晶を用いた時の0
.07〜0.25より大幅な改善が見られた。
The current transfer coefficient α at 4.2 of the device fabricated as described above has a value of 0.65 to 0.85 when the emitter-base bias is 20111V, and the Nb formed by sputtering on the base layer Or 0 when using NbN polycrystal
.. A significant improvement was seen from 0.07 to 0.25.

実施例 4 ノンドープInSb単結晶を基板として実施例3と同様
にMOCVD法により、今度は I n S bl−、As、とダイヤモンド構造Snを
エピタキシャル成長させた。前者の場合はT M I 
nとSbH,、AsH3を原料ガスとして用い、まず厚
さ5000人のn+型I n S b。、、、 As。
Example 4 Using a non-doped InSb single crystal as a substrate, similarly to Example 3, MOCVD was used to epitaxially grow InS bl-, As, and diamond structure Sn. In the former case, TMI
First, using n, SbH, and AsH3 as source gases, an n+ type I n S b with a thickness of 5,000 people was prepared. ,,, As.

、、層をバッファ層として形成した後、厚さ1000人
のn型I n S bo、3Aso、vからなるコレク
タ層を形成した。
,, layer as a buffer layer, a collector layer consisting of a 1000 nm thick n-type I n S bo,3Aso,v was formed.

Snの場合は(CH3)4Snを原料ガスに、ドープ用
としてH2で希釈したSbH3を用い、n+層をやはり
5000人とコレクタ層のn型Sn層を厚さ1000人
成長させた。この上に連続して実施例1,2と同様にC
VD法でNb及びNbN層をエピタキシャル成長させて
単結晶のベース層(厚さ500人)を形成した。次に、
実施例1〜3と同様のプロセスで素子を作製した。この
場合のエミッタ接合は下地のNb(またはNbN)のプ
ラズマ酸化膜からなるバリア層を介して常伝導のAuか
らなる電極を堆積し、形成した。
In the case of Sn, (CH3)4Sn was used as the source gas and SbH3 diluted with H2 was used for doping, and the n+ layer was grown to a thickness of 5000 layers and the n-type Sn layer as the collector layer was grown to a thickness of 1000 layers. Continuously on top of this, as in Examples 1 and 2, C
Nb and NbN layers were epitaxially grown using the VD method to form a single crystal base layer (thickness: 500 nm). next,
Elements were produced using the same process as Examples 1 to 3. The emitter junction in this case was formed by depositing an electrode made of normal conducting Au through a barrier layer made of an underlying Nb (or NbN) plasma oxide film.

これらの素子の4.2にの電流伝達率は0.4〜0.7
5(I n S b、−yAsyコレクタの場合のエミ
ッターベース間は10mV、Snコレクタの場合150
mV)と、多結晶Nb (またはNbN)ベースの素子
での値0.01〜0.35を越える値が得られた。
The current transfer coefficient of these elements is 0.4-0.7
5 (I n S b, -y 10 mV between emitter-base for Asy collector, 150 mV for Sn collector
mV), which exceeded the values for polycrystalline Nb (or NbN)-based devices from 0.01 to 0.35.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、ダイヤモンド構
造のSn、GaSb、I’nSb、InAs。
As explained above, according to the present invention, diamond-structured Sn, GaSb, I'nSb, and InAs.

CdS、CdSe、PbTe、In1−xGaxAs混
晶及びI n S bl−y混晶のいずれかを基板(下
地)に選ぶことにより、同じ立方晶で、格子定数のミス
マツチの小さなNbあるいはNbNのエピタキシャル成
長単結晶薄膜を得ることができ、この単結晶Nbあるい
はNbNを素子のベース層、下地半導体単結晶をコレク
タ層とすることにより、ベース結晶及び界面構造の乱れ
による準粒子の散乱要因が低減化され、半導体バイポー
ラトランジスタに匹敵する大きな電流伝達率、すなわち
大きな電流利得が得られるという利点がある。また、同
様に、ベース−コレクタ界面での界面準位密度の低下の
ために、半導体材料及び極性の選択により低いポテンシ
ャルバリアを形成することができ、動作電圧の低減化、
すなわち素子の低消費電力化が達成できるという利点が
ある。
By selecting one of CdS, CdSe, PbTe, In1-xGaxAs mixed crystal, and InS bl-y mixed crystal as the substrate (base), it is possible to epitaxially grow Nb or NbN monomers with the same cubic crystal but with small lattice constant mismatch. A crystal thin film can be obtained, and by using this single crystal Nb or NbN as the base layer of the device and the underlying semiconductor single crystal as the collector layer, the scattering factors of quasiparticles due to disorder of the base crystal and interface structure are reduced. It has the advantage of providing a large current transfer rate comparable to that of semiconductor bipolar transistors, that is, a large current gain. Similarly, due to the reduction in interface state density at the base-collector interface, a low potential barrier can be formed by selecting the semiconductor material and polarity, reducing the operating voltage.
That is, there is an advantage that lower power consumption of the element can be achieved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図は本発明の実施例を示す概略断面図、第
3図は本発明に係わる従来の超伝導三端子デバイスの模
式図、第4図はNb、Nb−N及び半導体の格子定数a
。を示す図表、第5図はNb又はNbN単結晶と第4図
に示した半導体単結晶との格子整合状態を説明するため
の図、第6図は本発明による超伝導二端子デバイスと従
来の超伝導三端子デバイスの電流伝達率αを示す図表で
ある。 図において、1は半導体単結晶基板、2はベース層(エ
ピタキシャル成長Nb又はNbN単結晶層)、3は絶縁
J(SiO)、4はバリア層、5はエミッタ電極(Nb
)、6はベース電極(Nb)、7はコレクタ電極(Au
)、8は半導体単結晶基板(InP)、9はn” −G
ao、□6 I n。、 B HA s層、10はコレ
クタ層(n  Gao、1sI n。、Il、As層)
、11はベース層(エピタキシャル成長Nb又はNbN
層)、12はn+−G a A s層、13は絶縁層(
SiO)、14はベース電極(Nb)、15はエミッタ
電極(Au)、16はオーミックコレクタ電極(A u
 )である。 JI!P2図 831−A艷イ参月1(ギ1晶、1(−才l乏(r??
P)才3図 才4 ダ 矛5図 (A) ■ 0 ■ o  OoNbA) (B) Δ   Δ   Δ   Δ ■   ・   ΔN 浮子 (Vac =O)
1 and 2 are schematic cross-sectional views showing examples of the present invention, FIG. 3 is a schematic diagram of a conventional superconducting three-terminal device according to the present invention, and FIG. 4 is a schematic diagram of a conventional superconducting three-terminal device according to the present invention. lattice constant a
. 5 is a diagram for explaining the lattice matching state between the Nb or NbN single crystal and the semiconductor single crystal shown in FIG. 4, and FIG. 6 is a diagram showing the superconducting two-terminal device according to the present invention and the conventional one. It is a chart showing the current transfer rate α of a superconducting three-terminal device. In the figure, 1 is a semiconductor single crystal substrate, 2 is a base layer (epitaxially grown Nb or NbN single crystal layer), 3 is an insulator (SiO), 4 is a barrier layer, and 5 is an emitter electrode (NbN
), 6 is a base electrode (Nb), 7 is a collector electrode (Au
), 8 is a semiconductor single crystal substrate (InP), 9 is n''-G
ao, □6 I n. , B HA s layer, 10 is the collector layer (n Gao, 1sI n., Il, As layer)
, 11 is a base layer (epitaxially grown Nb or NbN
layer), 12 is an n+-Ga As layer, and 13 is an insulating layer (
14 is a base electrode (Nb), 15 is an emitter electrode (Au), 16 is an ohmic collector electrode (Au
). JI! P2 Figure 831-A 艷い三月 1 (Gi 1 Crystal, 1 (-talience (r??
P) Sai3 figure Sai4 Dako5 figure (A) ■ 0 ■ o OoNbA) (B) Δ Δ Δ Δ ■ ・ ΔN Float (Vac = O)

Claims (1)

【特許請求の範囲】[Claims] 1、超伝導体からなるベース層と、該ベース層の一方の
側に接し、該ベース層に準粒子を注入する常伝導金属、
超伝導体又は半導体からなるエミッタ層と、該ベース層
の他方の側に接し、該ベース層から準粒子を捕獲する半
導体からなるコレクタ層とで構成されている超伝導三端
子デバイスにおいて、前記ベース層がダイヤモンド構造
Sn、GaSb、InSb、InAs、CdS、CdS
e、PbTe、In_1_−_xGa_xAs混晶又は
InSb_1_−_yAs_y混晶からなる前記コレク
タ層上にエピタキシャル成長させたNbあるいはNbN
層からなることを特徴とする超伝導三端子デバイス。
1. A base layer made of a superconductor, and a normal conducting metal in contact with one side of the base layer and injecting quasiparticles into the base layer;
In a superconducting three-terminal device comprising an emitter layer made of a superconductor or a semiconductor, and a collector layer made of a semiconductor that is in contact with the other side of the base layer and captures quasiparticles from the base layer, the base layer Layer has diamond structure Sn, GaSb, InSb, InAs, CdS, CdS
e, Nb or NbN epitaxially grown on the collector layer consisting of PbTe, In_1_-_xGa_xAs mixed crystal or InSb_1_-_yAs_y mixed crystal.
A superconducting three-terminal device characterized by consisting of layers.
JP61035239A 1986-02-21 1986-02-21 Superconducting three-terminal device Pending JPS62195189A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61035239A JPS62195189A (en) 1986-02-21 1986-02-21 Superconducting three-terminal device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61035239A JPS62195189A (en) 1986-02-21 1986-02-21 Superconducting three-terminal device

Publications (1)

Publication Number Publication Date
JPS62195189A true JPS62195189A (en) 1987-08-27

Family

ID=12436291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61035239A Pending JPS62195189A (en) 1986-02-21 1986-02-21 Superconducting three-terminal device

Country Status (1)

Country Link
JP (1) JPS62195189A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5097741A (en) * 1989-02-03 1992-03-24 Roland Corporation Electronic musical instrument with tone volumes determined according to messages having controlled magnitudes
US5231295A (en) * 1990-08-21 1993-07-27 Thomson-Csf Superconducting field effect transistor
JP2008026404A (en) * 2006-07-18 2008-02-07 Yamaha Corp Electronic keyboard musical instrument

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5097741A (en) * 1989-02-03 1992-03-24 Roland Corporation Electronic musical instrument with tone volumes determined according to messages having controlled magnitudes
US5231295A (en) * 1990-08-21 1993-07-27 Thomson-Csf Superconducting field effect transistor
JP2008026404A (en) * 2006-07-18 2008-02-07 Yamaha Corp Electronic keyboard musical instrument

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