JPS62193441A - Level controller - Google Patents

Abstract

PURPOSE:To always find the optimum slice level to identify an input digital data (digital signal) as a code of '1' or '0' without fail, by obtaining a level correction value corresponding to the error rate of the input digital data. CONSTITUTION:An arithmetic circuit 14 finds an error rate A from A=(counter value (c))/(counter values a+c). The error rate A represents 'a rate of too low level'. Also, an arithmetic circuit 15 finds an error rate B from B=(counter value (d))/(counter values b+d). The error rate B represents 'a rate of too high'. An arithmetic circuit 16 finds a dislocation rate alpha from alpha=1-(B/A). A correction value beta (=Rx beta ) can be found with the dislocation rate alpha and a reference data R, and the correction value beta is added/subtracted on the reference value, then being supplied to a D/A converter 17. The D/A converter 17 converts the correction value beta to an analog offset voltage, then supplying it to an adder 3, and the offset voltage and the reference voltage Eref are added, then being supplied to an input terminal at the other side of a level comparator 2.

Description

Detailed Description of the Invention (Field of Industrial Application) This invention relates to a level control device, such as a character signal packet superimposed within the vertical blanking period of a video signal transmitted (sent) from a broadcasting station. level control m+ to find the discrimination point (slice level at VI) to reliably identify the digital signals that make up the n9 of rlJ and rOJ.
Regarding equipment.

(Prior technology) Recently, a new broadcasting service has been teletext broadcasting (hereinafter referred to as
teletext) has been put into practical use.

Furthermore, compared to the conventional pattern method, there is a hybrid method that combines the advantages of the pattern method with a code method having high transmission efficiency.

Unlike regular television programs that are organized by time, teletext repeatedly transmits various information and entertainment programs consisting of text, graphics, and additional sounds, allowing viewers to access the information they want when they want it. This is a new broadcasting system that has made it possible to

The above information such as text and images is multiplexed with the television radio waves (video signals) from the currently broadcasting station, and the receiver side has a text signal receiving device that can receive text broadcasting, and text If you prepare an adapter, you can select and watch a desired teletext program from among many teletext programs.

In addition, this teletext signal (text signal packet) is transmitted as a digital signal using the lli gap (i.e., vertical blanking period) of the current preview video signal, and is transmitted as a digital signal to the receiving device. On the side, the signal is decoded and received, and images are displayed on the television screen and additional sounds such as music are generated to create a text program. You can now listen to J2.

The character signal bucket l- (digital signal) that is generated during the vertical blanking period of the video signal as described above is separated by a gate pulse generated by the synchronous reproducing circuit of the character signal receiving device, and is converted into a clock signal (digital signal). bling clock)
The mark Q GE separation is performed at the timing of , rlJ, r
The OJ digital data signal is taken out.

Further, in the code identification of the digital signals that constitute such character signal buckets 1 to 1, etc., it is "1".

In order to reliably identify "0", it is necessary to set the discrimination level so that the margins in the amplitude direction are equal to the positive and negative margins.

For this reason, the slice level can be determined by clamping the pedestal potential of the video signal using a pedestal clamp circuit, distinguishing between a fixed level (constant potential) and the clamped signal using an inverter, or using a peak hold circuit to determine the peak of the digital signal. How to detect the potential and how to determine the slice level from the pedestal potential and peak potential [
That is, slice level ES=EC+ (Ep-Ec
)/2, where EC is the clamp potential.

Ep is the peak potential], etc., and the discrimination level is set.

(Problem to be Solved by the Invention) However, in reality, in the relationship diagram between frequency and relative amplitude shown in Figure 2, the ideal curve S appears due to ghost interference, orthogonal distortion, phase distortion, group delay, etc. In some cases, the typical amplitude characteristics and phase characteristics cannot be realized in an actual transmission path, and the optimum slice level cannot be determined using the method for determining the slice level as described above.

For example, in the case of curve a in Fig. 2, the slice level shifts above the optimal level due to overshoot (see an example of a character signal packet in Fig. 3 (a)) due to the high frequency range being increased. In addition, in the case of the curved line in Figure 2, the high frequency range is lowered (see an example of a character signal packet in Figure 3 (b)), so the slice level has shifted below the optimal level. Put it away.

In addition, as another method of determining the slice level, for example, the clock run-in (CR: C1
In the case of the method of trapping 2.8MH of the ock run-in section and finding the slice level, it is possible to remove the influence of frequency characteristics to some extent, but it is not possible to remove the influence of nonlinear distortion of the transmission path. Can not.

The above will now be explained using an eye pattern characteristic diagram as shown in FIG. 4 (that is, a characteristic diagram in which the pulse wave sequences of the transmitted digital signal are overlapped). In FIG. 4, the eye opening ratio for evaluating signal quality is the ratio of the amplitude difference A between "11" and "0" to the amplitude difference B inside the eye pattern expressed as a percentage. As for η rope, the eye width ratio = (B/A) x 100 (%).

In Fig. 4, the slice level is set at position a (
(Yo is in the center), the timing margin (limit)
and the amplitude margin are both maximum, but when the slice level is set to position b (upwards), the timing margin becomes small and the amplitude margin is shifted to one side, and the sampling phase is changed to position C at position g1 (approximately below). ), it becomes completely inappropriate.

Matt=, teletext is binary N RZ (Non Re
Because data is transmitted as a digital signal (turnto 7ero) signal, it is susceptible to waveform distortion and interference depending on the characteristics of the transmitter and receiver and the characteristics of the transmission path, which may affect the reception quality of teletext broadcasting. It will have an impact.

This means that the eye pattern characteristic diagram, for example, is
) ~ Figure 4 (C) shows that, unlike the one shown in Figure 4, the eye pattern is not necessarily in the center (that is, it is asymmetrical in the time book direction or the amplitude axis direction), and the eye pattern is different from the one shown in Figure 4. This is because the frontage ratio may become small, and therefore, the optimal slice level is not necessarily at the amplitude center position.

In this way, finding the optimal slice level is an important condition for obtaining data with few errors.

Therefore, the present invention solves the above-mentioned problems of the conventional technology and converts input digital data (digital signal) into Ml,
It is an object of the present invention to provide a level control device that can always reliably determine the optimum slice level for identifying the rOJ code and is less susceptible to the influence of a transmission path.

(Means for Solving the Problems) In order to achieve the above object, the present invention includes an error detection means for detecting an error every data interval of error-correctable input digital data; Calculates the error rate (or correct value rate) of the data using one stage of arguments that counts the detected error data and the count value of this adaptation means, and also calculates the level corresponding to the error rate (or correct rate) of the data. The present invention provides a level control device comprising a control means for controlling a correction value.

(Function) In the level control device configured as described above, a level correction value is obtained according to the error rate (or correct value rate) of human-powered digital data.

(Embodiment) An embodiment of the level control device according to the present invention will be described below with reference to the drawings.

For example, the present invention can generate a signal from a human input signal consisting of a character signal bucket 1- superimposed within a vertical blanking period of a video signal.
In order to find the optimal slice level, the binarized input signal is supplied to an error correction circuit, and it is checked whether there is an error in each data interval (1 bit) of this input digital data. [Number of correctly received it OIIs (a) J, r Number of correctly received 1″s (b) J,
r Number of “0” received incorrectly as “O” as “1” (
C)J.

r ``1'' and ``number of ``0'' and erroneously received 1''(d)'', and from these number data, 110
The error rate A (=c/ (a+c)) of II and the error rate B (-d/ (b+d)) of 1" are determined, and the slice level is automatically changed based on the relationship between A and 8. , to find the optimal slice level.

Next, the above will be explained with reference to a block diagram of an embodiment of the level control device of the present invention shown in FIG.

In FIG. 1, reference numeral 1 denotes an input terminal, to which input data is supplied, for example, digital signals such as character signal buckets 1 to 1 superimposed within a set blanking period of a video signal. This input data is then supplied to one input terminal r of the level comparator 2. Further, a reference voltage E ref is applied to the other input terminal of the level comparator 2 , and this standard voltage E ref is added to an offset voltage, which will be described later, in the adder 3 and then applied to the level comparator 2 . Ru.

The output of the level comparator 2 is supplied to a syndrome register 4 for error correction (detection), where bit errors in data (digital signals) are detected.

The error correction output of the syndrome register 4 is supplied to one input terminal of an exclusive OR circuit (EX-OR circuit) 5, while gate circuits 6, 7, 8, 9
and correction signals of the syndrome register 4 (i.e., 110 II is output when no correction is required, and 11111 is output when correction is required) 4, tEX-OR circuit 5 while the other input terminals of the gate circuits 6, 7.8 .
9, respectively.

In the EX-OR circuit 5, when the data supplied to one input terminal and the correction signal supplied to the other input terminal match (in other words, if the data supplied to one input terminal matches the correction signal supplied to the other input terminal), ”), output 0”, and if there is no match (i.e. “
0" and °゛1" or "°1" and °°0") to 1"
Output.

Further, the gate circuit 6 is an ANC circuit with an inverter connected to both input terminals, the gate circuit 7 is an AND circuit with an inverter connected to one input terminal, and the gate circuit 8 is an ANC circuit with an inverter connected to one input terminal. AND with inverter connected
The circuit 9 is an AND circuit in which nothing is connected to both input terminals.

Therefore, by inputting the error correction output and the correction signal, each gate circuit 6.7, 8.9 outputs "correctly received "0"data" and "correctly received data". 1” data”.

[Incorrectly received data of °゛0'' (i.e., data in which °゛0'' is incorrectly interpreted as 1'')], [Incorrectly received data of 1''
``data (that is, data that incorrectly identifies 711 II as II O11)'' is obtained.

Each output of the gate circuit 6.7.8.9 is then sent to the counter 10. Correct 1" data counter 11. Incorrect "OII data counter 12
．． The erroneous "1" data is supplied to the counter 13, and each data is counted.

Each counter value (a, C) of counters 10 and 12 is °''
0'' error rate e4 is supplied to the Korean circuit 14, and each counter value of the counters 11 and 13 (1,'', d> is "1'
.

The signal is supplied to the error rate reconstruction circuit 15. In addition, counter 1
Each counter value (a, b) of 0.11 indicates the "number of correctly received bits" and each counter value (c, d) of counter 12.13 indicates the "number of incorrect bits".

In addition, the arithmetic circuit 14 calculates the error rate of 0'' by calculating the following formula, and outputs the result of the calculation. In other words, A = (counter value C) / (counter value a + G > error) This error rate A indicates the "level undersize rate."

Further, the arithmetic circuit 15 calculates the following equation to obtain °“1”.
The error rate B is calculated and the result of the calculation n is output. That is, the error rate B is calculated from B=(counter value d)/(counter value b+d). Note that this error rate B indicates the "level too high rate".

Furthermore, the error rate A, which is calculated by the calculation circuits 14 and 15,
B is supplied to the control voltage offset value calculation circuit 1G.

The arithmetic circuit 16 performs the following calculation to determine the deviation rate α from the optimum level, and outputs the calculation result.

That is, α-1-<B/A) Find the deviation rate α.

Furthermore, a correction value β (=
R×α), and use this correction value β (e.g., 8-bit digital signal) as a reference till ((e.g., 8-bit digital signal).
127) and is supplied to the D/A converter 17.

Then, the D/ATI inverter 17 converts this correction value β into an analog offset voltage and supplies it to the adder 3, and further adds this offset voltage and the reference voltage ifE ref to the other side of the level comparison terminal 2. Correction is also supplied as a quaternary voltage to the input terminal of.

In the above manner, the error rate of II OII is reduced to “1''
The slice level is automatically changed according to the relationship with the error rate B, and the optimal slice level is controlled.

J5. In the above embodiment, the data error rate is determined and the slice level is controlled based on the error rate. However, on the contrary, the data positive value rate is determined and the slice level is controlled based on the positive value rate. It's okay.

(Effects of the Invention) As described above, according to the level it, l1ltl device of the present invention, the level correction value is obtained according to the error rate (or correct value rate) of the input digital data. The optimum slice level for discriminating (digital signal) into the codes "1" and "O" can always be reliably determined, and it is less susceptible to the influence of the transmission path.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the level control device according to the present invention, FIG. 2 is a diagram showing the relationship between the frequency and relative amplitude of a digital signal, and FIGS. 3(a) and 3(b) )
4 is a diagram showing an example of a character signal packet to explain the influence of a digital signal transmission path, and FIG. 4 is a diagram showing an example of an eye pattern characteristic diagram. It is a diagram showing an example of an eye pattern characteristic diagram for various disturbances. 1... Input terminal, 2... Level comparator, 3... Adder/Q device, 4... Syndrome register, 5... EX-
OR circuit, 6.7, 8.9... Gate circuit, 10, 11.12.13... Counter, 14, 15.
iG...Arithmetic circuit, 17...D/'8 converter. Patent Applicant: Japan Victor Co., Ltd. Representative: Odori
Part "-',,','::f':l:,',-1/1 b 2? f 9 a

Claims (1)

[Scope of Claims] Error detection means for detecting errors in error-correctable input digital data for each data period; counting means for counting error data detected by the error detection means; and a count value of the counting means. 1. A level control device comprising calculation means for calculating a data error rate (or positive value rate) according to the data error rate (or positive value rate), and calculating a level correction value according to the data error rate (or positive value rate).