JPS62190837A - Semiconductor manufacturing apparatus - Google Patents

Semiconductor manufacturing apparatus

Info

Publication number
JPS62190837A
JPS62190837A JP61034063A JP3406386A JPS62190837A JP S62190837 A JPS62190837 A JP S62190837A JP 61034063 A JP61034063 A JP 61034063A JP 3406386 A JP3406386 A JP 3406386A JP S62190837 A JPS62190837 A JP S62190837A
Authority
JP
Japan
Prior art keywords
resist
exposure
measuring
reflectivity
reflectance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61034063A
Other languages
Japanese (ja)
Inventor
Koichiro Tsujita
好一郎 辻田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61034063A priority Critical patent/JPS62190837A/en
Publication of JPS62190837A publication Critical patent/JPS62190837A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To always give constant energy to resist even if it is set in any condition and improve size controllability of resist pattern by measuring reflectivity of reflection measuring mark having the same structure as the practical device and achieving exposure by changing amount of exposure to device depending on such measuring value. CONSTITUTION:The reflectivity measuring mark in the same structure as the practical device to be exposed is formed by alignment using the alignment mark and this reflectivity measuring mark 7 is moved to the region where the reflectivity measuring beam of reflectivity measuring means is applied. The beam is radiated, incident light intensity and reflected light intensity are measured respectively with measuring instruments 3, 4, reflectivity is calculated, this reflectivity is compared with that when amount of exposure is determined and such ratio is calculated into the existing amount of exposure. Amount of exposure is changed for every exposure processing so that energy stored in the resist 10 becomes constant. Thereby, size of resist pattern can always be kept constant and the wafer can be exposed with the wanted amount of exposure.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体製造装置に関し、特にマスクパター
ンを転写するため縮小投影型の露光をする半導体製造装
置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor manufacturing apparatus, and more particularly to a semiconductor manufacturing apparatus that performs reduction projection type exposure to transfer a mask pattern.

〔従来の技術〕[Conventional technology]

ウェハプロセスでは、種々の材質上にレジストを塗布し
、露光機を用いてマスク寸法通りにレジストパターンを
形成することが重要である。レジストパターン形成を制
御するパラメータの一大要因には、レジスト膜厚がある
。これは、特に単一波長の光を用いる縮小投影型露光機
に顕著であるので、以下、この場合について説明を行う
In the wafer process, it is important to apply resist on various materials and form a resist pattern according to the mask dimensions using an exposure machine. One of the major parameters controlling resist pattern formation is resist film thickness. This is particularly noticeable in reduction projection type exposure machines that use light of a single wavelength, so this case will be explained below.

第5図は露光時のレジスト内での波形を説明する図であ
り、図において、21は入射波、22は反射波、23は
合成波(定在波)、24は空気層、25はレジスト、2
6は下地である。ある下地26の上にレジスト25が塗
布されると、該レジスト25内では、第5図に示すよう
に入射波21と下地26からの反射波22が干渉して合
成波としての定在波23が生じる。第5図では、下地2
6の屈折率がレジスト25の屈折率より大きく、かつ下
地26が電気伝導度(σ)をもたない場合、すなわち反
射で位相が反転する場合の合成波23が示されている。
FIG. 5 is a diagram explaining waveforms within the resist during exposure. In the figure, 21 is an incident wave, 22 is a reflected wave, 23 is a composite wave (standing wave), 24 is an air layer, and 25 is a resist waveform. ,2
6 is the base. When a resist 25 is applied on a certain base 26, within the resist 25, an incident wave 21 and a reflected wave 22 from the base 26 interfere with each other, as shown in FIG. 5, and a standing wave 23 is formed as a composite wave. occurs. In Figure 5, the base 2
The composite wave 23 is shown when the refractive index of the resist 25 is larger than the refractive index of the resist 25 and the base 26 has no electrical conductivity (σ), that is, when the phase is reversed by reflection.

そして、ここではある時間における入射波21と反射波
22の合成波23を計算し示したものであるが、該合成
波23の「節」つまり電場ベクトルの振巾の一部小さい
所と「腹」つまり電場ベクトルの振巾の一番大きい所の
位置は時間的に一定である。このことから、レジスト表
面で合成波が「節」、「腹」又はその中間的′性態のい
ずれになるかはレジスト膜厚で決定される。
Here, the composite wave 23 of the incident wave 21 and the reflected wave 22 at a certain time is calculated and shown. ''In other words, the position of the point where the electric field vector has the largest amplitude is constant over time. From this, the resist film thickness determines whether the composite wave forms a "node", "antinode", or an intermediate property on the resist surface.

次に、レジスト内で定在波が発生した時のレジストに与
えられる光エネルギの割合を第6図において説明する。
Next, the proportion of optical energy applied to the resist when standing waves are generated within the resist will be explained with reference to FIG.

図において、27は入射波の電界ベクトル、28は透過
波の電界ベクトル、29は反射波の電界ベクトル、30
は下地26からの反射波の電界ベクトル、31は入射波
と反射波の合成波の電界ベクトル、32は透過波と下地
26からの反射波の合成波の電界ベクトルである。
In the figure, 27 is the electric field vector of the incident wave, 28 is the electric field vector of the transmitted wave, 29 is the electric field vector of the reflected wave, and 30 is the electric field vector of the reflected wave.
is the electric field vector of the reflected wave from the substrate 26, 31 is the electric field vector of the composite wave of the incident wave and the reflected wave, and 32 is the electric field vector of the composite wave of the transmitted wave and the reflected wave from the substrate 26.

空気とレジストは電気伝導度σ=Oであるから、電磁気
の境界条件が成立し、 IEレジスト=lE空気 となる。ここでIEは電界バク1−ル、IEレジストは
空気とレジストの境界面でのレジスト側電界ベクトル3
2、IE空気は空気とレジストの境界面での空気側電界
ベクトル31である。
Since the electrical conductivity of air and resist is σ=O, the electromagnetic boundary condition is established, and IE resist=lE air. Here, IE is the electric field vector 1, and IE resist is the electric field vector 3 on the resist side at the interface between air and resist.
2. IE air is the air side electric field vector 31 at the interface between air and resist.

また、平面波である電磁波の電場IEはlE=  l 
 E  1sin  ((1)t −λ χ+6)と表
現できる。ここで、 IEIは電界の振巾 ω は角周波数 λ は波長 δ は位相ずれ である。また電磁波のエネルギの流れはl IE l 
”に比例する。そして、これは、各時間当たりのエネル
ギ流であり、これを時間平均したものは、ω である。
In addition, the electric field IE of an electromagnetic wave, which is a plane wave, is lE = l
It can be expressed as E 1sin ((1)t −λ χ+6). Here, IEI is the amplitude of the electric field ω is the angular frequency λ is the wavelength δ is the phase shift. Also, the flow of energy of electromagnetic waves is l IE l
This is the energy flow per time, and the time average of this is ω.

そして、反射波の時間平均したエネルギ流を求めると以
下のようになる。
Then, the time-averaged energy flow of the reflected waves is calculated as follows.

旧空気=lEレジスト IE空気−IE入射波+IE反射波 従って、 IE反射波−IEレジスト−IE入射波となり、これを
、数式化すると l E+ 1sin ((1) を−λX+δ1)= 
l Er  1sin ((J) t−λ7x+δ、)
+ l Eolsin (ωt−λX+δ。)となる、
ここで撚数0.1.rはそれぞれ入射波、反射波、レジ
スト界面の電磁波の物理量を示す。
Old air = lE resist IE air - IE incident wave + IE reflected wave Therefore, IE reflected wave - IE resist - IE incident wave This can be expressed mathematically as l E + 1 sin ((1) - λX + δ1) =
l Er 1sin ((J) t-λ7x+δ,)
+ l Eolsin (ωt−λX+δ.),
Here, the number of twists is 0.1. r represents the physical quantity of the incident wave, reflected wave, and electromagnetic wave at the resist interface, respectively.

ば、時間平均されたエネルギ流が求められる。つまり、 ・5in(ωt−λX+δ。)dL である。一般的に f ’ sin” (ωt+Δ’) dt 。For example, the time-averaged energy flow is determined. In other words, ・5in(ωt−λX+δ.)dL It is. Typically f’ sin” (ωt+Δ’) dt.

f  sin  (ωt+Δr  )  ・sin (
al t+Δ2 ) dt(Δ、Δ1.Δ2は定数) の計算値はωだけで決まる定数であるから、反射波の時
間平均したエネルギ流は a+’1Erl” +a2.l Eel ・l E、1 +3.  ・IEOI” (al、aZ*  a2は定数) で与えられる。
f sin (ωt+Δr) ・sin (
al t+Δ2 ) dt(Δ, Δ1.Δ2 is a constant) Since the calculated value is a constant determined only by ω, the time-averaged energy flow of the reflected wave is a+'1Erl'' +a2.l Eel ・l E,1 +3.・IEOI” (al, aZ* a2 is a constant).

以上のことから、レジストの下地に電気伝導度σ=Oの
物質を考えると、入射光エネルギ流は反射光エネルギ流
とレジストへのエネルギ貯蓄に分解され、一定入射光エ
ネルギ流のもとでは、レジストへのエネルギ貯蓄は反射
光エネルギ流によって決定される。そして、反射光エネ
ルギ流は上式からIE、、lで決定され、IE、lはレ
ジスト膜厚によって決定されるので、レジストへのエネ
ルギ貯蓄はレジスト膜厚によって決定されることとなる
。そして、レジストパターン寸法はレジストへのエネル
ギ貯蓄によって決定されるから、最終的に、一定置光、
一定下地条件のもとでは、レジストパターン寸法はレジ
スト膜厚によって決定されることとなる。
From the above, if we consider a material with electrical conductivity σ = O as the base of the resist, the incident light energy flow is decomposed into the reflected light energy flow and the energy storage in the resist, and under a constant incident light energy flow, Energy storage in the resist is determined by the reflected light energy flow. Then, the reflected light energy flow is determined by IE, , l from the above equation, and IE, l is determined by the resist film thickness, so the energy storage in the resist is determined by the resist film thickness. Finally, since the resist pattern dimensions are determined by the energy storage in the resist,
Under certain underlying conditions, the resist pattern dimensions are determined by the resist film thickness.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来は、レジストパターンの寸法を制御する為に塗布装
置の性能を向上させ、レジスト膜厚を50〜100人の
精度で寸法制御性の良い膜厚に設定していたが、以下の
3点の問題から、塗布側でいくら膜厚を制御しても正し
いレジストパターンを得るのが困難となってきた。
Conventionally, in order to control the dimensions of the resist pattern, the performance of the coating equipment was improved and the resist film thickness was set to a film thickness with good dimensional controllability with an accuracy of 50 to 100 people. Due to this problem, it has become difficult to obtain a correct resist pattern no matter how much the film thickness is controlled on the coating side.

第1に、現実のデバイスでは凸凹があるため、フラット
なウェハ上に塗布した場合の適正膜厚とは異なる@厚に
なってしまう。又、凸凹による膜厚の変化は凸凹の密度
に依存するので、実デバイス上上で適正膜厚を得る為に
はデバイスのパターンが変わるごとに塗布側の条件を変
えなければならない。
First, since actual devices have unevenness, the film thickness differs from the appropriate film thickness when coated on a flat wafer. Furthermore, since the change in film thickness due to unevenness depends on the density of the unevenness, coating conditions must be changed every time the device pattern changes in order to obtain an appropriate film thickness on an actual device.

第2に、下地がレジストの屈折率とほぼ等しい屈折率を
もつ酸化膜等の物質の場合は、レジスト表面からの反射
率(すなわちレジストへのエネルギ貯蓄に相当する)は
酸化膜とレジストとの膜厚の和で決定される。ところが
、酸化膜生成において、生成膜厚の変動、面内バラツキ
は塗布機の膜厚制御性(50〜100人)に比べて悪い
ことが多いため、デバイス上でのレジストの適正膜厚が
ロフト毎に変化したり、縮小投影型露光機の各ショット
毎に変化したりすることとなり、これらを防ぐことは塗
布機では困難となる。
Second, if the underlying material is a material such as an oxide film that has a refractive index almost equal to that of the resist, the reflectance from the resist surface (that is, equivalent to energy storage in the resist) is the difference between the oxide film and the resist. Determined by the sum of film thicknesses. However, when producing an oxide film, fluctuations in the thickness of the produced film and in-plane variations are often worse than the film thickness controllability of the coating machine (50 to 100 people), so the appropriate film thickness of the resist on the device is determined by the loft. It may change from time to time, or change from time to time for each shot of a reduction projection type exposure machine, and it is difficult to prevent this from happening in a coating machine.

第3に、下地がポリシリコンのように電気伝導度σをも
つ場合には、定在波のたち方や、レジストからの反射率
とレジストへのエネルギ貯蓄との完全な相関はないが、
近似的に今までの議論が成立する。そしてこの場合は、
酸化膜等のσ=0の物質とは異なり、反射率に対して膜
厚以外にσという要因が入ってくる。プロセス的にはシ
ート抵抗と呼ばれるもので、絶対値の変動、面内分布共
に膜厚と同様な変化を示す、この膜厚とシート抵抗の2
重変動のもとでは、塗布機により膜厚を制御しても、実
デバイス上での反射率は変動することとなる。
Third, when the base has electrical conductivity σ such as polysilicon, there is no perfect correlation between the standing waves, the reflectance from the resist, and the energy storage in the resist.
Approximately, the discussion up to now holds true. And in this case,
Unlike a substance such as an oxide film where σ=0, the factor σ other than the film thickness affects the reflectance. In terms of process, it is called sheet resistance, and both the absolute value fluctuation and the in-plane distribution change in the same way as the film thickness.
Under heavy fluctuations, even if the film thickness is controlled by a coating machine, the reflectance on the actual device will fluctuate.

本発明は上記のような問題点を解消するためになされた
もので、実デバイス上での反射率の変動によるレジスト
パターン寸法の変動を防ぐことができる縮小投影型の露
光をする半導体製造装置を得ることを目的とする。
The present invention has been made in order to solve the above-mentioned problems, and provides a semiconductor manufacturing apparatus that performs reduction projection type exposure that can prevent variations in resist pattern dimensions due to variations in reflectance on an actual device. The purpose is to obtain.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る半導体製造装置は、露光されるデバイス
と同じ構造をもつ反射率測定マークを備え、該マークの
反射率を測定し、その測定値に応じてデバイスへの露光
量を変化させて露光するものである。
A semiconductor manufacturing apparatus according to the present invention includes a reflectance measurement mark having the same structure as a device to be exposed, measures the reflectance of the mark, and changes the amount of exposure to the device according to the measured value to perform exposure. It is something to do.

〔作用〕[Effect]

この発明においては、露光されるデバイスと同じ構造を
もつ反射率測定マークの反射率を測定し、その測定値に
応じてデバイスへの露光量を変化させるので、どのよう
な状態のウェハであっても、レジストに一定エネルギを
与えることができる。
In this invention, the reflectance of a reflectance measurement mark that has the same structure as the device to be exposed is measured, and the amount of exposure to the device is changed according to the measured value, so no matter what condition the wafer is in. can also impart a certain amount of energy to the resist.

〔実施例〕〔Example〕

以下、本発明の一実施例を図について説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

第1図は縮小投影型露光をする本実施例装置に備えられ
た反射率測定手段を示し、図において、1は既知波長の
光源、2はハーフミラ−13は入射光強度測定器、4は
反射光強度測定器、5はウェハステージ、6はウェハ、
7は反射率測定マークである。
FIG. 1 shows the reflectance measuring means provided in the present embodiment apparatus for reduction projection exposure. In the figure, 1 is a light source with a known wavelength, 2 is a half mirror, 13 is an incident light intensity measuring device, and 4 is a reflection A light intensity measuring device, 5 a wafer stage, 6 a wafer,
7 is a reflectance measurement mark.

ここで上記反射率測定マーク7は、露光されるデバイス
(以下、実デバイスという)のパターンをつくる所と同
じ下地構造、断面構造、及び該パターンの凸凹と同じ密
度を持ち、実デバイスのパターンをつくる所と同じ反射
率になるように作成される。
Here, the reflectance measurement mark 7 has the same underlying structure, cross-sectional structure, and the same density as the unevenness of the pattern of the device to be exposed (hereinafter referred to as the actual device), and forms the pattern of the actual device. It is created to have the same reflectance as the location where it is created.

第2図及び第3図は本発明の一実施例によるMOS)ラ
ンジスタのポリシリコンゲート作成工程において用いる
反射率測定マークを示し、第2図はウェハ上部から見た
図、第3図はその断面を示す。これは第4図に示すよう
な実デバイスのポリシリコントランジスタの一例とほぼ
同じ構造を有し、8は反射率測定用ビームの当たる所、
9.9aはLOGO3のエツジ、10はレジスト、11
はポリシリコン、12はLOGO3の酸化膜、13は反
射率測定用入射ビーム、14は反射率測定用反射ビーム
、llaはポリシリコンゲートである。
2 and 3 show reflectance measurement marks used in the process of manufacturing a polysilicon gate of a MOS transistor according to an embodiment of the present invention, FIG. 2 is a view seen from the top of the wafer, and FIG. shows. This has almost the same structure as an example of a polysilicon transistor in an actual device as shown in FIG.
9.9a is the edge of LOGO3, 10 is the resist, 11
is polysilicon, 12 is an oxide film of LOGO3, 13 is an incident beam for measuring reflectance, 14 is a reflected beam for measuring reflectance, and lla is a polysilicon gate.

また、反射率測定用ビームは、コリメートされてウェハ
上の反射率測定マーク7に照射される訳であるが、種々
の反射率測定マークが考えられるので、ビーム径は1μ
程度にしぼったものとする。
In addition, the reflectance measurement beam is collimated and irradiated onto the reflectance measurement mark 7 on the wafer, but since various reflectance measurement marks are possible, the beam diameter is 1μ.
It shall be limited to a certain extent.

またその波長は、露光波長を用いても良く、あるいはレ
ーザー等の非露光波長を用いて、これによる実測の反射
率を露光波長での反射率に変換するようにしても良い。
Further, as the wavelength, an exposure wavelength may be used, or a non-exposure wavelength such as a laser may be used, and the measured reflectance may be converted to reflectance at the exposure wavelength.

次に本実施例装置の動作について説明する。露光しよう
とする実デバイスと同じ構造の反射率測定マークをアラ
イメントマークを用いてアライメントする等して作成し
、この反射率測定マーク7を第1図に示す反射率測定手
段の反射率測定用ビームの当たる位置に移動させる。そ
して該ビームを照射し、入射光強度と反射光強度をそれ
ぞれの測定器3.4で測定し、反射率を計算する。次に
、該反射率と露光量を決定した時の反射率とを比較し、
その比を既存の露光量に演算する。そしてこのようにし
て各露光処理毎に露光量をレジストに貯蓄されるエネル
ギが一定となるよう変化させることにより、レジストパ
ターンの寸法を常に一定とできる。そして求められた露
光量でウェハを露光する。ここで本実施例装置のプログ
ラムには、各工程毎に反射率を入力できる項目を付加し
ておかねばならないが、これは自動入力でも良く、手動
入力でも良い。
Next, the operation of the apparatus of this embodiment will be explained. A reflectance measuring mark 7 having the same structure as the actual device to be exposed is created by aligning it using an alignment mark, and this reflectance measuring mark 7 is used as the reflectance measuring beam of the reflectance measuring means shown in FIG. Move it to the position where it hits. Then, the beam is irradiated, the incident light intensity and the reflected light intensity are measured by respective measuring devices 3.4, and the reflectance is calculated. Next, compare the reflectance with the reflectance when determining the exposure amount,
The ratio is calculated to the existing exposure amount. In this way, by changing the exposure amount for each exposure process so that the energy stored in the resist remains constant, the dimensions of the resist pattern can always be kept constant. Then, the wafer is exposed with the determined exposure amount. Here, an item for inputting the reflectance for each process must be added to the program of the apparatus of this embodiment, but this may be input automatically or manually.

一般にレジスト膜厚はウェハの半径方向に変動する傾向
をもち、下地膜の膜厚とシート抵抗も面内分布をもって
おり、このような状態でウェハ面内を同一露光量で露光
すると、レジストパターン寸法の面内分布をまねいてし
まうこととなるが、本実施例装置のように、反射率測定
の機能を備えることにより、各ショット毎に反射率を測
定して各ショット毎にレジストに一定エネルギを与える
露光量で露光することができ、ウェハ面内の寸法制御性
を向上させることができる。
In general, the resist film thickness tends to vary in the radial direction of the wafer, and the underlying film thickness and sheet resistance also have in-plane distribution.If the wafer is exposed with the same amount of light under these conditions, the resist pattern size will change. However, by having a reflectance measurement function like the device of this embodiment, it is possible to measure the reflectance for each shot and apply a constant energy to the resist for each shot. Exposure can be performed with the given exposure amount, and dimensional controllability within the wafer plane can be improved.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、実デバイスと同じ構造
をもつ反射測定マークの反射率を測定し、その測定値に
応じてデバイスへの露光量を変化させて露光するように
したので、どのような状態のウェハであっても常にレジ
ストに一定エネルギーを与えることができ、レジストパ
ターンの寸法制御性を向上できる効果がある。
As described above, according to the present invention, the reflectance of a reflection measurement mark that has the same structure as the actual device is measured, and the amount of exposure to the device is changed according to the measured value. Even if the wafer is in such a state, constant energy can always be applied to the resist, which has the effect of improving the dimensional controllability of the resist pattern.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例による半導体製造装置に備
えられた反射率測定手段を示す概略構成図、第2図及び
第3図はこの発明の一実施例による半導体製造装置に備
えられた反射率測定マークを示す平面図及び断面図、第
4図はその反射率測定マークとほぼ同じ構造を有するポ
リシリコントランジスタを示す平面図、第5図は露光時
のレジスト内での波形を説明するための図、第6図は露
光時のレジスト内での光エネルギーの割合を説明するた
めの図である。 図において、1は光源、2はハーフミラ−13は入射光
強度測定器、4は反射光強度測定器、5はウェハステー
ジ、6はウェハ、7は反射率測定マーク、8は反射率測
定用ビームの当たる所、9はLOGO3のエツジ、10
はレジスト、11はポリシリコン、12はLOGO3の
酸化膜、13は反射率測定用入射ビーム、14は反射率
測定用反射ビームである。 なお図中同一符号は同−又は相当部分を示す。
FIG. 1 is a schematic configuration diagram showing a reflectance measuring means provided in a semiconductor manufacturing apparatus according to an embodiment of the present invention, and FIGS. 2 and 3 show reflectance measuring means provided in a semiconductor manufacturing apparatus according to an embodiment of the present invention. A plan view and a cross-sectional view showing a reflectance measurement mark, FIG. 4 is a plan view showing a polysilicon transistor having almost the same structure as the reflectance measurement mark, and FIG. 5 explains the waveform in the resist during exposure. FIG. 6 is a diagram for explaining the ratio of light energy within the resist during exposure. In the figure, 1 is a light source, 2 is a half mirror, 13 is an incident light intensity measurement device, 4 is a reflected light intensity measurement device, 5 is a wafer stage, 6 is a wafer, 7 is a reflectance measurement mark, and 8 is a reflectance measurement beam 9 is the edge of LOGO3, 10
11 is a resist, 11 is polysilicon, 12 is an oxide film of LOGO3, 13 is an incident beam for measuring reflectance, and 14 is a reflected beam for measuring reflectance. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] (1)マスクパターンをレジストに転写するため露光す
る半導体製造装置において、 露光されるデバイスと同じ構造をもつ反射率測定マーク
と、 該マークの反射率を測定する反射率測定手段と、該測定
手段により得られる測定値に応じて露光量を変化させる
露光量制御手段とを備えたことを特徴とする半導体製造
装置。
(1) In a semiconductor manufacturing apparatus that performs exposure to transfer a mask pattern to a resist, the following equipment is provided: a reflectance measurement mark having the same structure as the device to be exposed, a reflectance measurement means for measuring the reflectance of the mark, and the measurement means. 1. A semiconductor manufacturing apparatus comprising: an exposure amount control means for changing an exposure amount in accordance with a measured value obtained by the method.
JP61034063A 1986-02-18 1986-02-18 Semiconductor manufacturing apparatus Pending JPS62190837A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61034063A JPS62190837A (en) 1986-02-18 1986-02-18 Semiconductor manufacturing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61034063A JPS62190837A (en) 1986-02-18 1986-02-18 Semiconductor manufacturing apparatus

Publications (1)

Publication Number Publication Date
JPS62190837A true JPS62190837A (en) 1987-08-21

Family

ID=12403804

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61034063A Pending JPS62190837A (en) 1986-02-18 1986-02-18 Semiconductor manufacturing apparatus

Country Status (1)

Country Link
JP (1) JPS62190837A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60177623A (en) * 1984-02-24 1985-09-11 Hitachi Ltd Exposure device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60177623A (en) * 1984-02-24 1985-09-11 Hitachi Ltd Exposure device

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