JPS62190528A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To perform various shift processings efficiently and reduce the amount of hardware to facilitate an arithmetic unit into an LSI by cascading a right shift circuit and a left shift circuit with an arithmetic operating circuit between them. CONSTITUTION:A right shift circuit 27 shifts right output data from a mantissa part selecting part 24 by a prescribed number of bits on a basis of shift extent data from a selector 36 and gives shifted data to an arithmetic operating circuit 28. Output data of the circuit 27 and that of the selecting part 24 are inputted to the circuit 28 and are subjected to arithmetic operation, and the circuit 28 gives the operation result to a temporary register 29. A left shift circuit 33 shifts left output data of the register 29 by a prescribed number of bits on a basis of shift extent data from a selector 37 and gives shifted data to an output register 35. The circuit 27, the circuit 28, and the circuit 33 are operated to perform arithmetic shift, addition/subtraction of the mantissa part, and normalizing shift respectively, thus performing various shift processings efficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention provides an arithmetic device that performs signal processing operations, in particular, a fixed-point digital converter from an A/D converter (analog-to-digital converter). Data is input as data, the fixed point data is converted to floating point data, digital signal processing is performed, the resulting floating point data is converted to fixed point data, and a 0/^ converter (digital to analog The invention relates to an arithmetic device that performs arithmetic operations such as output to a converter.

(Prior Art) In general, when digital signal processing is performed in the form of floating point data that has a wide dynamic range for arithmetic processing, the digital signal processing in A/D and D/A converters that convert external analog signals is Since the data format of the data is fixed point data, it is necessary to convert the data format between fixed point data and floating point data. Therefore, a digital signal processor dedicated to signal processing is required to have an arithmetic unit that can process both fixed point data and floating point data. Furthermore, since the signal processing operations performed by this arithmetic device are basically arithmetic operations, both right shift and left shift processing are required when processing operation data.

2. Description of the Related Art Conventionally, there has been an arithmetic device having processing functions for right shift and left shift, as described in, for example, Japanese Unexamined Patent Publication No. 59-534/1. The configuration will be explained below using figures.

FIG. 2 is a configuration block diagram showing a conventional parallel shift device, which is a type of arithmetic device.

This parallel shift device includes a shift number detection circuit 1 that detects the number of shifts required to normalize input data X. For example, input data
As a base number with two's complement representation, X-X SX 1
5...×1 (where XS is a sign bit) In order to perform a normalization shift, the shift number detection circuit 1 uses H88 of input data X, that is, successive signals starting from sign bit Xs. It has a function of counting the number of "011" or "1" and outputting a predetermined shift number signal Z for normalization, and is composed of a bit inversion section, a bit inversion phase detection section 3, and an encoder 4.

The pill inverter 2 picks up the sign bits 1 to Xs of the input data X.
If is "O'', perform bit inversion over two digits of X,
If the sign bit
This is a circuit that gives The bit inversion phase detection unit 3 detects “1” only in the digit corresponding to the bit position immediately before the bit value of the input data first inverts from “1” to “O” when viewed from the sign bit side, and in the other digits. It has a function of outputting "'O" and giving it to the encoder 4. The encoder 4 inputs the output of the pick-up inversion digit detection unit 3 and outputs the pick-up for the first time immediately after the bit number counting from the sign bit Xs of the input data.
This circuit converts whether or not a shift signal has occurred into a 4-bit binary number, generates a shift number signal Z, and outputs it.

Further, the parallel shift device is provided with an absolute value generation section 5, a shift mode selector 6, parallel circuits 971 to 7, 8, a shift circuit selector 9, and a shift circuit output selector 10.Here, The absolute value generator 5 is a circuit that inputs data M (=m5m4...ml) representing the number of shifts and outputs the absolute value H8 as a 4-bit binary number, and the shift mode selector 6 selects a 1-bit shift mode. Controlled by the selection signal SH, either the output Z of the encoder 4 or the output HA of the absolute value generation section 5 is selected and the output signal &(=S45
332 Sl). The parallel shift circuits 7 and 8 use the output signal S as a reference input and input data X (=
X, ×15... Each has a shift function. Shift circuit selector 9
is a circuit that outputs a control signal to the shift circuit horn selector 10 by referring to the positive/negative bit shift number of data M and the shift mode selection signal SR, and the shift circuit output selector 10 outputs a control signal to the shift circuit horn selector 10 based on the control signal. Shift circuit 7 or 8
Select output data Y (=y, ”15
...yl). In the above configuration, in the case of an arithmetic shift of fixed point data, the absolute value output (IA) of the absolute value generator 5 is used, and in the case of a normalized shift of floating point data, the output Z of the encoder 4 is used to select the shift mode. parallel shift circuits 7 and 8
given to. Then, one parallel shift circuit 7 shifts the input data X to the left by a predetermined bit, and the other parallel shift circuit 8 shifts the input data X to the right by a predetermined bit. The shift circuit output selector 10 selects the output of the parallel shift circuit 8 if the shift number is negative in the arithmetic shift mode, and selects the output of the parallel shift circuit 8 if the shift number is negative in the arithmetic shift mode. For example, the outputs of the parallel shift circuit 7 are selected and outputted.

This type of parallel shift device realizes two operation modes, arithmetic shift and normalization shift, of N-digit parallel binary data with less hardware by sharing the parallel shift circuits 7 and 8. There is.

(Problems to be Solved by the Invention) However, the apparatus shown in FIG. 2 has the following problems.

In the apparatus shown in FIG. 2, in one shift operation, data X is input to both left and right shift circuits 7, 8, and these quantity shift circuits 7, 8 operate. Normally, only one of the left shift results is required, so a shift circuit output selector 10 is provided to output the required result. Therefore, it is a redundant circuit, and the LSI
It is disadvantageous to

Also, when performing addition/subtraction operations on floating point data, right shift processing is performed to align the digits between the two input data before the operation, then addition/subtraction is performed, and then left shift processing is performed to normalize the result. Since the flow of processing is to obtain the final result, the shift operation shown in FIG. 2 is required twice, once before and after the arithmetic processing. If we try to realize this with hardware, two sets of parallel shift circuits 7, 8, etc. (as shown in Figure 2) will be required, which will increase the number of redundant circuits, which will be disadvantageous for LSI implementation.In order to avoid this, software If this is realized using a shift circuit output selector, etc., the number of steps in the program will increase and the processing time will be extended. The object of the present invention is to provide an arithmetic device that solves the problem that the circuit configuration is disadvantageous when integrated into an LSI.

(Means for Solving the Problems) In order to solve the above problems, the present invention is capable of processing fixed point data and floating point data, and converting the fixed point data into the mantissa of the floating point data. In a two-input arithmetic operation device for binary data that can be processed as a unit, a stone shift circuit and a left shift circuit are connected in series via an arithmetic operation circuit. Here, the right shift circuit is the first
and the first shift amount data obtained by subtracting the exponent part of the second input calculation data, or the second shift amount set by the microinstruction, as the shift amount, and the first input An arithmetic operation circuit that shifts the mantissa part of the operation data to the right takes the output data of the right shift circuit as a first input, and uses the mantissa part of the second input operation data as a second input and inputs the first and second inputs. A circuit that performs arithmetic operations on a second input, a left shift circuit, receives either the second shift amount data or normalized shift amount detection data for normalizing the output of the arithmetic operation circuit. This circuit shifts the output data of the arithmetic operation circuit to the left as a shift amount.

(Function) According to the present invention, since the arithmetic device is configured as described above, the right shift circuit performs arithmetic shifts 1 to 1, and the arithmetic operation circuit performs addition and subtraction of data mantissa parts. Further, the left shift 1~ circuit operates to perform a normalization shift. These circuits allow various types of shift processing to be performed efficiently. Therefore, the above-mentioned problem can be eliminated.

(Embodiment) FIG. 1 is a block diagram of the configuration of an arithmetic device showing an embodiment of the present invention.

This arithmetic unit consists of pipeline registers (i.e.
This device employs a two-stage pipeline processing configuration using temporary registers), and includes an instruction decoding section 20, input registers 21 and 22, an arithmetic shift amount detection section 23, a mantissa selection section 24, an exponent selection section 25, Exponent comparison unit 26, stone shift 1 to circuit 27, arithmetic operation circuit (hereinafter referred to as group A) 28
, temporary register (hereinafter referred to as TR) 29.3
0.31, normalized shift amount detection section 32, left shift circuit 3
3, an exponent part correction section 34, an output register 35, and selectors 36 and 37.

Here, the instruction decoding section 20 is a circuit that decodes the microinstruction and provides the decoding result to the arithmetic shift mother detection section 23. The arithmetic shift detection unit 23 is a circuit that detects the shift 1 amount control signal output from the instruction decoding unit 20 and provides shift amount data (second shift amount data) of the signal to the selector 36.

Each input register 21.22 has an exponent part 21a.

This circuit has a data holding area of 22a and mantissa parts 21b and 22b, and temporarily holds input calculation data to be processed (hereinafter simply referred to as input data). The mantissa part 22b of each input register 21.22 is connected to the mantissa selection part 24, and the exponent parts 21a and 22a are connected to the exponent part selection part 25 and the exponent part comparison part 26, respectively. The mantissa selection section 24 is a circuit that selects the data held in the mantissa section 21b or 22b based on the output signal of the exponent comparison section 26 and supplies it to the right shift circuit 27 or ALU 2B. The exponent part selection unit 25 is a circuit that provides data held in the exponent part 21a or 22a to the TR 31. In addition, the exponent part comparison unit 26 calculates the absolute value of the difference between the data held in both the exponent parts 21 and 22a, and calculates the absolute value of the difference between the data held in both the exponent parts 21 and 22a, and calculates the absolute value of the difference between the data held in both the exponent parts 21 and 22a to shift the digit alignment data (
A circuit that generates first shift amount data), supplies the shift amount data to the selector 36, and outputs an output signal according to the comparison result of the held data to perform a switching operation of the mantissa selection section 24. be.

The selector 36 is connected to the arithmetic shift detection section 23. and the right shift circuit 27 and the right shift circuit 27 and the right shift data output from the exponent part comparison section 26.
It is a circuit that gives 30. The right shift circuit 27 is a circuit that shifts the output data from the mantissa selector 24 to the right by a predetermined number of pips based on the shift data from the selector 36, and transfers the shifted data to the ALU 28. give to The ALU 28 is a circuit that performs two-man arithmetic operations using the output data of the circuits 6971 to 27 as the first input and the output data of the mantissa selector 24 as the second input, and sends the operation results to the TR 29. Given.

TR29 is a circuit that temporarily holds the output data of the ALU 28 and provides it to the normalization shift mother detection unit 32 and the left shift circuit 33, and further, TR30 temporarily holds the output data of the selector 36 and provides it to another selector 37. circuit,
TR31 is a circuit that temporarily holds the output data of the exponent selection section 25 and supplies it to the exponent correction section 34.
' The normalized shift amount detection section 32 operates in the same manner as the conventional shift number detection circuit 1 shown in FIG.
This circuit detects the normalized shift amount from the output data of , outputs the normalized shift amount detection data, and inputs it to the selector 37. The selector 37 is a circuit that selects one of the surface output data of the TR 30 and the normalized shift amount detection section 32 and supplies it to the left shift circuit 33 and the exponent part correction section 34. The left shift circuit 33 is a circuit that shifts the output data of T1129 to the left by a predetermined number of bits based on the shift amount data given from the selector 37, and its output is given to the output register 35. The exponent part correction unit 34 is a circuit that inputs the output data of the TR 31 and the selector 37 and performs a correction operation for normalization. section 34 and left shift circuit 33
This is a circuit that temporarily holds the output data.

Next, the operation will be explained with reference to FIGS. 3(1) to (4). In FIG. 3, △ indicates the time of the cell 1 of the input registers 21 and 22, O indicates the time of the cell 1 of the TRs 29 to 31, and x indicates the time of the cell 1 of the output register 35, respectively.

(I> Fixed-point data continuous arithmetic shift operation in Figure 3 (1) For example, pipeline operation when 16-bit fixed-point vector data (the most significant bit is the sign bit) is continuously arithmetic shifted I will explain about it.

First, at clock ■1, when the instruction decoder 20 decodes the microinstruction "data input", the input registers 21 and 22
The first 16-bit data ooiooo...0 is input to the mantissa part 21b or 22b.

Next, at clock T2, when the instruction decoder 20 decodes the microinstruction "shift left 1 bit and input data", the arithmetic shift detector 23 detects the shift amount control dll signal output from the instruction decoder 20, and The shift amount data of the signal is sent via the selector 36 to TI'? 30. Here, the shift amount data is TR according to the Schiffmill direction.
30 only. Roughly speaking, the input data ooiooo...O selected by the mantissa selection unit 24 is directly AL
When applied to U28, the input data passes through ALU28 as is and is input to TR29. On the other hand, at this time, the second data 01 is stored in the input register 21 or 22.
0100...0 is input.

Further, moving to clock T3, when the first data output and the right 2-bit shift instruction are decoded by the instruction decoding section 20,
The shift amount data held in TR30 is transferred to selector 3.
7 to the left shift circuit 33. Then, T
The first input data input from R29 to the left shift circuit 33 is shifted to the left by 1 bit, and the shift result is 010.
0-...0 is given to the output register 35. On the other hand, the second data input at the previous clock T3 is given to the right shift circuit 27 via the mantissa selection section 24, and the right shift circuit 27 converts the right 2-bit shift amount from the arithmetic shift amount detection section 23. The data is shifted and the shift result is 00010100...O or TR2 is passed through ALU28.
given to 9.

At clock T4, the shift data of the second data held in TR29 passes through left shift circuit 33 with a shift amount O and is output to output register 35.

(II> Floating point data exponent arithmetic shift 1 to operation in Figure 3 (2) For example, floating point data 01100 with 16 bits of mantissa and 6 bits of exponent... OX2 to the right 3
The case of bit shifting will be explained.

Now, assuming that the floating point data is input to the input register 21 at clock {circle around (2)} 1, the exponent selector 25 selects the data in the input register 21 and supplies it to the TR 31 at clock T2. On the other hand, the arithmetic shift I-amount detection section 23 detects the right 3-bit shift amount control signal output from the instruction decoding section 20, and supplies the shift amount data of the signal to the IR 30 through the selector 36. The mantissa data of the floating point data is selected by the mantissa selector 24 in the same way as the exponent part, and is directly given to the AL028. Then, the mantissa data passes through the ALU 28 as is and is input to the TR 29.

At clock T3, the exponent part data in TR31 is sent to the exponent part correcting part 34, and the shift amount data in TR30 is sent to the exponent part correcting part 34 via the selector 37. Then, the exponent part correction section 34 corrects the exponent part binary data from 000010 to 000110, and outputs it to the exponent part 35a of the output register 35. Zarani, Ding R2
The data in 9 passes through the left shift circuit 33 shift by an amount O and is output to the mantissa part 351) of the output register 35.

(III) Data format conversion operation from fixed point data to floating point data in Figure 3 (3) For example, the scaling constant (normalization constant) of the data exponent part is 4 (
A case will be described in which the 16-bit fixed point data oooiiioo...0, which is 000100(2)), is converted to floating point data.

First, at clock T1, fixed point data is input to the mantissa part 21 of the input register 21, 22 by a data input command.
b or 22b, and a scaling constant is input to the exponent part 22a or 21a.

At clock T2, the scaling constant selected by the exponent selection section 25 is input to the lR31, and the fixed point data selected by the mantissa selection section 24 is directly input to the TR 29 through the ALU 28.

At clock T3, the scaling constant data in TR31 is input to the exponent correction unit 34, and the fixed decimal point data 000100...O in TR29 is input to the normalized shift amount detection unit 32, where the normalized shift amount is input. 0O1
0 is detected. The normalized shift amount is supplied to the left shift circuit 33 and the exponent correction unit 34 via the selector 37, so the left shift circuit 33 performs a 2-bit shift to the left, and the exponent correction unit 34 performs a correction calculation for normalization oioo→ 0
010 respectively, and output the results to output register 1.
Output to 6. This completes the data format conversion.

(IV) In the digit alignment shift operation clock ■1 in the floating point data addition/subtraction field in FIG. 3 (4), for example, input data 010010
0011000101X 2 is input register 2
1, human data 0100101000010010X
2 is set in the input register 22.

At clock T2, the exponent part of each input data is input to the exponent part comparison part 26, and in this exponent part comparison part 26, the digit alignment shift amount data (that is, the absolute value of the difference between the exponent parts of both human data) before calculation is calculated. It is generated and supplied to the right shift circuit 27 in 4 bits.

At this time, the mantissa selector 24 selects the mantissa data of the input register 21 whose exponent data has a large absolute value as input to the right shift circuit 27 . Then, the mantissa data is shifted to the right by 1 bit to 0010010001100010 by the right shift circuit 27, and then output to the ALU 2B. On the other hand, the mantissa data of the input register 22 is directly supplied to A1.12B via the mantissa selector 24.

When the digit alignment is completed in this way, the ALU 29 performs the operation of adding and subtracting the mantissa part, and sets the result in the TR 29. Thereafter, normalization shift 1 operation is performed by the normalization shift amount detection unit 32 and left shift 1 circuit 33, and the exponent part data correction required for the normalization shift is performed by the exponent part correction unit 33. , their final results are set in the output register 35.

The advantages of this embodiment are as follows.

Since the right shift circuit 27 and the left shift circuit 33 are connected in cascade via the bridge 28, the stone shift circuit 27 and the left shift circuit 1 to
There is no redundant circuit with the circuit 33, and as a result, a conventional shift circuit output selector is no longer necessary, and the amount of hardware can be reduced.

Furthermore, the following processing involving left shift or right shift, which is necessary when handling both fixed point data and floating point data, can be performed efficiently.

■Arithmetic shift processing of fixed point data, ■Processing to digit shift before [pull operation to floating point data], ■Normalization shift processing of floating point data, ■Exponent part arithmetic of floating point data Shift processing, ■Data format conversion processing between fixed-point data and floating-point data.

Furthermore, an arithmetic unit capable of multifunctional shift operations can be realized with a small amount of hardware, which is a great advantage when implementing ISI.

It should be noted that the present invention is limited to the illustrated embodiment, and various modifications may be made to the various circuitry parts of the arithmetic unit shown in FIG.

(Effects of the Invention) As described in detail above, according to the present invention, since the right shift circuit and the left shift circuit are connected in cascade via the ALU, it is possible to shift the entire mantissa data bit width left and right. Not only can various shift processes be performed efficiently, but the amount of hardware can be reduced, and as a result, LSI implementation can be easily implemented.

4. Detailed Description of the Invention FIG. 1 is a block diagram of the configuration of an arithmetic device showing an embodiment of the present invention, FIG. 2 is a block diagram of the configuration of a conventional parallel shift device, and FIG. 2), (3), and (4) are operation explanatory diagrams of FIG. 1.

20... Instruction decoding section, 21.22...
Input register, 23... Arithmetic shift amount detection unit,
24... Mantissa selection section, 25... Exponent selection section, 26... Exponent comparison section, 27...
...Right shift circuit, 28... Arithmetic operation circuit (
ALU), 29, 30.31...Temporary register (IR), 32...Normalization shift amount detection section, 33...Left shift circuit, 34...・・・
Exponent correction unit, 35...output register, 36.
37...Selector.

Arithmetic device of the present invention Helmet 1

Claims (1)

[Claims] Fixed point data and floating point data can be processed,
and in a two-input arithmetic operation device for binary data that can process the fixed point data as the mantissa part of the floating point data, a first shift obtained from subtraction of the exponent part of the first and second input operation data. a right shift circuit that shifts the mantissa part of the first input operation data to the right using either the amount data or the second shift amount set by the microinstruction as the shift amount; an arithmetic operation circuit that performs arithmetic operations on the first and second inputs with output data as a first input and a mantissa part of the second input operation data as a second input; and the second shift amount data. or a left shift circuit that shifts the output data of the arithmetic operation circuit to the left by using either one of the normalized shift amount detection data for normalizing the output of the arithmetic operation circuit as the shift amount. A computing device characterized by: