JPS62188980A - Logical integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a circuit with a minimized increase in the number of terminals necessary for testing a logical circuit, by detecting coincidence or non-coincidence between an output expected value from a memory means and an output pattern obtained by inputting into the logical circuit. CONSTITUTION:At a test, ROMs 1-4 and error detection circuits 7-8 are selectively specified by a ROM selection circuit 10 according to a selecting signal for ROM and logic to be tested to determine which logic should be tested and selectors 5 and 6 are set ready for testing by a normal/test switching signal from an input terminal S. Under such a condition, a clock is supplied to an address generation circuit and synchronizing this clock, addresses of specified ROM 1-4 selected are updated sequentially and test pattern corresponding to addresses inputted into logical circuits 22a 22b. The error detection circuits 7 and 8 compare actual outputs from the circuit 22a and 22b with output expected values from the ROMs 2 and 4 corresponding to the address to judge the coincidence or non-coincidence therebetwee. Then, the results (acceptance or reject) are outputted to an output terminal (E) thereby minimizing the increase in the number of input/output terminals.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a logic integrated circuit, and particularly to a logic integrated circuit consisting of a plurality of logic circuits with different functions, and to easily diagnose each logic circuit. This invention relates to logic integrated circuits capable of

[Background of the invention]

An example of configuring one logic integrated circuit (hereinafter referred to as a multi-chip module) by appropriately connecting the input/output terminals of multiple logic circuits with different functions is given in Nikkei Electronics 1984゜8. The article published in No. 17 titled ``Exploring new methods for LSI packaging such as rCu polyimide and Si/# package'' is known. On the other hand, as a means of testing such multi-chip modules, there is a method of testing each logic circuit that constitutes the multi-chip module, as proposed by the Japanese Patent Publication Publication No. 54-1983.
No. 12375. The test method described in the above publication relates to a case where a plurality of logic circuits having different functions are formed on the same semiconductor substrate. In other words, the test method described in the above publication connects tri-state elements in series to the output terminals of each logic circuit, so that each logic circuit is electrically isolated from other circuits while mounted on a board. This makes it possible to test each logic circuit separately by disconnecting it, connecting an external circuit with the same function as the logic circuit, and inputting the same test numbers and turns. .

However, in order to test each logic circuit of a multi-chip module using the test method described in the above publication, it is necessary to electrically disconnect the logic circuit each time and connect an external circuit with the same function as the logic circuit. Need to connect and test. Therefore, there is a problem in that the throughput decreases during testing.

In addition, the number of terminals of the multichip module equal to the number of input/output terminals of each logic circuit is required for testing. As the number of logic circuits increases, it becomes difficult to secure input/output terminals, making it difficult to test each logic circuit. [Objective of the Invention] The present invention was made in view of the problems of the prior art described above. It is an object of the present invention to provide a multi-chip module configured to be able to test each logic circuit unit without reducing test throughput and to minimize an increase in the number of input/output terminals.

[Summary of the invention]

The logic integrated circuit of the present invention includes a plurality of logic circuits having different functions, and in particular, a first storage means storing a test pattern of the logic circuit on the input side of the logic circuit, and an output of the logic circuit. a second storage means storing the expected value;
Above 1. Address signal generation means for generating an address signal for the second storage means, the expected output value outputted from the second storage means, and the test t! The present invention is characterized in that it includes an error detection means for determining whether the turn is matched or not with the output turn obtained by inputting the turn.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in more detail with reference to embodiments shown in the accompanying drawings. Figures 2 (a) and (b) schematically show a multi-chip module to which the present invention is applied. logic circuit 22
The figure shows a cross-sectional view and a plan view when equipped with a . As shown in FIGS. 2(a) and 2(b), the multi-chip module has caps 7'24. ! : It is connected to the pace 25 and is mother-caged, and is configured to send and receive signals to and from the logic circuit 22 on the mother chip 21 via the external terminal side, the signal hat 27, the ending wire 26, and the internal connection 23. ing.

FIG. 1 shows an embodiment in which the present invention is applied to a multi-chip module as shown in FIGS. 2(&) and (b). As shown in FIG. 1, this multi-chip module has external input terminals 11 to 11 as external terminals. and external output terminal 0. 〜0'' and Clodgis 1] phase-7-
Cμ, a switching signal input terminal S for receiving a signal from Yamado/Test, and an error detection terminal E. Inside the multi-chip module is a logic circuit 22a.

22b is provided. And logic circuit 22 m
On the input terminal side thereof, there is a terminal N, which receives a signal from the outside during normal use. ~N1f11, and a terminal T that receives the test pattern of the logic circuit 22m from ROMI during testing. ~T, and a terminal P that receives the normal/test switching signal from the switching signal input terminal S.
is provided. Further, an error detection circuit 7 is connected to the output terminal side of the logic circuit 22m, which receives the expected output value of each output terminal from the ROM 2, compares it with the actual output value, and detects an error.

Similarly to the logic circuit 22m, the logic circuit 22b also has a terminal N! on its input terminal side that receives signals from the outside during normal use. . ~Nt! l and logic circuit 2 during testing.
2 Terminal T that receives the test pattern b from ROM3
,. ~Ttt and terminal P that receives the normal/test switching signal.
A selector 6 is provided.

Further, the logic circuit 22b is connected to the output side of the logic circuit 22b.
Similarly to M, an error detection circuit 8 is connected which receives the expected output value of each output terminal from the ROM 4, compares it with the actual output value, and detects an error.

In addition, the multi-chip module is provided with an address generation circuit and a ROM selection circuit IO that appropriately selects and outputs the address signal output from the address generation circuit 9 to ROMI, 2, 3.4. There is. For example, when testing only the logic circuit 22a, the ROM selection circuit 10 outputs a predetermined address signal only for ROMI, 2, based on the input ROM-to-test logic selection signal.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

First, in the normal use state, the selector 5.6 is set to the normal use state by a normal/test switching signal inputted to the input terminal S. In this case, external input terminal 1
Signals are input from 1 to ■, and the logic circuits 22m and 22b
A normal state in which signals are output from external output terminals 0° to Oj appears.

On the other hand, during testing, the ROM selection circuit 10 selects the designated ROMs 1 to 4 and the error detection circuits 7 and 8 in response to a ROM/logic to be tested selection signal that determines which logic is to be tested. Next, the normal/test switching signal input to the input terminal S causes the selectors 5 and 6 to be set to the test state.

In this state, by supplying a clock to the address generation circuit 9, a predetermined RO selected in synchronization with the clock is generated.
The addresses of M1 to M4 are updated sequentially, and the test Yaturn corresponding to the address is the logic circuit 22a, 22b.
is input.

A logic circuit 22a corresponding to the input pattern.

The output of 22b is compared with the expected output value corresponding to the address, and its quality is outputted to the error output terminal E.

As is clear from the above explanation, according to this embodiment, the RO
M.By appropriately setting the logic under test selection signal,
It is possible to test the two logic circuits 22m and 22b at the same time or individually.Also, in the above embodiment, a multi-chig mole having two logic circuits was explained, but in this case, The invention is not limited to this, and the number of logic circuits may be arbitrary.

〔Effect of the invention〕

In conventional logic integrated circuits, the number of new terminals equal to the number of input/output terminals of the logic circuit is required, which is a major disadvantage. Furthermore, since the logic circuit to be tested is electrically isolated and external circuits are connected, there is a problem in that throughput is reduced.

In contrast, according to the present invention, when there are generally less than 2 logic circuits to be tested, the number of terminals required for the test is one input terminal for the normal/test switching signal,
The total number of input terminals for ROM/logic under test selection signal, one clock input terminal, and one error detection terminal (3+k
), and the increase in the number of terminals can be kept to a minimum.

Further, according to the present invention, it is not necessary to electrically disconnect the logic circuit to be tested and connect it to an external circuit, and it is possible to test multiple logic circuits simultaneously, thereby preventing a drop in throughput. be able to.

Furthermore, with the advancement of semiconductor technology, when the capacity of ROM becomes sufficient to ensure a failure detection rate of 10%, the logic integrated circuit to which the present invention is applied will be able to be installed with an LSI tester in a logic cage. It is now possible to perform a self-test in the same state as when it was installed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the logic integrated ifl circuit of the present invention, FIG. 2 (IL) is a side sectional view of the logic integrated circuit, and FIG. 3(b) is a plan view of the logic integrated circuit. . 1.2, 3.4...ROM, 5.6...Selector,
7.8...Error detection circuit, 9...Address generation circuit, 10-ROM selection circuit, 22m, 22b-logic circuit, I. ~If11...External input terminal, O4~Oj...External output terminal, S...Switching signal input terminal, C...Clock input terminal, E...Error detection terminal. Agent Patent attorney Tadashi Akimoto Essay 2 (a) Procedural amendment (foot) 1. Indication of the case 1985 Patent Application No. 211154 2. Name of the invention Logic integrated circuit 3. Person making the amendment Related Patent applicant address (residence) 4-6 Kanda Surugadai, Chiyoda-ku, Tokyo Name (510) Hitachi, Ltd. 4, Agent February 24, 1988 6 "Drawings" of the specification subject to amendment Column 7 of ``Brief explanation of the content of the correction'' ゛

Claims (1)

[Claims] 1. In a logic integrated circuit comprising a plurality of logic circuits with different functions, a first storage means storing a test pattern of the logic circuit on the input side of the logic circuit, and an output of the logic circuit. a second storage means storing expected values, and the first and second storage means storing expected values;
an address signal generation means for generating an address signal for the storage means, and a match/mismatch between the expected output value outputted from the second storage means and the output pattern obtained by inputting the test pattern to the logic circuit. 1. A logic integrated circuit comprising: error detection means for making a determination. 2. The address generating means selects the first and second storage means corresponding to a predetermined logic circuit from among the first and second storage means provided corresponding to each logic circuit, 2. The logic integrated circuit according to claim 1, further comprising a function of outputting an address signal.