JPS62187873U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention;
2 and 3 are timing waveform diagrams for explaining the operation of the same configuration, FIG. 4 is a configuration diagram showing a conventional delay element testing method, and FIG. 5 is a measurement explanatory diagram of the same method. 1...Test pulse generator, 2...Delay element under test,
4... Reference delay element, 5... Delay line, 6... Logic circuit,
7, 8... Integrator, 9, 10... Bias offset power supply, 11, 12... Operational amplifier, 13, 14...
Detector.

Claims (1)

[Scope of utility model registration request] a pulse generator that generates repetitive pulses;
A reference delay element serving as a reference for delay time and a first means having a delay line connected to the delay element under test are provided, and the repetitive pulses at the same timing are applied to the reference delay element and the first means. , a third means for generating a bias voltage corresponding to the delay time of the delay line, further comprising a second means for integrating the logical sum of the output pulses of the reference delay element and the first means to obtain a DC voltage; A delay element testing apparatus characterized in that a differential voltage between the integrated voltage and a bias voltage is amplified by an operational amplifier, and a delay time of the delay element under test is measured from the output voltage.