JPS62183186A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable the charge to be inputted in a gate insulating film by a method wherein the field effect from a gate electrode to a substrate surface is abruptly changed in the changing part of gate insulating film of a MISFET as a memory cell. CONSTITUTION:n<+> type semiconductor regions 5 are formed by implanting n<+> type impurity e.g. phosphorus or arsenic using a gate electrode 10 as a mask to be used as a source region in writing-in data and as a drain region in reading-out the same. A channel region 1A covered with thick insulating film 9 below the gate electrode 10 is hardly affected by the electric field effect from the electrode 10. Resultantly, when the electrode 10 is impressed with high potential around 9V in writing-in data, a barrier to potential is formed against the region 1A while a channel region 1B is below the part coating the exposed silicon oxide film 6 of electrode 10 easily forming an inversion layer at low potential around 7V. Through these procedures, electrons can be injected by partially changing potential in the channel regions to lower the writing potential.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and in particular to a memory of a semiconductor storage device in which information is electrically written and information is erased using ultraviolet light. It is related to cells.

[Conventional technology]

EPROM is a type of erasable non-volatile memory.
The memory cell of the 1a ROM consists of an M I S FET in which a control gate electrode is laminated on a floating gate electrode with a thin insulating film interposed therebetween. Information is written into the MISFET, which is a memory cell, by applying a high voltage of about 12.5 V, for example, to the control gate electrode. Regarding EPROM, for example, it is described in "Very LSI Device Handbook" published by Science Forum, November 28, 1980, page 54.

[Problem that the invention seeks to solve]

The inventor of the present invention investigated writing information into the memory cell and found that it is extremely difficult to lower the write voltage. This means that the voltage of the floating gate electrode during writing is the value obtained by dividing the voltage of the control gate electrode according to the ratio of the capacitance between the control gate electrode and the floating gate electrode and the capacitance between the blowing gate electrode and the substrate. Because it will be.

An object of the present invention is to provide a semiconductor integrated circuit device with a new structure and a nonvolatile memory function.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve problems]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, by partially changing the gate insulating film of the MISFET, which is a memory cell, the electric field effect from the gate electrode to the substrate surface changes rapidly in the changed area, creating a potential barrier in the channel region. do. This rapid change in potential is used to inject charges into the gate insulating film.

The configuration of the present invention will be explained below along with examples.

〔Example〕

FIG. 1 is a cross-sectional view of a memory cell according to an embodiment of the present invention, and is a cross-sectional view taken along the line II in FIG. FIG. 2 is a plan view of the memory cell, and FIG. 3 is a plan view of the memory cell with a conductive layer on the semiconductor substrate removed. In addition,
In FIG. 2 and FIG. 3, in order to make the structure of the memory cell easier to see, the insulation films other than the field insulating film are not shown.

1 to 3, reference numeral 1 denotes a semiconductor substrate made of P-type m-crystalline silicon, and a field insulating film 2 made of a silicon oxide film is provided on the surface of 9 to define a memory cell pattern to be described later. be. A p-type channel stopper region 3 is provided on the surface of the semiconductor substrate 1 below the field insulating film 2.

The memory cell of this example is as shown in FIG.

The n4 type semiconductor region 4 and the n' type semiconductor region 5 which are the source region or the drain region on the surface of the semiconductor substrate 1, the silicon oxide film 6 and the silicon nitride film 7 which are gate insulating films, and the CVD on the silicon nitride film 7, for example. The gate electrode 10 is made of, for example, a polycrystalline silicon layer and is deposited mainly on the exposed upper surface of the silicon oxide IEi6 and the side surfaces of the insulating film 9.

Note that FIG. 1 shows a 2-bit memory cell. 1
The two memory cell areas are enclosed by dashed lines in FIG.
As shown with , the plane pattern is rectangular, and between the memory cell regions M there is a field insulating film 2.
and is electrically divided by a channel stopper region 3 therebelow. The rt" type semiconductor region 4 for configuring the memory cell is the n" type semiconductor region of the memory cell connected to the same data line 13, with the center line in the direction in which the word line WL extends as a border. 4 are integrated. Further, the r1° type 16 conductor region 4 is connected to the n of the memory cell adjacent in the direction in which the word line WL extends.
The ゛-type semiconductor region 4 is integrated. That is, the square-shaped semiconductor region 4 extends linearly on the surface of the semiconductor substrate 1 in the direction in which the word line WL extends so as to connect a plurality of memory cells. The 11゜ type semiconductor region 4 is used as a drain region when writing information,
Used as a source area when reading. The n-type semiconductor region 5 is provided at the end of each memory cell region M on the surface of the semiconductor substrate l on the opposite side from the n-type semiconductor region 4. Silicon oxide [6] for forming the gate insulating film is deposited on the entire surface of the semiconductor substrate 1 exposed from the field insulating film 2. A silicon nitride film 7 for forming a gate insulating film extends over the silicon oxide 1EiiG above the n-type semiconductor region 4 with a width larger than that of the n-type semiconductor region 4 and in the same direction as the nI-type semiconductor region 4. There is. Therefore, in the memory cell region M, the silicon nitride film 7 is
The silicon oxide film 6 and the n1
The width of the silicon nitride film 7 provided on the field insulating film 2 on both sides of the type semiconductor region 4 in the memory cell region M is equal to the length of the channel region IA where a potential barrier occurs when writing information, which will be described later. Therefore, the silicon oxide film 6 is covered with the silicon nitride film 7 in the part above the n-type semiconductor region 4 and the part above the channel region IA. , @A portion above the channel region IB and the wedge-shaped semiconductor region 5 where no potential barrier is generated during implantation is exposed from the silicon nitride film 7.

A conductive layer 8 made of, for example, an n-type polycrystalline silicon layer is provided on the silicon nitride film 7 so as to extend in the same direction as the n°-type semiconductor region 4 . Although the conductive layer 8 is not necessarily required when configuring the memory cell, the provision of the conductive layer 8 improves the controllability of the film thickness of the insulating layer 9 on the sides of the conductive layer 8, so that the channel region IA This is effective in improving the uniformity of A high potential of 9 V, for example, is applied to the conductive layer 8 during writing, and the circuit ground potential VsS is applied during reading.
, for example, OV is applied. For example, C
An insulating film 9 made of a silicon oxide film formed by VD is provided on the silicon nitride film 7. The insulating film 9 is for insulating the conductive layer 8 and the goo 1-ffl electrode 1o, and also for separating the gate electrode 10 and the channel region IA so that a potential barrier may be generated in the channel region IA during writing. It is for the purpose of Gate electrode 10 is made of an n-type polycrystalline silicon layer and is formed integrally with word line WL. The word line WL extends between the top of the n+ type semiconductor region 4 and the n' type semiconductor region 5 in the same direction as the n' type semiconductor region 4. Goo 1-electrode 1o and word line WL are:
In the memory cell region M, the silicon oxide film 6 is deposited on the upper part of the channel region IB, that is, on the exposed part of the silicon oxide film 6 and the side surface of the insulating film 9, and the field voltage is aV! It is deposited on the upper surface of the field insulating film 2 and the side surface of the insulating film 9 on X2. The gate electrode 10 and the word line WL may be formed of a high melting point metal film such as Mo, W, Ta, Ti, etc. or a silicide film of the high melting point metal. The an-type semiconductor region 5, which may be a two-layer film formed by laminating films or silicide films, is connected to the gate electrode 10 and the field insulating film 2 in the memory cell region M of the semiconductor substrate 1.
The surface facing the gate electrode 10 is provided on the surface surrounded by the side 10A of the gate electrode 10.
The other side is defined by the field insulating film 2.
The n'' type semiconductor region 5 defined by s is formed by ion implantation of an n type impurity 1 such as phosphorus or arsenic using the gate electrode 10 as a mask for ion implantation. It is used as a source region when writing and as a drain region when reading.

IA and IB below the gate electrode 10 are channel regions, and the channel region IA is a region having a thick insulation vf 49 thereon. For this reason, the electric field from the gate electrode 10 is difficult to act on the channel region 1A, so the region IA
This is equivalent to the fact that there is substantially no gate electrode lO above, and when a high potential of about 9V is applied to the gate fli electrode 10 during information writing, a potential barrier is created in the channel region IA. The channel region IB is a region under the exposed portion of the gate electrode 1O that adheres to the silicon oxide film 6, and is a region where an inversion layer is easily formed at a low voltage of about 0.7V.

Reference numeral 11 denotes an insulating film made of, for example, phosphosilicate glass (PSG), which covers the semiconductor substrate 1 . Reference numeral 13 denotes a data line DL made of the first fi-th aluminum layer, which is connected to the surface of the h°-shaped semiconductor region 5 through a connection hole 12 formed by selectively removing the insulating film 11 on the square-shaped semiconductor region 5. ing. The data line 13 is connected to the rl' type semiconductor region 5 at a circuit ground potential Vss, for example, Ov.
is applied, and a power supply potential Vec, for example 5V, is applied to the n3 type semiconductor region 5 during reading.

Reference numeral 14 denotes a conductive layer made of a first aluminum layer, and the conductive layer 14 is a conductive layer made of a first aluminum layer.
It is connected to the surface of the n' type semiconductor region 4 through a contact hole 15 formed by selectively removing l.

The conductive layer 14 applies a high potential of about 9 V to the n-type semiconductor region 4 during writing, and applies a high potential of about 9 V to the circuit ground potential V during reading.
Apply s s, for example Ov.

Next, the writing principle will be explained.

In writing, 9V is applied to the n'' type semiconductor region 4 connected to the memory cell to be written through the conductive layer 14.
At the same time, a potential of about 9 V is applied to the conductive layer 8 thereon. Thereby, an inversion layer can be reliably formed in the substrate 1 under the conductive layer 8. Therefore, the distance between this inversion layer and the inversion layer generated in the channel IB by the write voltage of the gate electrode 10 is defined by the insulating film 9. Gate electrode lO and insulation r for region 4
r! The alignment of X9 becomes easy, while writing can be reliably performed in any memory cell under the same conditions.

One word line W connected to the memory cell to be written
L is selected by an X decoder (not shown). A high potential (write voltage) of about 9 V is applied to the selected word AIIWL, and the six unselected word lines WL are set to the ground potential Vss (for example, Ov) of one circuit. On the other hand, one data line 13 connected to the memory cell to be written is
Six selected data lines 13 selected by a Y decoder (not shown) are set to the ground potential Vss of the circuit. on the other hand,
A write voltage of about 9V is applied to the unselected data gDL. As a result, a current flows between the source and the drain in the selected 1-bit memory cell, and in the unselected memory cell, the low level (Vsg level) of the word line WL or the equal voltage between the source and the drain causes a current to flow between the source and the drain. No current flows between the drains.

In a memory cell to which writing is performed, a square semiconductor region 5 (
Carriers, that is, electrons flow from the source (source) to the n'-type semiconductor region 4 (drain) through the channel region IB and channel region IA. At this time.

As described above, since a potential barrier is formed in the channel region IA, some of the electrons in the electron flow are scattered by the potential barrier in the channel region IA. These scattered electrons are trapped at the interface between silicon oxide film 6 and silicon nitride film 7 on channel region IA, and writing is performed.

As described above, since writing is performed by scattering electrons by the potential barrier of the channel region IA, the writing potential required for writing in an EPROM having a floating gate electrode is, for example, 9 V, which is lower than 12.5 V.
Writing can be performed at a potential of about 100 yen or less.

Therefore, breakdown of the n'' type semiconductor region 4 of the memory cell is less likely to occur, and dielectric breakdown and breakdown of the gate insulating film of the MISFET forming the write circuit are also less likely to occur.

The electrical reliability of the EFROM can be improved.

Next, the readout principle will be explained.

A circuit ground potential VsS is applied through the conductive layer 14 to the n° type semiconductor region 4 which becomes a source region during reading. n” type semiconductor region 5 which becomes a drain region during readout
is the power supply potential Vcc, for example 5V, through the data line 13.
will be precharged.

A word @WL connected to the gate electrode 10 of the memory cell to be read is selected by a decoder, and a power supply potential V c c 1, for example 5V, is applied to the word line WL. The words MWL other than the word mWL connected to the gate electrode 10 of the memory cell to be read are set to the circuit ground potential Vss, for example ov.

In the selected memory cell, if the memory cell has been programmed, that is, if electrons have been trapped between the silicon oxide film 6 and the silicon nitride film 7, the threshold value of the channel region IA is high and the mutual conductance is high. Therefore, the potential drop of the data line 13 is small. In the case of a memory cell to which writing has not been performed, the mutual conductance is larger than that of a memory cell to which writing has been performed, and therefore, the potential drop of the data line 13 becomes larger.

According to the new technology disclosed in this application, the following effects can be obtained.

(1) MI S FET that constitutes the memory cell
By increasing the thickness of a portion of the gate insulating film to such an extent that a potential barrier is generated in the channel region near one semiconductor region during writing, the writing is performed by scattering carriers at the potential barrier. Therefore, writing can be performed with a low writing potential.

(2) Due to (1) above, breakdown of the semiconductor region of the memory cell during writing, dielectric breakdown of the gate insulating film of the MI S FET forming the writing circuit,
Since breakdown and the like are less likely to occur, it is possible to improve the electrical reliability of the EPROM.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

Since electrons are injected by partially changing the potential of the channel region, the write voltage can be lowered.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a memory cell of an EPROM according to an embodiment of the present invention. FIG. 2 is a plan view of the memory cell, and FIG. 3 is a plan view mainly showing the semiconductor region of the memory cell. l...Semiconductor substrate, 2...Field insulating film, 3.
... Channel stopper region, 4, 5... Semiconductor region of memory cell, 6 (silicon oxide film), 7 (silicon nitride film)... Gate insulating film of memory cell, 8... Conductive layer (polycrystalline silicon layer), 10...gate electrode (for example, made of polycrystalline silicon, formed integrally with the word line), 9
...Insulating film (CVD silicon oxide film), 10A...
One side surface of the gate electrode 10, 11... interlayer insulating film,
12.15... Connection hole, 13... Data line made of aluminum, 14... Conductive layer made of aluminum (Vss or 9V is applied to the semiconductor region 4)
, M...Memory cell area. Agent Patent Attorney Katsuma Ogawa' ゝFigure 1 Figure 2

Claims (1)

[Claims] 1. From an insulated gate field effect transistor having a pair of semiconductor regions spaced apart from each other on the surface of a semiconductor substrate, a gate insulating film on the surface of the semiconductor substrate, and a gate electrode on the gate insulating film. 1. A semiconductor integrated circuit device comprising a memory cell, wherein one of the gate insulating films is thicker than the other to such an extent that a potential barrier is created in a predetermined portion of a channel region. . 2. The thicker part of the gate insulating film is a two-layer film in which a silicon nitride film is laminated on at least a silicon oxide film, and the thinner part is made of only a silicon oxide film. A semiconductor integrated circuit device according to claim 1.