JPS62182959A - I/o emulation circuit - Google Patents

Abstract

PURPOSE:To generate an interruption without executing an erroneous input/ output instruction, by performing the detection of an input/output instruction, or a control for the generation of the interruption within a CPU. CONSTITUTION:Addresses set at registers 107 and 108, and a generated I/O address are compared at a comparator 106, and when the generated I/O address is within the range of set addresses, an I/O trap flag 109 is set at '1', and when it is '0', an address output control line 110 is activated, and the I/O address is outputted to an external address bus 103, and an I/O bus cycle is made run, then the execution of an I/O instruction is completed. On the other hand, when the I/O trap flag 109 is '1', a microprogram 112 starts up the microprogram of an interruption process, and branches it to an interruption process routine, and investigates the address where the interruption is generated from the value of an instruction pointer, and exchanges a stored input/output instruction with a correct input/output instruction, and issues again the I/O address.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a microcomputer, and particularly to an input/output
This relates to an ffl emulation circuit.

[Conventional technology]

One of the problems when trying to port software to a computer system from another existing system is the Ilo used in the software. In other words, if the Ilo address used in the new system is different from the Ilo address used in the existing system, all I/O addresses in that part must be rewritten, but in this case, the hardware Generally speaking, there is no need to change anything, but it is difficult to modify the software. Therefore, there is a way to deal with this problem in terms of hardware in order to port it without changing the software at all.

A conventional example will be explained with reference to FIGS. 3 and 4.

The CPO 301 decodes and executes the program. Here C
If the instruction decoded by the PU 301 is an input/output instruction, the address generator 302 calculates the address, outputs the I/O address through the external address bus 303, and outputs the I/O address.
Run a bus cycle. The range of I/O addresses to be emulated is set in advance in register 307 and register 308. That is, the upper limit I/O address to be emulated is preset in the register 307, and the lower limit address is preset in the register 308.

Next, the CPU 301 emulates j1/O7.
Assume that an I/O instruction for the address is executed and an I/O bus cycle is run. At this time, the external address bus 30
3 to comparator 30B! /O address is input.

On the other hand, the register 3G? and register 308, and if the executed I/O address is within the range of register 307 and register 308, it is determined that the I/O bus cycle is an I/O instruction to be emulated, and the CPU 301 Interrupt line 301
Activate and notify 1. Signal line 305 is activated and input to comparator 306 only when the bus cycle being executed is an I/O bus cycle. When the signal [305 is inactive, the comparator 306 also does not perform a comparison operation. In other words, the comparator 30B determines whether the I/O address is within the address range set in the registers 307 and 308 only when an I/O instruction is issued, and if it is, the CP
Activate interrupt line 308 for U301.

Next, when the old CPU 3 detects an interrupt request from the interrupt line 308, it processes the interrupt according to the flow shown in Figure 4. That is, when an interrupt occurs, the CPU 301 saves the address of the program at the time the interrupt occurred.
Based on this information, it is determined what kind of input/output instruction the instruction executed within the interrupt handling routine was (step 401), and then the executed input/output instruction is converted into the correct input/output instruction ( Step 402) Execute it (Step 403).

Then return to the original program again. By adopting such a method, an incorrect input/output instruction is converted into a correct input/output instruction and re-executed.

[Problem that the invention seeks to solve]

In the conventional I/O estimation circuit described above, the CP
Detection of input/output instructions and control of interrupt generation are performed outside the U, and once an incorrect input/output instruction is executed, the correct input/output instruction is executed again, so if an incorrectly executed input/output instruction The disadvantage is that if some other input/output device is assigned to this address, the system may malfunction. l! ! f, if it is an output command, there is a high possibility that the input/output device will be programmed incorrectly and malfunction before the correct output command is executed.

[Means for solving problems]

The I/O emulation circuit of the present invention includes an input/output instruction detection means, a first . When an input/output command is detected by the second data holding means and the input/output command detection means, the first . Second
A comparison means compares the data stored in the data holding means with the I/O address of the input/output instruction being executed, and the comparison between the comparison means determines that the I/O address of the input/output instruction is the first one. If the data is outside the range of the data stored in the second data holding means, the input/output bus cycle control means activates the input/output bus cycle and continues execution of the input/output instruction, and the comparison means compares the input/output It has internal interrupt generating means for generating an internal interrupt if the I/O address of the instruction is within the range of data stored in the first and second data holding means.

In other words, before executing an input/output instruction, it is determined within the CPU whether it is a correct input/output instruction, and if it is an incorrect input/output instruction, an interrupt is generated without executing an incorrect I/O bus cycle. , only correct input-output instructions can be executed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a microprocessor (CPU) incorporating an embodiment of the I/O emulation circuit of the present invention. Within the CPU/O1, there are registers /O7 and /O8 in which the range of I/O addresses to be emulated, that is, the upper limit I/O address and lower limit 1/O address to be emulated are set in advance, and the CPU10I.
The address generator /O2 generates a 1/O address when the instruction decoded by the input/output command, the I/O trap flag /O8, and the I/O instruction identification signal /O5 are activated. Compare the I/O address generated by O2 with the addresses set in registers /O7 and /O8, and if it is within the range of I/O addresses to be emulated,
”, and if it is outside the range, set Of' / O trap flag /
The comparator /OB is set to O9, and when an input/output command is detected, the I/O command identification signal /O5 is activated, and the I/O command is activated.
/O trap /O8 force (if "Q", activate address output control ° line 1/O and open gate 111, "1"
If so, a microprogram 112 is provided that starts a microprogram for interrupt processing.

Next, the operation of this embodiment will be explained.

CPUl0I decodes and executes the fetched instruction.

CPU10I decodes the instruction and executes microprogram 1.
Execute 12. If the instruction decoded here is an input/output instruction, a microprogram for input/output instructions in the microprogram 112 is run. FIG. 2 is a flowchart of this input/output instruction microprogram. In the initial state, the address output control line 1/O is inactive, and the output of the address to the outside is forcibly suppressed by the gate l11. First, an address generator generates an I/O address. Next, register /O7 and register /
The address preset in O8 and the generated I/O address are compared by comparator/O6, and the generated I/O address is
If the O address is within the set address range, ■/O trap flag/O9 is set to l''.6 Next, the microprogram sets Ilo trap flag/
Checks O9 (step 201), and if it is "o", activates address output control line 1/O, opens gate 111, outputs the I/O address to external address bus /O3, and outputs the I/O address to external address bus /O3. The cycle is run and the execution of the I/O instruction is completed (step 204). On the other hand, if the wrap flag /O8 is 1", the address output control line 1 is
/O remains inactive.

Since the I/O address is not output to the external address bus /O3 and the I/O trap flag /O9 is '1'', the microprogram 112 starts the interrupt processing microprogram and branches to the interrupt processing routine (
Step 203) After branching to the interrupt processing routine, the address where the interrupt occurred is checked from the value of the instruction pointer saved in the stuff at the time of the interrupt, and the incorrect input/output instruction stored there is replaced with the correct input/output instruction. Then I again
Issues /O address. Newly issued correct I/
The O address is register /O7. Since it is not within the address range set in register /O8, comparator l
O8 is! Do not set the IO trap flag /O9 to ``1''.

Therefore, the address output control line 1/O is activated and the gate 111 is opened to transfer the I/O address to the external address bus/
Outputs to O3, executes the /O bus cycle, and completes the execution of the input/output instruction.

〔Effect of the invention〕

As explained above, the present invention detects input/output instructions and controls the generation of interrupts within the CPU, thereby making it possible to generate interrupts without executing erroneous input/output instructions. This has the effect of enabling effective Ilo emulation without causing malfunctions.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a CPU having an embodiment of the I/O emulation circuit of the present invention, FIG. 2 is a flowchart of a microprogram of input/output instructions in the embodiment of FIG. /O C showing emulation circuit
The block diagram of Pu, FIG. 4, is a processing flowchart in the interrupt processing routine. /O1...cpu. 1G2...Address generator. /O3...External address bus. /O5...I/O command identification signal, /OB...
... Comparator, /O?・・・・・・Upper address register, /O8・
...lower limit address register, /O9...
・! lO trap flag, 1/O... address output control line, 111... gate, 112... micro program.

Claims (1)

[Claims] When an output command is detected by the input/output command detection means, the first and second data holding means, and the input/output command detection means,
Comparing means for comparing the data stored in the first and second data holding means with the I/O address of the input/output instruction being executed, and the comparison between the comparing means determines the I/O address of the input/output instruction. If the data is outside the range of the data stored in the first and second data holding means, the input/output bus cycle control means activates the input/output bus cycle and continues execution of the input/output instruction, and the comparing means compares the data. . An I/O emulation circuit having internal interrupt generating means for generating an internal interrupt if the I/O address of the input/output instruction is within the range of data stored in the first and second data holding means.