JPS62181471A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS62181471A JPS62181471A JP2352386A JP2352386A JPS62181471A JP S62181471 A JPS62181471 A JP S62181471A JP 2352386 A JP2352386 A JP 2352386A JP 2352386 A JP2352386 A JP 2352386A JP S62181471 A JPS62181471 A JP S62181471A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- light
- film transistor
- layer
- gate insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 37
- 239000010408 film Substances 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910001936 tantalum oxide Inorganic materials 0.000 claims abstract description 11
- 238000002161 passivation Methods 0.000 claims description 3
- 229910003070 TaOx Inorganic materials 0.000 claims 2
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 11
- 239000011521 glass Substances 0.000 abstract description 7
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052804 chromium Inorganic materials 0.000 abstract description 4
- 239000011651 chromium Substances 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 4
- 239000000126 substance Substances 0.000 abstract description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 238000002834 transmittance Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 241000511976 Hoya Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 239000013543 active substance Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000003599 detergent Substances 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001552 radio frequency sputter deposition Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 229910021642 ultra pure water Inorganic materials 0.000 description 1
- 239000012498 ultrapure water Substances 0.000 description 1
- 238000004506 ultrasonic cleaning Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、薄膜トランジスタに係り、特に光照射時にお
ＣプるＯ Ｎ ／’ＯＦ Ｆ比を十分に大きくすること
のできる７ａ脱トランジスタの構造に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to thin film transistors, and in particular to a structure of a 7a transistor that can sufficiently increase the O N /'O F ratio during light irradiation. Regarding.
［従来技術およびその問題点］
半導体層としてアモルファスシリコン等を用いた薄膜ト
ランジスタは、ガラス基板のように低廉イ【大面槓塁板
上に２次元的に集積してアクティブ７１〜リクスにまと
められ、これと液晶のような光学的活性物質とを紺み合
わせてパネル形ディスプレイを実現したり、スイッチン
グ素子として密着型イメージセンサと同一基板上に形成
されて画像読み取り装置を構成する等、近年注目を集め
ているデバイスである。[Prior art and its problems] Thin film transistors using amorphous silicon or the like as a semiconductor layer are inexpensive like glass substrates. In recent years, it has attracted attention, such as by combining this with optically active substances such as liquid crystals to realize panel displays, and by forming switching elements on the same substrate as contact image sensors to construct image reading devices. This is a device that I collect.
λ９膜トランジスタの素子＠造の代表例としては、第４
図に示す如くゲートＴｉ極１００とソースおよびドレイ
ン電極１０１．１０２とが半導体薄膜１０３の同一面側
にあるコプラナ（Ｃｏｔ） １ａｎａｒ ）形と、第５
図に示す如くゲート電極２００とソースおよびドレイン
電＃Ａ２０１，２０２とが半導体薄膜２０３の異なる側
にあるスタガ（ｓｔａａｑｅｒ ＞形とがある。A typical example of a λ9 film transistor device is the 4th one.
As shown in the figure, there is a coplanar (Cot) type in which the gate Ti electrode 100 and the source and drain electrodes 101 and 102 are on the same side of the semiconductor thin film 103, and a fifth type.
As shown in the figure, there is a staggered type in which the gate electrode 200 and the source and drain electrodes #A 201 and 202 are on different sides of the semiconductor thin film 203.
スタガ形では、電極金属を２回に分けてＪ（Ｌ槓、パタ
ーニングする必要があるのでコブツナ形よりも製造］、
程が複雑になる。しかし半導体薄膜層と絶縁体層とを連
続的に形成できるので、この界面の電気的特性が優れ、
したがってトランジスタ特性が良好であることが多い。For the staggered type, the electrode metal is divided into two parts and J (L, patterning is required, so it is manufactured more than for the kobutsuna type).
The process becomes complicated. However, since the semiconductor thin film layer and the insulator layer can be formed continuously, the electrical properties of this interface are excellent.
Therefore, transistor characteristics are often good.
従来このスタガ形の薄膜トランジスタは、例えば、ガラ
ス基板２０４上にゲート電Ｖ４Ａ２００を形成し、この
上にＣＶＤ法などによってゲート絶縁膜２０５を形成し
た後続いて半導体活性層としてのアモルファスシリコン
ｉ ＩＨ２０３、オーミック接触形成層としてのアモル
ファスシリコンｎ″層（図示せず）を堆積し、最後にソ
ース電極２０１およびドレイン電極２０２を形成するこ
とによって作成されている。Conventionally, this staggered thin film transistor is manufactured by forming a gate voltage V4A200 on a glass substrate 204, forming a gate insulating film 205 thereon by CVD, etc., and then forming an amorphous silicon IH203 as a semiconductor active layer and an ohmic contact. It is created by depositing an amorphous silicon n'' layer (not shown) as a forming layer, and finally forming a source electrode 201 and a drain electrode 202.
ところで、通常、ゲート絶縁膜としては、酸化シリコン
（３１０２＞膜（例えば、特公昭５８−１９００６１号
公報参照）、シラン（Ｓｉト１４）と窒素（Ｎ２）との
プラズマ分解による窒化シリコン＜Ｓｉ ３ Ｎ４）膜
（例えば、特公昭５７−１４７２７９号公報参照）等が
使用されている。By the way, the gate insulating film is usually made of silicon oxide (3102> film (see, for example, Japanese Patent Publication No. 190061/1983), silicon nitride <Si3> formed by plasma decomposition of silane (Sito14) and nitrogen (N2)). N4) membrane (see, for example, Japanese Patent Publication No. 57-147279), etc. are used.
これらのゲート絶縁膜はいずれも、可視光の透過率が８
０％以上と極めて高いため、透光性の基板上に形成され
た薄膜トランジスタにおいては、基板側から、ゲート絶
縁膜を介して半導体層に光が入射する。従って、アモル
ファスシリコン層のように光導電率の高い材料で該半導
体層２０３が構成されている場合、トランジスタがＯＦ
Ｆ状態の時にも光電流が流れるため、０Ｎ１０ＦＦ比が
悪いという問題が生じる。Both of these gate insulating films have visible light transmittance of 8.
Since it is extremely high at 0% or more, in a thin film transistor formed on a light-transmitting substrate, light enters the semiconductor layer from the substrate side through the gate insulating film. Therefore, when the semiconductor layer 203 is made of a material with high photoconductivity such as an amorphous silicon layer, the transistor is
Since photocurrent flows even in the F state, a problem arises in that the 0N10FF ratio is poor.
この問題を解決するためには、新たに遮光層を設けるよ
うにするか又は、基板を非透光性のセラミック基板で構
成する必要があった。しかし、この上うな構成では、液
晶表示等で用いる場合は、透過モードでの表示が不可能
となり、画質の悪い反射モードでの表示で使用しなけれ
ばならないという問題があった。In order to solve this problem, it was necessary to provide a new light-shielding layer or to configure the substrate with a non-light-transmitting ceramic substrate. However, with such a configuration, when used in a liquid crystal display or the like, there is a problem in that display in a transmission mode is impossible, and the display must be displayed in a reflection mode with poor image quality.
本発明は、前記実情に鑑みてなされたもので、透光性基
板上に形成された場合にも遮光層を別に設けることなく
、光照射時においても０Ｎ１０ＦＦ比の優れた薄膜トラ
ンジスタを提供することを目的とする。The present invention has been made in view of the above-mentioned circumstances, and aims to provide a thin film transistor that has an excellent 0N10FF ratio even when irradiated with light without providing a separate light-shielding layer even when formed on a transparent substrate. purpose.
Ｅ問題点を解決するだめの手段］
そこで本発明の薄膜トランジスタでは、ゲート絶縁膜を
光透過率の小さい物質からなる絶縁層で構成するように
している。[Means for Solving Problem E] Therefore, in the thin film transistor of the present invention, the gate insulating film is composed of an insulating layer made of a substance with low light transmittance.
［作用］
すなわち、例えば、ゲート絶縁膜を黒色の酸化タンタル
（Ｔａ Ｏｘ 、 ｘ＜ ２．５）膜で構成することに
より、基板側からの光の入射に対しても、半導体層に光
が入射せしめられることはない。従って、光？ｔｆ流は
発生しないため、薄膜トランジスタがＯＦＦ状態であれ
ば、電流は流れない。[Function] That is, for example, by forming the gate insulating film with a black tantalum oxide (TaOx, x<2.5) film, even when light is incident from the substrate side, the light is not incident on the semiconductor layer. You will not be forced to do so. Therefore, light? Since no tf current occurs, no current flows if the thin film transistor is in the OFF state.
このように、ゲート絶縁膜によって光を遮蔽し、半導体
層における光導電効果を防止することにより、光照射時
における０Ｎ１０ＦＦ比を向上せしめることができる。In this way, by blocking light with the gate insulating film and preventing the photoconductive effect in the semiconductor layer, the 0N10FF ratio during light irradiation can be improved.
［実施例］
以下、本発明の実施例について、図面を参照しつつ詳細
に説明する。[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は、本発明実施例の逆スタガ＠造の薄膜トランジ
スタの断面図である。FIG. 1 is a sectional view of an inverted staggered thin film transistor according to an embodiment of the present invention.
この薄膜トランジスタは、第１図（ａ＞に示す如く透光
性のガラス基板１上に形成されたクロム薄膜のパターン
からなるゲート電極２と、この上層に順次積層せしめら
机た黒色の酸化タンタル（Ｔａ Ｏｘ 、 ｘ＜ ２．
５）層からなるゲート絶縁膜３およびアモルファスシリ
コン１層からなる半導体活性層４と、更にこの上層に互
いに離間して形成されたソース電極５およびドレイン電
極とから構成されており、該ソースおよびドレイン電極
はいずれもオーミック接触層７としてのアモルファスシ
リコンｎ＋層を介して半導体活性層上に形成されている
。This thin film transistor consists of a gate electrode 2 consisting of a pattern of a chromium thin film formed on a transparent glass substrate 1, as shown in FIG. TaOx, x<2.
5) consists of a gate insulating film 3 consisting of a layer, a semiconductor active layer 4 consisting of one layer of amorphous silicon, and a source electrode 5 and a drain electrode formed on the upper layer at a distance from each other. All electrodes are formed on the semiconductor active layer via an amorphous silicon n+ layer as an ohmic contact layer 7.
次にこの薄膜トランジスタの製造方法について説明する
。 。Next, a method for manufacturing this thin film transistor will be explained. .
まず透光性のガラス基板（ＨＯＹＡ ＮＡ−４０）を
中性洗剤で３０分間の超音波洗浄後超純水で洗浄し、リ
ンカ−ドライヤーを用いて充分乾燥させる。First, a translucent glass substrate (HOYA NA-40) was subjected to ultrasonic cleaning for 30 minutes using a neutral detergent, then washed with ultrapure water, and thoroughly dried using a linker dryer.
このようにして形成された透光性のガラス基板１上に膜
厚１５０〇へのクロム（Ｃ「）蒸着膜を形成した後、こ
れをフォトリソエツチングによりバターニングし、第１
図（ｂ）に示す如くゲート電極２を形成する。（、この
とき圧力は１．３Ｘ １０−３次いで、第１図（Ｃ）に
示り如く五＾な化タンタル（Ｔａ２０５）をターゲラ１
−として使用し、酸素分圧を下げたＲＦスパッタリング
法により、ゲート絶縁膜３として膜厚３０００人の黒色
の酸化タンタル（Ｔａ Ｏｘ ）層を形成する。このと
き、ベース圧力をＩＪｘ １Ｏ−３Ｐ ａ以下とした後
、アルゴンガスを導入して圧力を３．８ｘ １０”Ｐ
ａとし放電電力は５００Ｗどする。After forming a chromium (C'') vapor-deposited film to a thickness of 1500 mm on the transparent glass substrate 1 thus formed, this was patterned by photolithography, and the first
A gate electrode 2 is formed as shown in Figure (b). (The pressure at this time was 1.3
A black tantalum oxide (TaOx) layer having a thickness of 3,000 wafers is formed as the gate insulating film 3 by RF sputtering with a lower oxygen partial pressure. At this time, after setting the base pressure to IJx 1O-3P a or less, argon gas was introduced to reduce the pressure to 3.8x 10"P.
a, and the discharge power is 500W.
そして、プラズマＣＶＤ法により基板上に約３０００人
のアモルファスシリコン１ｌｉＨ４を第１図（ｄ）に示
す如く形成する。このとき、基板温度を２００℃とし、
ベース圧力を１．３ｘ １０’Ｐ ａとした後、ト＋２
．ｓ；ｈ４を人々流量１２ＳＳＣＭ、２８ＳＣＣＭで導
入し、圧力を５４Ｐａとする。また放電電力は０．０３
Ｗ／ｃｄとする。Then, about 3000 layers of amorphous silicon 1liH4 are formed on the substrate by plasma CVD as shown in FIG. 1(d). At this time, the substrate temperature was 200°C,
After setting the base pressure to 1.3x 10'Pa,
．． s; h4 was introduced at a flow rate of 12 SSCM and 28 SCCM, and the pressure was set to 54 Pa. Also, the discharge power is 0.03
Let it be W/cd.
この後、リフトオフ法により、アモルファスシリコンｎ
＋層７およびソース・ドレイン電極５゜６を形成づる。After this, amorphous silicon n
+ layer 7 and source/drain electrodes 5.6 are formed.
すなわち、第１図（ｅ）に示す如く、レジストパターン
Ｒを形成した後、ドーピングガスどして２５００ｐｐｌ
の７オスフア（ＰＩ〜１３）を３０３ＣＣＭで流ずと共
に、Ｓ ｉ ｌ−１４を２０８ＣＣＭで流し、圧カフ
５ Ｐａ放雷電力０．３Ｗ ／ ｃｉｉでプラズマＣＶ
Ｄ法によって約５００人のアモルファスシリコンｎ＋層
を＠映する。続いて、膜厚１５００人のクロム蒸着膜を
成膜した後、前記レジストパターンＲを除去し、リフト
オフ法により、ゲート電＋ｆＡ２上をはじめ不要部のア
モルファスシリコンｎ＋層およびクロム蒸着膜を除去し
、コンタクト接触層７およびソース・ドレイン電極５．
６のバターニングを行なう。That is, as shown in FIG. 1(e), after forming the resist pattern R, 2500 ppl of doping gas was added.
7 Ospher (PI ~ 13) was flowed at 303 CCM, S i l-14 was flowed at 208 CCM, and the pressure cuff was
Plasma CV with 5 Pa lightning power 0.3W/cii
Approximately 500 amorphous silicon n+ layers were imaged using the D method. Subsequently, after forming a chromium vapor-deposited film with a thickness of 1,500, the resist pattern R was removed, and unnecessary parts of the amorphous silicon n+ layer and the chromium-deposited film, including on the gate electrode +fA2, were removed by a lift-off method. Contact layer 7 and source/drain electrodes 5.
Perform buttering in Step 6.
このようにして形成された薄膜トランジスタでは、光照
射時においても十分な０Ｎ１０ＦＦ比を得ることができ
る。また製造に際してｂゲート電極を黒色の酸化タンタ
ル膜に代えるの志で何ら工程を付加覆ることなく極めて
容易に製造可能である。ただ、ゲート絶縁膜が非透光性
であるため、ソース・ドレインのバターニングに際して
セルフアライメントが不可能である。従って、バターニ
ングの位置合わＵに注意が必要である。In the thin film transistor formed in this manner, a sufficient 0N10FF ratio can be obtained even during light irradiation. Furthermore, by replacing the b gate electrode with a black tantalum oxide film during manufacturing, it can be manufactured extremely easily without any additional steps. However, since the gate insulating film is non-transparent, self-alignment is not possible when patterning the source and drain. Therefore, it is necessary to pay attention to the positioning U of patterning.
この薄膜トランジスタのＯＮ時（Ｖ（１＝１５Ｖ）およ
びＯＦＦ時（Ｖ（＋ ＝ＯＶ）のドレイン電流１ （た
て軸）と電圧Ｖ９．（横軸）との関係を第２図（ａ）に
夫々曲４Ｉａおよびｂ 、ｂ で示ず。The relationship between the drain current 1 (vertical axis) and the voltage V9. (horizontal axis) when this thin film transistor is ON (V (1 = 15V) and OFF (V (+ = OV)) is shown in Figure 2 (a). Songs 4Ia and b, respectively, not shown.
ｂ は暗時、ｂｌは暗時を示す。このようにす。b indicates dark time, and bl indicates dark time. It's like this.
とｂｌがほぼ等しいすなわち暗時にも電流はほとんど流
れておらず、０Ｎ１０ＦＦ比は十分に大であることがわ
かる。It can be seen that when and bl are almost equal, that is, almost no current flows even in the dark, and the 0N10FF ratio is sufficiently large.
比較のために、ゲート絶縁膜をＳｉ３Ｎ４膜で形成した
従来例の薄膜トランジスタについてのＯＮ＠（Ｖｏ ＝
１５Ｖ）およびＯＦＦ時（Ｖ（＋ ＝０■）のドレイン
電流１．（たて軸）と電圧■Ｏ３（横軸）との関係を第
２図（ｂ）に人々曲線ａ゛およびｂ ’、ｂ ’で
示す。ｂｏ゛は暗時、ｂ１゛は暗時を示す特性曲線であ
る。この場合はＯＦＦ時にも暗時には光電流が流れてお
り、暗時におれる０Ｎ１０ＦＦ比は十分でない。For comparison, ON@(Vo =
Figure 2(b) shows the relationship between drain current 1. (vertical axis) and voltage O3 (horizontal axis) when OFF (V (+ = 0)) and when OFF (V (+ = 0)). It is shown by b'. BO' is a characteristic curve showing the dark time, and b1' is the characteristic curve showing the dark time. In this case, a photocurrent flows in the dark time even when it is OFF, and the 0N10FF ratio in the dark time is not sufficient.
第２図（ａ）および（ｂ）の比較からも本発明の薄膜ト
ランジスタでは従来例の薄膜トランジスタに比べて大幅
に暗時の０Ｎ１０ＦＦ比が改善されていることがわかる
。Comparison of FIGS. 2(a) and 2(b) also shows that the thin film transistor of the present invention has a significantly improved 0N10FF ratio in the dark compared to the conventional thin film transistor.
ところで、ゲート絶縁膜としての酸化タンタル膜の成膜
に際しては、酸素ガス（０２）を導入しても良いが、そ
の１１．？ 、Ｇよ分圧を６ｘ １Ｏ−２Ｐ ａ以下と
する。酸素分圧を６ｘ１０’Ｐａ以上とすると、透光性
の五酸化タンタル膜が形成される。第３図に、成膜時の
酸素分圧（Ｔｏｒｒ）と膜の光透過率（％）との関係を
示づ。このときのスパッタリング条件は基板温度３００
℃、印加電力５００Ｗ、ベース圧力５ｘ １０’Ｔｏｒ
ｒとした。この図からも酸素分圧を６ｘ１０−２Ｐａ以
上とサベきであることがわかる。By the way, when forming the tantalum oxide film as the gate insulating film, oxygen gas (02) may be introduced, but 11. ? , G, the partial pressure is 6x 1O-2P a or less. When the oxygen partial pressure is 6x10'Pa or more, a translucent tantalum pentoxide film is formed. FIG. 3 shows the relationship between the oxygen partial pressure (Torr) during film formation and the light transmittance (%) of the film. The sputtering conditions at this time were a substrate temperature of 300
°C, applied power 500W, base pressure 5x 10'Tor
It was set as r. This figure also shows that the oxygen partial pressure can be kept at 6x10-2 Pa or higher.
なお、このような非透光性の絶縁膜を表面のパッシベー
ション膜として使用することも可能である。この場合、
薄膜トランジスタの半導体層の両面に遮光性の膜が形成
されているため、更に光の遮蔽効果は高められ、素子の
安定化と共に更に光電流を低減し、０Ｎ１０ＦＦ比の優
れた薄膜トランジスタをＩＪることか可能となる。Note that such a non-light-transmitting insulating film can also be used as a surface passivation film. in this case,
Since a light-shielding film is formed on both sides of the semiconductor layer of a thin-film transistor, the light-shielding effect is further enhanced, which stabilizes the device and further reduces the photocurrent, making it possible to create a thin-film transistor with an excellent 0N10FF ratio. It becomes possible.
また、ゲート絶縁膜としては、実施例に限定されること
なく、他の非透光性の絶縁膜も適用ＩＪ能であることは
いうまで−しない。Further, the gate insulating film is not limited to the embodiments, and it goes without saying that other non-light-transmitting insulating films can also be applied.
更に、薄膜トランジスタの構造どしては、スタガ構造の
みならず、コプラナ憫造の場合にも、イ１効である。Furthermore, the present invention is effective not only in a staggered structure but also in a coplanar structure.
［効果］
以上説明したように、本発明の薄膜トランジスタによれ
ば、ゲート絶縁膜を非道光性の絶縁膜で形成しているた
め、光電流を低減し、明時にも０Ｎ１０ＦＦ比を十分に
大きくすることが可能で。[Effects] As explained above, according to the thin film transistor of the present invention, since the gate insulating film is formed of a non-photonic insulating film, the photocurrent is reduced and the 0N10FF ratio is sufficiently increased even during bright times. It is possible.
ある。be.
第１図（ａ＞は、本発明実施例の薄膜トランジスタの断
面ＭＩＪａを示す図、第１図（ｂ）乃至（ｅ）は同薄膜
トランジスタの製造工程図、第２図（ａ）および（ｂ）
は、大々、本発明実施例および従来例の薄膜トランジス
タの電流−雷圧特性曲線を示す図、第３図は、ゲート絶
縁膜としての酸化タンタル層の成膜工程における酸素分
圧と形成された膜の光透過率との関係を示す図、第４図
および第５図は通常の薄膜トランジスタの構造を示ず図
である。
１・・・ガラス基板、２，１００，２００・・・ゲート
電極、３・・・ゲート絶縁膜（４°ａＯＸ＞、４，１０
３．２０３・・・半導体６性層、５，１０１，２０１・
・・ソース電極、６，１０２，２０２・・・ドレイン電
極、７・・・オーミック接触層、２０５・・・ゲート絶
縁膜。
ＤＳ
Ｏ５
第２図（ｂ）
第３図
第５図FIG. 1(a) is a diagram showing the cross section MIJa of a thin film transistor according to an embodiment of the present invention, FIGS. 1(b) to (e) are manufacturing process diagrams of the same thin film transistor, and FIGS. 2(a) and (b)
3 is a diagram showing current-lightning pressure characteristic curves of thin film transistors according to an embodiment of the present invention and a conventional example, and FIG. 4 and 5, which are diagrams showing the relationship with the light transmittance of a film, do not show the structure of an ordinary thin film transistor. DESCRIPTION OF SYMBOLS 1... Glass substrate, 2,100,200... Gate electrode, 3... Gate insulating film (4°aOX>, 4,10
3.203...Semiconductor 6-layer, 5,101,201.
...Source electrode, 6,102,202...Drain electrode, 7...Ohmic contact layer, 205...Gate insulating film. DS O5 Figure 2 (b) Figure 3 Figure 5
Claims (5)
ト絶縁膜を介してゲート電極を形成すると共に、該半導
体活性層に対してゲート電極と同じ側又は他方の側にソ
ース・ドレイン電極を形成してなる薄膜トランジスタに
おいて、 前記ゲート絶縁膜が、非透光性の絶縁膜から構成されて
いることを特徴とする薄膜トランジスタ。(1) A gate electrode is formed on one side of a semiconductor active layer having photoconductivity via a gate insulating film, and a source/drain electrode is formed on the same side as the gate electrode or on the other side of the semiconductor active layer. A thin film transistor formed by forming a thin film transistor, wherein the gate insulating film is composed of a non-light-transmitting insulating film.
ート電極と、ゲート絶縁膜と、半導体活性図と、ソース
・ドレイン電極とが順次積層せしめられた逆スタガ構造
の薄膜トランジスタであることを特徴とする特許請求の
範囲第（１）項記載の薄膜トランジスタ。(2) The thin film transistor is an inverted staggered thin film transistor in which a gate electrode, a gate insulating film, a semiconductor active layer, and a source/drain electrode are sequentially stacked on a transparent substrate. A thin film transistor according to claim (1).
ーション膜は、非透光性を有するものであることを特徴
とする特許請求の範囲第（２）項記載の薄膜トランジス
タ。(3) The thin film transistor according to claim (2), wherein the passivation film covering the surface of the thin film transistor is non-transparent.
ＴａＯｘ、ｘ＜２．５）から構成されていることを特徴
とする特許請求の範囲第（１）項乃至第（３）項記載の
薄膜トランジスタ。(4) The gate insulating film is a non-transparent tantalum oxide film (
3. The thin film transistor according to claim 1, wherein the thin film transistor is made of TaOx, x<2.5.
タル膜（ＴａＯｘ、ｘ＜２．５）から構成されているこ
とを特徴とする特許請求の範囲第（３）項記載の薄膜ト
ランジスタ。(5) The thin film transistor according to claim (3), wherein the passivation film is made of a non-transparent tantalum oxide film (TaOx, x<2.5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2352386A JPS62181471A (en) | 1986-02-05 | 1986-02-05 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2352386A JPS62181471A (en) | 1986-02-05 | 1986-02-05 | Thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62181471A true JPS62181471A (en) | 1987-08-08 |
Family
ID=12112804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2352386A Pending JPS62181471A (en) | 1986-02-05 | 1986-02-05 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62181471A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012103697A (en) * | 2010-11-09 | 2012-05-31 | Beijing Boe Optoelectronics Technology Co Ltd | Array substrate and liquid crystal display |
-
1986
- 1986-02-05 JP JP2352386A patent/JPS62181471A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012103697A (en) * | 2010-11-09 | 2012-05-31 | Beijing Boe Optoelectronics Technology Co Ltd | Array substrate and liquid crystal display |
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