JPS62181044U - - Google Patents
Info
- Publication number
- JPS62181044U JPS62181044U JP6944186U JP6944186U JPS62181044U JP S62181044 U JPS62181044 U JP S62181044U JP 6944186 U JP6944186 U JP 6944186U JP 6944186 U JP6944186 U JP 6944186U JP S62181044 U JPS62181044 U JP S62181044U
- Authority
- JP
- Japan
- Prior art keywords
- output signal
- flip
- flop circuit
- circuit
- timer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Electronic Switches (AREA)
- Measurement Of Predetermined Time Intervals (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6944186U JPS62181044U (de) | 1986-05-09 | 1986-05-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6944186U JPS62181044U (de) | 1986-05-09 | 1986-05-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62181044U true JPS62181044U (de) | 1987-11-17 |
Family
ID=30910177
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6944186U Pending JPS62181044U (de) | 1986-05-09 | 1986-05-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62181044U (de) |
-
1986
- 1986-05-09 JP JP6944186U patent/JPS62181044U/ja active Pending