JPS62179971A - Line feed controller for printer - Google Patents

Line feed controller for printer

Info

Publication number
JPS62179971A
JPS62179971A JP2227786A JP2227786A JPS62179971A JP S62179971 A JPS62179971 A JP S62179971A JP 2227786 A JP2227786 A JP 2227786A JP 2227786 A JP2227786 A JP 2227786A JP S62179971 A JPS62179971 A JP S62179971A
Authority
JP
Japan
Prior art keywords
line feed
circuit
line
data
input data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2227786A
Other languages
Japanese (ja)
Inventor
Kazuya Takagi
和也 高城
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2227786A priority Critical patent/JPS62179971A/en
Publication of JPS62179971A publication Critical patent/JPS62179971A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain the titled controller capable of shortening the period of time required for line feeding by combining pieces of line feed data supplied in succession and executing the line feed in a single line-feeding operation. CONSTITUTION:When an LF code designating the first one-line feed is sent as an input data 1a, a line feed data signal 2b is outputted from an input data analyzing circuit to a set terminal of a continuous line feed mode storage circuit 5, and a continuous line feed mode is set. A line feed data set signal 5a from the circuit 5 is supplied to a line feed number storage circuit 4, which stores a one-line feed 2a. The second and third LF codes supplied from a host device 1 are similarly processed, the numbers of lines of feed are summed up, and three-line feed is stored. When the fourth input data 1a is sent from the host device 1, a line-feeding command 9a and the number of lines of feed stored in the circuit 4 are sent to a line feed driving circuit. Simultaneously, the content in the circuit 4 is reset to 0. Thus, the data for performing a one-line feeding operation three times are converted into data for performing a three-line feeding operation one time.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、プリンタの改行制御装置に関し、特に上位装
置からの入力データにより印字及び改行動作を行うプリ
ンタの改行制御装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a line feed control device for a printer, and more particularly to a line feed control device for a printer that performs printing and line feed operations based on input data from a host device.

〔従来の技術〕[Conventional technology]

従来、プリンタの改行制御装置は、上位装置からの改行
データが送られ来る毎にプリンタ改行動作を実行させて
いた。例えば1行改行の改行データが連続して10個送
られた場合、改行動作は、1行改行動作を10回繰り返
えして行っていた。
Conventionally, a line feed control device of a printer has executed a printer line feed operation every time line feed data is sent from a host device. For example, if 10 pieces of single line feed data are sent in succession, the single line feed operation is repeated 10 times.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のプリンタの改行装置では、上位装置から
改行データが連続して送られてきた場合に、プリンタの
改行実行時間が長くなり、処理時間に悪影響を与えてい
た。
In the conventional printer line feed device described above, when line feed data is continuously sent from a host device, the printer takes a long time to execute the line feed, which adversely affects the processing time.

本発明は、このような不具合をなくし、連続して送られ
てくる改行データを統合し、1回の改行動作で実行する
ようにして改行実行時間を短くすることができるプリン
タの改行制御装置を提供するものである。
The present invention provides a line feed control device for a printer that eliminates such problems and can shorten the line feed execution time by integrating continuously sent line feed data and executing it in a single feed operation. This is what we provide.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のプリンタ改行制御装置は、入力する入力データ
を解析して改行データおよび改行データ信号または印字
データ信号を出力する入力データ解析回路と、連続改行
モードが前記改行データ信号によりセットされ前記印字
データ信号によりリセットされる連続改行モード記憶回
路と、前記改行デートを概に記憶している内容に加算し
て記憶する改行数記憶回路と、前記改行データ信号が消
えてから所定の時間以上経過しても前記入力データがな
いと前記連続改行モード記憶回路の前記連続改行モード
をリセッI・する入力データ監視タイマー回路と、前記
連続改行モード記憶回路の前記連続改行モードがリセッ
I・された時に改行指令と前記改行数記憶回路の記憶内
容を出力するとともに前記改行数記憶回路の記憶内容を
リセットする改行指令送出回路とを含んで構成される。
The printer line feed control device of the present invention includes an input data analysis circuit that analyzes input input data and outputs line feed data and a line feed data signal or print data signal, and a continuous line feed mode is set by the line feed data signal and the print data a continuous line feed mode memory circuit that is reset by a signal; a line feed number memory circuit that adds and stores the line feed date to the generally stored content; an input data monitoring timer circuit that resets the continuous line feed mode of the continuous line feed mode storage circuit if there is no input data, and a line feed command when the continuous line feed mode of the continuous line feed mode storage circuit is reset. and a line feed command sending circuit that outputs the memory contents of the line feed number memory circuit and resets the memory contents of the line feed number memory circuit.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例のブロック図、第2図及び第
3図は第1図に示す実施例におけるタイミングチャート
図である。プリンタは電源投入後、データが受取可能に
なるとパワーオンセフl−信号]Oaを出力し、オア回
路7へ供給する。オア回路7の出カフaは入力データ要
求回路8のセット端子へ加えられ、入力データ要求信号
8aを上位装置1へ送る。上位装置1は入力データ要求
信号8aが送られて来たのでプリンタに入力データ1a
を送出する。入力データ1aは入力データ解析回路2で
解析され、送られた入力データlaが改行データ(1−
Fコード)であると、改行データ(1行)2aと改行デ
ータ信号2bを出力する。又、入力データ1aが印字デ
ータであると印字データ信号2Cを出力する。
FIG. 1 is a block diagram of an embodiment of the present invention, and FIGS. 2 and 3 are timing charts in the embodiment shown in FIG. After turning on the power, the printer outputs a power-on-safe l-signal]Oa when it becomes ready to receive data, and supplies it to the OR circuit 7. The output a of the OR circuit 7 is applied to the set terminal of the input data request circuit 8, and the input data request signal 8a is sent to the host device 1. The host device 1 receives the input data request signal 8a, so it sends the input data 1a to the printer.
Send out. The input data 1a is analyzed by the input data analysis circuit 2, and the sent input data la is converted into line feed data (1-
F code), line feed data (one line) 2a and line feed data signal 2b are output. Further, if the input data 1a is print data, a print data signal 2C is output.

例えば、上位装置1からの入力データ1aが次に示すデ
ータの場合について説明する(第2図のタイミングチャ
ート参照)。
For example, a case will be explained in which the input data 1a from the host device 1 is the following data (see the timing chart in FIG. 2).

入力データ・・・ LP  、  LF  、  LF
  。
Input data... LP, LF, LF
.

(1行改行)(1行改行)(1行改行)印字コード 入力データ1aに最初の1行改行を指示するLドコード
が送られると、入力データ解析回路2から改行データ信
号2bが出力され、連続改行モード記憶回路5のセット
端子へ供給され、連続改行モードがセットされる。さら
に連続改行モード記憶回路5の改行データセット信号5
aが改行数記憶回路4へ加えられ、改行数記憶回路4は
改行データ(1行改行)2aを記憶する。上位装置lか
らの入力データ1aが出力しなくなると、入力データ解
析回路2の改行データ信号2bも出力しなくなり、これ
によって入力データ監視タイマー回路6が動作し、タイ
マー監視を始めるとともに、データ要求セット信号6b
が出力され、入力データ要求回路8は再び上位装置1に
対して入力データ要求信号8aを送出する。これにより
上位装置1は入力データ1aに2番目のLFコードを送
出し、上記と同様に処理される。この場合、改行数記憶
回路4には、前回の改行数1行と今回の改行数1行が加
算され2行改行が記憶される。同様にして3番目の上位
装置1からのLPコードが処理され、改行数記憶回路4
には3行改行が記憶される。
(1 line feed) (1 line feed) (1 line feed) When an L code instructing the first line feed is sent to the print code input data 1a, a line feed data signal 2b is output from the input data analysis circuit 2, The signal is supplied to the set terminal of the continuous line feed mode storage circuit 5, and the continuous line feed mode is set. Furthermore, the line feed data set signal 5 of the continuous line feed mode storage circuit 5
a is added to the line feed number storage circuit 4, and the line feed number storage circuit 4 stores line feed data (one line feed) 2a. When the input data 1a from the host device 1 is no longer output, the input data analysis circuit 2 also no longer outputs the line feed data signal 2b, which causes the input data monitoring timer circuit 6 to operate, start timer monitoring, and set the data request. signal 6b
is output, and the input data request circuit 8 again sends the input data request signal 8a to the host device 1. As a result, the host device 1 sends the second LF code to the input data 1a, and is processed in the same manner as above. In this case, the previous line feed count of 1 line and the current line feed count of 1 line are added to the line feed number storage circuit 4, and 2 line feeds are stored. Similarly, the LP code from the third host device 1 is processed, and the line feed number storage circuit 4
3 line breaks are memorized.

上位装置1から4番目の入力データ1aが送られると、
これは印字データであるため、入力データ解析回路2の
印字データ信号2Cが出力され、これが第3回路3を介
して連続改行モード記憶回路5のリセット端子へ加えら
れるため連続改行モードがリセットされ、連続改行モー
ド記憶回路5の改行指令セ・ソト信号5bが出力され、
改行指令送出回路9へ加えられる。この結果、改行指令
送出回路9は改行指令9aと、改行数記憶回路4に記憶
されている改行数(3行改行)4aを改行駆動回路(図
示せず)へ送る。同時に改行数記憶回路4の内容はOに
される。このようにして1行改行を3回実行するデータ
が3行改行を1回実行するように変換される。
When the fourth input data 1a is sent from the host device 1,
Since this is print data, the print data signal 2C of the input data analysis circuit 2 is output, and this is applied to the reset terminal of the continuous line feed mode storage circuit 5 via the third circuit 3, so that the continuous line feed mode is reset. The line feed command sesoto signal 5b of the continuous line feed mode storage circuit 5 is output,
It is added to the line feed command sending circuit 9. As a result, the line feed command sending circuit 9 sends the line feed command 9a and the line feed number (3 line feeds) 4a stored in the line feed number storage circuit 4 to the line feed drive circuit (not shown). At the same time, the contents of the line feed number storage circuit 4 are set to O. In this way, data in which one line feed is executed three times is converted into data in which three line feeds are executed once.

又、第3図に示すタイミングチャートは、入力データ1
aにLFコードが1個しかなく、以下入力データ1aが
上位装置1から送られて来ない場合を示す。この場合、
最初のLPコードを受は取った後入力データ・監視タイ
マー回路6が働き、′F秒経過しても、入力データが来
ない場合、入力データ監視タイマー回路6のタイムアラ
I・信号6L’Lが出力され、オア回路3を介し°ζ連
続改行モード記憶回路5のリセット端子へ加えられ、連
続改行モードがリセットされ重連の場合と同様にして改
行指令9aが改行駆動回路へ送られる。
In addition, the timing chart shown in FIG.
The case where there is only one LF code in a and the input data 1a is not sent from the host device 1 will be described below. in this case,
After receiving the first LP code, the input data/monitoring timer circuit 6 operates, and if the input data does not come even after 'F seconds have elapsed, the time alarm I/signal 6L'L of the input data monitoring timer circuit 6 is activated. It is outputted and applied to the reset terminal of the °ζ continuous line feed mode storage circuit 5 via the OR circuit 3, the continuous line feed mode is reset, and the line feed command 9a is sent to the line feed drive circuit in the same manner as in the case of double series.

なお、この入力データ監視タイマー回路6のタイムアウ
ト時間T秒は、改行データが連続しない場合の損失時間
を考慮して1行政行実行時間より短くする事が望ましい
Note that it is desirable that the timeout time T seconds of the input data monitoring timer circuit 6 be shorter than the execution time of one administrative execution, taking into consideration the loss time when line feed data is not consecutive.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、入力データ解析回路と、
複数個の改行データを統合するための連続改行モード記
憶回路と改行数を記憶する改行数記憶回路と、入力デー
タの送出を監視する入力データ監視タイマー回路を設け
る事によって、連続する複数個の改行データを統合し1
回の改行動作で実行するため改行処理時間を短縮する事
ができる。
As explained above, the present invention includes an input data analysis circuit,
By providing a continuous line feed mode memory circuit for integrating multiple line feed data, a line feed number memory circuit for storing the number of line feeds, and an input data monitoring timer circuit for monitoring the sending of input data, it is possible to Integrate data 1
The line feed processing time can be shortened because it is executed in one line feed operation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示ずブロック図、第2図及
び第3図は第1図に示す実施例のタイミングチャー1−
図である。 1・・・上位装置、2・・・入力データ解析回路、3・
・・オア回路、4・・・改行数記憶回路、5・・・連続
改行モード記憶回路、6・・・入力データ監視タイマー
回路、7・・・オア回路、8・・・入力データ要求回路
、9・・・改行指令送出回路。
FIG. 1 is a block diagram of an embodiment of the present invention, and FIGS. 2 and 3 are timing charts of the embodiment shown in FIG. 1.
It is a diagram. 1... Host device, 2... Input data analysis circuit, 3.
... OR circuit, 4... Line feed number memory circuit, 5... Continuous line feed mode memory circuit, 6... Input data monitoring timer circuit, 7... OR circuit, 8... Input data request circuit, 9...Line feed command sending circuit.

Claims (1)

【特許請求の範囲】[Claims] 入力する入力データを解析して改行データおよび改行デ
ータ信号または印字データ信号を出力する入力データ解
析回路と、連続改行モードが前記改行データ信号により
セットされ前記印字データ信号によりリセットされる連
続改行モード記憶回路と、前記改行デートを概に記憶し
ている内容に加算して記憶する改行数記憶回路と、前記
改行データ信号が消えてから所定の時間以上経過しても
前記入力データがないと前記連続改行モード記憶回路の
前記連続改行モードをリセットする入力データ監視タイ
マー回路と、前記連続改行モード記憶回路の前記連続改
行モードがリセットされた時に改行指令と前記改行数記
憶回路の記憶内容を出力するとともに前記改行数記憶回
路の記憶内容をリセットする改行指令送出回路とを含む
ことを特徴とするプリンタの改行制御装置。
an input data analysis circuit that analyzes input input data and outputs line feed data and a line feed data signal or print data signal; and a continuous line feed mode memory in which a continuous line feed mode is set by the line feed data signal and reset by the print data signal. a circuit, a line feed number storage circuit that adds and stores the line feed date to the stored contents; an input data monitoring timer circuit that resets the continuous line feed mode of the line feed mode storage circuit, and outputs a line feed command and the memory contents of the line feed number storage circuit when the continuous line feed mode of the continuous line feed mode storage circuit is reset; A line feed control device for a printer, comprising: a line feed command sending circuit for resetting the stored contents of the line feed number storage circuit.
JP2227786A 1986-02-03 1986-02-03 Line feed controller for printer Pending JPS62179971A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2227786A JPS62179971A (en) 1986-02-03 1986-02-03 Line feed controller for printer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2227786A JPS62179971A (en) 1986-02-03 1986-02-03 Line feed controller for printer

Publications (1)

Publication Number Publication Date
JPS62179971A true JPS62179971A (en) 1987-08-07

Family

ID=12078264

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2227786A Pending JPS62179971A (en) 1986-02-03 1986-02-03 Line feed controller for printer

Country Status (1)

Country Link
JP (1) JPS62179971A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05124232A (en) * 1991-10-30 1993-05-21 Sanyo Electric Co Ltd Print controller for multi-line printer
JP2008094449A (en) * 2006-10-13 2008-04-24 Dainippon Printing Co Ltd Lid with hot-water draining function
US7439992B2 (en) * 1998-12-25 2008-10-21 Sanyo Electric Co., Ltd. Communication terminal

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05124232A (en) * 1991-10-30 1993-05-21 Sanyo Electric Co Ltd Print controller for multi-line printer
US7439992B2 (en) * 1998-12-25 2008-10-21 Sanyo Electric Co., Ltd. Communication terminal
JP2008094449A (en) * 2006-10-13 2008-04-24 Dainippon Printing Co Ltd Lid with hot-water draining function

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