JPS62176242A - Line trace equipment - Google Patents

Abstract

PURPOSE:To efficiently troubleshoot an erroneous even in a transmission data by providing a trace start circuit detecting a data frame start pattern of a serial data, a slot counter counting a slot at each prescribed bit number and a trace counter. CONSTITUTION:When a trace start circuit 41 detects a start pattern included in a serial data, the tracing is started and a parallel data 66 converted in the unit of bits decided by a serial/parallel conversion circuit 42 is stored in a trace memory 40. Data signal lines D0-D7, a memory address signal ADR and a memory read/write signal R/W connect respectively to an external microprocessor. Then a memory read/write control circuit 30 switches memory address switch circuits 31, 32 and memory data switch circuits 33-36 to read/ write freely the content of a memory 40 and each memory (a command memory 37, a comparison data memory 38 and a mask data memory 39).

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a data transmission device that connects a plurality of control devices with a transmission line through each transmission control station and mutually transmits and receives data. In particular, the present invention relates to a line tracing device that detects malfunctioning transmissions that occur sporadically in a transmission device that is in operation using serial transmissions, and easily searches for the cause.

(Prior art) In a serial transmission system in which multiple control devices are connected by a data transmission device, if an abnormality occurs in each transmission control station including the control device, each transmission control station detects and determines the abnormality and takes appropriate action. It is common to do so.

However, since a plurality of transmission control stations are interconnected, it is not possible to grasp abnormal phenomena using correct causal functions for individual detection results and make accurate judgments.

In addition, if an error occurs sporadically in the transmission control station, check whether the cause of the error is a problem with the transmission control station circuit or the transmission control procedure.
It is difficult to determine whether the problem is caused by software (software) or by noise, etc., including the line.

If an abnormality occurs in the serial transmission interface or hardware/software, the online scope (online scope) is a device that can store and directly read the data exchanged between each transmission control station, including the control device, to investigate the cause and analyze the abnormality. For example, Northern Telecom Co., Ltd.'s D-901
There are measurement devices such as general-purpose logic analyzers (e.g. Yokogawa Hewlett Paracard Co., Ltd. Model D1630) that have the function of continuously storing and displaying the state transitions of electrical circuits. This is useful when a problem occurs with the transmission equipment.

(Problem to be solved by the invention) The data storage method of the online scope is simply to store and display the sent and received data frames in chronological order, and it mainly shows whether the data was sent or received. Find software bugs by clarifying transmission control interactions. This is effective because it allows you to know the timing of transmission and reception.

However, this type of measurement equipment is also oriented toward public communication networks, and is suitable for serial transmission between devices with standard terminal interfaces, and the applicable line speed is also the highest speed 1.
．． 68bit/sec (digital data transmission line primary group) LAN (local area network) at 8 degrees
When the speed exceeds 108bit/see, which is required by be.

In addition, Logic Scope is a method that uses a specified combination of state transitions of multiple electrical circuits as a condition, and displays the states of electrical circuits within a set range before and after the time the condition is met, with the activation condition being that the condition is met. It is. In this case, since a dedicated circuit is used to determine whether the above conditions are met, the LAN
It satisfies the high speed required for etc. Furthermore, since malfunction events are directly detected based on the voltage circuit status of the hardware, the detection response is good, and since the event can be traced and displayed only when a malfunction occurs, the storage capacity can be limited and the system can be configured compactly.

However, the activation conditions are limited by the number of probes that sense the circuit state, and there is a limit to the use of detecting the occurrence of an event based on a combination of many bits of data that arrive in series, such as in serial data transmission.

In addition, since the activation condition is only a simple combination condition, that is, a match with the data to be compared, in the case of a problem that occurs sporadically and infrequently, it is possible to
It is a 'true' condition detection, and it is difficult to set the condition.Also, there are cases where only consecutive bit strings of data that arrive in bit series are used as an event occurrence condition, or where a certain bit string is compared and subsequent bit strings are ignored. However, there are cases where the next bit string is further compared and the event generation condition is used, and conventional measuring devices cannot adequately meet these demands.

The purpose of the present invention is to establish comparison conditions for long serial bit patterns to detect fault events and to analyze the causes of faults and errors that occur sporadically on serial transmission lines. It is possible to detect cases where the serial bit pattern is different from the original one and set it as a failure occurrence condition, and it is possible to accumulate and display bit serial data that arrives before and after the failure event occurs. The purpose is to provide a possible line tracing device.

[Structure of the invention]

(Means for Solving the Problems) The present invention provides a transmission data viewing device that converts serial data into parallel data every predetermined number of bits and sequentially writes the serial data into a storage device. a trace start circuit for detecting; a slot counter and a trace counter for counting each predetermined number of bits; a trace data memory that is re-addressed by the trace counter and stores the parallel data; and a trace data memory for re-addressing the parallel data by the slot counter. A specified command memory, a comparison data memory, and a mask data memory, and comparison data read from the comparison data memory and a mask read from the mask data memory based on the command data read from the command memory. A comparison circuit that compares data with the parallel data, and a delay circuit that stops the counting of the trace counter after a predetermined time from the detection point of the comparison circuit are designed to efficiently investigate the cause of malfunctions in transmitted data. This is a line tracing device.

(Function) Serial data is converted into parallel data every predetermined number of bits (also called slots), and the slot counter and trace counter are incremented.

The command data, comparison data, and mask data at the address specified by the slot counter are read from the command memory, comparison data memory, and mask data memory, and the comparison data and mask data are compared with the parallel data based on the command data to determine whether they are normal. A determination is made as to whether there is an abnormality.

The command data includes a bit (NOP) that determines whether to perform comparison detection for that slot, a bit (MASK) that determines whether to use mask data, and a true or false condition when comparing data. It is possible to include a bit (T/F) for determining whether to use the slot, a bit (E N D) for specifying the end of comparison detection for that slot, and the like.

When it is determined that there is an abnormality, the slot counter stops counting, and after a predetermined time, the trace counter stops counting and writing of parallel data is stopped.

(Embodiment) A line tracing device of the present invention will be explained using an embodiment shown in FIG.

In the figure, serial data DTIN to be monitored and a trace start signal ST'RT are input to a line tracing device 10, and when a trace start circuit (STAT) 41 detects a start pattern included in the serial data, a trace operation is started. Ru. When the trace operation starts, the serial/parallel converter circuit (
The parallel data 66 converted in bit units (also called slots) determined by the SPC) 42 is stored in the trace memory (
TRM) is written and stored in 4G.

Data signal lines D0 to D7, memory address signal AD
R and memory read/write signals R/W are respectively connected to external microprocessors, and read/write 1-control circuit (RWC) 30 controls memory address switching circuits 31.3.
2 and memory data switching circuits 33 to 36 to select TR.
M40 and each memory (command memory (C:MD
) 37, comparison data memory (CPD) 3g, and mask data memory (MSK) 39), the contents of which can be freely read and written. When an abnormality in the serial data is detected, an interrupt signal lNTR is output.

FIG. 2 shows an example of the configuration of a line analysis and measurement device incorporating a line tracing device IO. Line tracing device [10 data lines 0° to D7, memory read/write signal R/W,
Address signal ADR is microprocessor (PU) 1
9 system bus 24. The trace start signal 5TRT is given by the input/output circuit (Ilo) 22 of the PU 19, and the 1 interrupt signal 1NTR is given by the interrupt controller (P
IC) 20, and as a result, an interrupt occurs to the PU 19. The PU 19 reads the line data stored inside the line tracing device 10 in response to one interrupt by the program written in the read/write memory (RAM) 18 and the read-only program memory (FROM) 17, and reads out the line data stored inside the line tracing device 10 at the time when an abnormality is detected. As the data before and after, CRT i'/
Evening ”:)
Display is output to the device 23. When displaying and outputting, the PU 19 can perform information processing such as data analysis and statistical processing.

In FIG. 1, CMD37. CPD38, MSK39
Each memory stores various data for detecting abnormalities in line data, and is stored in units of a predetermined number of bits, such as 8 bits or 10 bits. Using these data, a check is performed for each slot unit data of the incoming serial data.

FIG. 3 is a diagram showing the contents of each memory 37, 38, and 39, and is an example in which various data are stored corresponding to each slot. In the figure, the CPD 38 and MSK 39 have the same number of bits as the slot, and the CPD 38 has data DT1, DT2, .
DT3.0. ...but MSK39 has address ADR
This is an example in which mask data MSKI is stored in 3+1 slots.

The CMD 37 also generates data 0010.0010 that instructs how to check line data for each slot.
In this example, 0110.0001.1001, . . . are stored. This data is called a command and an example of its format is shown in FIG.

In the command format example in Figure 4, NOP, MASK
, T/, each bit of END has the following meaning.

NOP: CPD3 for line data of this slot
It is set to "1" when comparison and coincidence detection is not performed with the data of No. 8, and is set to uOu when comparison and coincidence detection is performed.

When MASK:NOP is designated as 1'0+' and comparison match detection is performed, if only a specific bit of that slot is desired to be compared and match detected, the corresponding bit of MSK39 is set to re I H, and the other bits are set to 11017.

T/F: When performing comparison match detection as described above, when there is a match, it is set as #171 when there is a match, and when there is a match, it is set as #171, and when there is no match, it is set as "true" (F (false)
When a comparison match is detected as a condition), it is set as II O) p.

END: Set to "02" when a plurality of slots are to be compared and matched, and set to "1" when this slot is the last slot to be compared and matched.

Therefore, the address ARD l+0 of CMD37 in FIG.
In the example programmed to ~3, 001O is specified in slot 1, so the line data is compared with the comparison data DT1 of CPD 38, and if they match, it is detected as "Parameters" (T condition). In slot 2, 0110 is specified. Therefore, only the specific number of bits of the line data specified by the data MSKI of MSK39 is compared with comparison data DT2 and detected according to the T (true) condition.In slot 3, 000
Since 1 is specified, the line data is comparison data DT3.
is compared and detected based on the F (false) condition, and the series of slots 1 to 3 are compared and detected as one comparison condition.

Since 1001 is specified in slot 4, no comparison and match detection is performed for this slot.

In FIG. 1, a bit counter (BTCN) 43 counts each bit of serial data, and a 5PC 42 divides the serial data frame into slot units of a constant bit length. A slot counter (SLCN) 44 is counted up for each slot, and a memory address switching circuit (A
GI) 31 via CMD37, CP D38. MS
Specify each address of K39 and read the respective data. Trace counter (TRCN) 45 is 5LCN4
4 and is counted up for each slot, the address of the TRM 40 is designated via the memory address switching circuit (AC3) 32, and the parallel-converted line data for each slot is written.

Data latch circuit (LHI, LH2, LH3) 47.4
8.49 latches each data read from the CMD 37, CPD 38, and MSK 39, and the data latch circuit (LH4) 50 latches the parallel-converted line data of the latest slot. The comparison data from the LH 248 and the mask data from the LH 349 are input to an exclusive OR circuit (exclusive off circuit FOR) 51, where an exclusive OR operation is performed and output together with a mask signal. In this case, the mask designation signal 74 from the LH 147 controls whether the mask data 69 is valid or invalid.

Bit comparison circuit (COI N) 52 has E OR51
The comparison data (including the mask signal) 70 outputted from the LH4 and the line data 67 from the LH4 are input, and a comparison and number calculation is performed. In this case, the true/false designation signal 75 from the LH 147 determines whether the comparison data 70 is to be the T condition or the F condition, and the NOP designation signal 76 determines whether or not to perform the comparison-number configuration operation. be done.

A comparison result holding circuit (CIF) 53 holds a detection signal 71 for each slot of C0IN52 and outputs a coincidence detection signal 72 in response to an end designation signal 77 from the LH 147. If at least one detection signal for each slot does not become true before the validity of the end designation signal 77 is detected, the coincidence detection signal 72 is not output.

Trace match pointer (CNPT) 46 latches the trace memory address pointer value 64 when match detect signal 72 is detected. In addition, the delay circuit (DLY) 5
5 outputs a trace stop signal 73 after a certain period of time has elapsed from the time when the coincidence detection signal 72 is detected, and stops the trace operation of the 5TAT 41.

A comparison detection interrupt circuit (INT) 54 outputs an interrupt signal 1NTR to an external processor when the match signal 72 becomes true.

FIG. 5 shows an example format of an incoming serial data input, ie, a received frame. One frame starts with frame start pattern (STRT) 9G, data section (DATA) 91 and frame end pattern (END).
)92. The trace start circuit (STAT) 41 of the line tracing device 10 receives the trace start signal 5TR from the microprocessor (PU) 19.
T, serial data input is frame start pattern 5T
If it matches RT90, the slot counter (SLCN) 4
4, and command memory (C) from slot 1.
Each data is read out from MD) 37, comparison data memory (CPD) 38, and mask data memory (MS-)@-) 39 to perform a comparison detection operation.

The frame start pattern is not particularly limited; therefore, the present device is effective not only for frames exchanged between transmission devices, but also for general serial bit patterns.

FIG. 6 is a time chart showing operation timing. The serial data DTIN is converted into parallel data every fixed number of bits by a bit counter BTCN.

The contents are stored one by one in the trace memory (TRM) 40 determined by the trace counter TRCN. When the frame start pattern 5TRT of the serial data DTIN is detected, the slot counter 5LCN is reset to zero, and thereafter increases by +1 for each slot until C, MD37, . C
Data is read by specifying each memory address of PD38 and MSK39.

The figure shows comparison data DTI, DT2, . . . DTN and command data 5TPI, 5TP2, . . . 5TPN. The data DATA of the serial data DTIN is composed of several slots, and is compared with comparison data (CPD) in accordance with the designation of command data (CMD) for each slot.

Figure 6 shows the comparison result holding circuit CCI after the end of slot 3.
This is an example in which the -number output signal 72 is output from F), and this signal causes the trace match pointer (CNPT) to hold the contents of the trace counter (TRCN) at that time, and further to change the count of the slot counter (SLCN). make it stop. Also, after a predetermined time (number of frames) has elapsed from the time of detection of this minus number output signal, the trace counter (T R
CN), but the counting stops when the frame end pattern (END) is detected. The figure shows an example in which the number of frames after the detection point is O. The slot counter initialization signal 62 indicates the timing during the trace operation.

FIG. 7 shows an example of trace data stored in the TRM 40.

The figure shows the case where a match is detected in 3 slots of the 1st frame data, and the address ADR4+m=ADR4 of TRM40.
This is an example in which data for one frame is stored at address +m+n. Therefore, the slot counter 44 and the trace pointer 46 store the address data corresponding to the address ADR40(m+2), and the trace counter 45 stores the address data corresponding to the frame END after the match detection.

In addition, the TRM40 has a circular memory system that allows for ADR
4+(m+n+1)~ADR4+K, and ADR4+O~
The stored contents up to address ADR4+(m-2) are input before a match is detected and indicate madrased data. [Effects of the Invention] By using the line tracing device of the present invention, the following various effects can be obtained.

(a) Command memory 37, comparison data memory 38,
By increasing the capacity of the mask data memory 39, data comparison of any length of serial bit input can be easily realized.

(b) By increasing the capacity of the trace data memory 40 and increasing the delay time of the delay circuit 55, it is possible to record as much data as possible before and after the occurrence of an event.

(c) The trace operation is started according to the frame start pattern, and by changing the pattern of the trace start circuit (STAT) 41, the trace operation can be performed for any frame or serial bit pattern.

(d) By setting a true/false comparison detection condition for the command programmed into the command memory 37, it is easy to detect when the command matches the comparison data and when it does not match the comparison data. This is very effective when detecting when data that should be the same as before has changed due to a problem.

(e) Since this line 1 to race device can be configured as independent hardware, the function of this line tracing device can be used by a microprocessor program to not only detect the occurrence of a malfunction event but also detect the transmission frame of a specific transmission device. It can be applied to analysis, measurement, statistics, etc. on the line, histograms of the number of times specific data in a transmission frame is sent, average transmission time, etc., maps of transmission equipment performing transmission and reception, frequency histograms, etc. .

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of an embodiment of the line tracing device of the present invention, FIG. 2 is a diagram of an embodiment of the line analysis and measurement device incorporating the above-mentioned line tracing operation, and FIG. 3 is a diagram of each memory. Diagram for explaining the contents. FIG. 4 is an example diagram showing the format of the command memory 37, FIG. 5 is a diagram showing an example of the format of serial data (DTIN), and FIG. 6 explains the operation of the line tracing device shown in FIG. 1. FIG. 7 is a timing chart showing the relationship between the line data stored in the trace data memory 40 and the slot counter 44, trace counter 45, and trace match pointer 46 when a match is detected. 10... Line tracing device 19... Microprocessor (PU) 20... Interrupt controller (PIC) 21-CRT input 9-7z
Chair (CRTI F) 22... Input/output circuit (Ilo) 23... Display device (CRT) 37... Command memory (CMD) 38... Comparison data memory (CP D) 39... Mask data Memory (MSK) 40...Trace data memory (TRM) 41...Trace start circuit (ST
AT) 42...Serial parallel conversion circuit (spc) 43...Bit counter (BTC) 44...Slot counter C3LCN) 45...Trace counter (TRCN) 46...Trace match pointer (CN P N )47-50...Latch circuit 51...Exclusive OR circuit (FOR) 52...
Comparison circuit (C, 0IN) 53... Comparison result holding circuit (CIF) 55... Delay circuit (DLY) Agent Patent attorney Noriyuki Chika Hirofumi Mitsumata Figure 2 Figure 6

Claims (2)

[Claims] (1) A transmission data viewing device that converts serial data into parallel data every predetermined number of bits and sequentially writes the data into a storage device, comprising: a trace start circuit that detects a data frame start pattern of the serial data; and a trace start circuit that detects a data frame start pattern of the serial data; A slot counter and a trace counter that count each number,
a trace data memory that is re-addressed by the trace counter and stores the parallel data; a command memory that is re-addressed by the slot counter;
a comparison data memory and a mask data memory, and the comparison data read from the comparison data memory based on the command data read from the command memory, the mask data read from the mask data memory, and the parallel data. A line tracing device comprising: a comparison circuit for comparison; and a delay circuit for stopping the counting of the trace counter after a predetermined time from the time of detection by the comparison circuit. (2) The command memory compares the comparison data and the parallel data with a bit (NOP) that determines whether or not data comparison detection is to be executed, and a bit (MASK) that determines whether or not the mask data is used. a bit (T/F) that determines whether the data match is true (true condition) or the data do not match, it is true (false condition);
The line tracing device according to claim 1, characterized in that the line tracing device is configured in a format including a bit (END) specifying the end of comparison detection.