JPS62175034A - Individual selecting calling receiver - Google Patents

Abstract

PURPOSE:To communicate securely a calling sound without giving the unpleasant feeling to a circumference by keeping the turn-off time of the discontinuous period of a calling sound at the long interval at first and shorting the time at every contact time gradually. CONSTITUTION:A decoder 4 compares the selection calling number of a self- station written in a memory part 6 beforehand with the signal from a waveform shaping circuit 3, and when they are coincident, the decoder informs that calling is executed. To an output port C of the decoder 4, the output frequency-dividing the oscillating frequency of an oscillator in the decoder 4 is outputted. When a resetting button 5 of the decoder 4 is depressed, a port D comes to be an L level until the calling is executed again. When the port D comes to be an H level, an alert control part 7 further frequency-divides, synthesizes the clock signal from the port D, mixes it with an audible frequency from an audible frequency generating circuit 9 with an analog switch 8, further amplifies it with a buffer 10 and outputs it as a calling sound from a speaker 11. The output of a circuit 18 can output the signal of the period shorter than the previous period at every time the constant time elapses.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an individual selective call receiver that controls the intermittent cycle of ringing tones.

(Prior Art) Conventionally, as shown in the waveform diagram of FIG. 1(a), the intermittent period of the ringing tone in an individual selective calling receiver is divided into a duration A that includes an audible signal and an intermittent period that does not have an audible signal. Time B is a constant time until the ringing tone ends. Therefore, in order to reliably transmit the ringing tone to the person carrying this receiver, the intermittent period of the ringing tone is shortened, but there is a drawback that it causes discomfort to people around this receiver.
Also, since it does not cause discomfort to people around you,
), if the intermittent period of the ringer is set to a sufficiently long period, there is a disadvantage that the communication to the person carrying the receiver may be delayed, or may not be communicated to the person carrying the automatic stop function. Ta.

(Object of the Invention) An object of the present invention is to eliminate the above-mentioned drawbacks, provide a ring tone that reliably transmits the ring tone to the person carrying the receiver, and furthermore does not cause discomfort to the surrounding people. All individual selective call receivers are available.

(Structure of the Invention) The individual selective calling receiver of the present invention includes a receiving section that receives an individual selective calling signal, and a plurality of receivers having different interruption times from when the receiving section receives the individual selective receiving signal until issuing a reset command. A counter that outputs a ringing tone intermittent cycle, a timer that outputs the ringing tone intermittent cycle of this counter in order of the longest interruption time every fixed time, and a switch that intermittents a ringing tone of a predetermined frequency based on the output from this timer. It is composed of a circuit.

(Example) Next, a detailed description will be given with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a block diagram of an embodiment of the present invention.
(5) is an operation waveform diagram of FIG. 2. In the figure, a radio frequency signal received by an antenna l is amplified and detected by a radio section 2 and demodulated. This demodulated signal is sent to the waveform shaping circuit 3.
is converted into a waveform that can be read by the decoder 4,
The decoder 4 compares the selective calling number of its own station, which is written in advance in the storage section 6, with the signal from the waveform shaping circuit 3, and when they match, it is notified that there is a call, as shown in FIG. As shown in a), a high (H) level output signal is output from the output port D of the decoder 4.

In the following description, the high output voltage iH level and the low output voltage are referred to as L level.

On the other hand, the output port C of the decoder 4 has an output CK1 (see Fig. 3 (C
)) is output. Reset button 5 of this decoder 4
Assume that when the button is pressed, the boat D remains at the L level until it is called again. When this boat reaches DiKH level,
The alert control unit 7 further divides and synthesizes the clock signal from the boat D, and uses the analog switch 8 to mix it with the audio frequency (FIG. 3 (P)) from the audio frequency generation circuit 9 (FIG. 3 (P)). , and is further amplified by the buffer 10 and output from the speaker 11 as a ringing tone.

Next, the alert control unit 7, which is the main part of the present invention, will be explained.

A clock signal CKz (FIG. 3(b)) is constantly input from the output port C of the decoder 4 to the clock input terminal of the counter 12. When the individual selective call receiver receives a signal matching the selective call number of its own station, the port D of the decoder 4 becomes H level, and the counter 12 of the alert control unit 7
And the reset terminal R of the timer 13 becomes H level. When these reset terminals R go to H level, the count is 12.
The divided outputs (Fig. 3 (C1 to (f)) are taken out from each terminal C1, C2, C3, and C4 of the counter 12.
A second clock signal CK2 is output from output port E of (FIG. 3(g)). On the other hand, when the clock signal CK2 is input to the timer 13 and the reset terminal R becomes H level, each output terminal T1 r T2 r T3 t T4
An output obtained by further dividing the clock CKz (Fig. 3 (k)) is output from the terminal T4.
When the level changes from the L level to the H level, the H level is maintained until the reset terminal ratio reaches the L level.

The waveform from the terminal CI of the counter 12 and the waveform from the terminal Tl11 of the tie W-13 are multiplied by an AND circuit L4, and similarly, the waveform from the terminals C2, T2 . Terminal C3, T3 and terminal C
4, each output from T4 is AND circuit 15, 16, respectively.
．． 17 and these AND circuits 14.15.16
．． Each output A1 to A4 (Fig. 3 (6 to (Q)) of 17 is O
The R circuit 18 adds the sum and outputs the result (FIG. 3(p)).

Therefore, the output of this circuit 18 can output a signal whose cycle is shorter than the previous cycle every time a certain period of time elapses.

Note that when the reset switch 5 is pressed, the output of the port D of the decoder 4 becomes L level, the counter 12 and the timer 13 are reset, and the ringing tone is stopped.

Then, the state waits for the output of the port D of the decoder 4 to become H level.

FIG. 4 is a circuit diagram showing an example of the counter 12 of FIG. 2. The inputs of the flip-flops 20 to 23 are connected to the output Q' so that the flip-flops are inverted at the falling edge of the clock input waveform, and the output Q outputs 1/2 period. This output Q is connected to the next stage 7 flip-flops, and is sequentially divided by 1/2 through shift flip-flops 20-23. The frequency-divided outputs of these flip-flops are outputted from the output Qv inverter 2 of the 7 flip-flops 20 to 23 so as to obtain the waveforms cl-c41 in FIG. 3(C) to (fl).
4 to 27, respectively. The output obtained by inverting the output Q of the flip-flop 2° by the inverter 24 is shown in Figure 3 i.
f) waveform C4. In addition, each output of the inverters 24 and 25 is multiplied by the AND circuit 28, and the result shown in FIG.
The output of the AND circuit 28 and the output of the inverter 26 are multiplied by the circuit 29 and output as the waveform C2 of FIG. 3(d).
The output of the D circuit 29 and the output of the inverter 27 are multiplied by the AND circuit 3o and outputted as the waveform shown in FIG. 3(C). Note that the output Q of the flip-flop 28 becomes the output clock CK2 of the counter 12.

Next, FIG. 5 is a circuit diagram of an example of timer I3 in FIG. 2, and FIG. 6 fa) to (kl are operating waveform diagrams in FIG. 5.

The output clock CK2 from the counter 12 is 7 clocks 7
The frequency is divided by 31. At this time, by connecting these flip 70 tabs in multiple stages, the sounding time can be increased. The output Q of this flip-flop 31 is summed with the output from the AND circuit 39 (in the JR circuit 32 (see FIG. 6).
C)) is input to the terminal CK of the flip-flop 33. Further, each output Q of the flip-flops 7'70-7'33.34 is input to the clock terminal CK of the next flip-flop 34.35.

These flip-flops 31, 33 to 35 are inverted at the falling edge of the input signal, and their input terminals and output Q are connected. In addition, each flip 70 tubes 3L
, 33 to 3.5 are reset when the reset terminals R are at L level.

The output Q (FIG. 6(d)) of the 7-lip-flop 33 is input to a multiplier circuit 40.42, and this flip-flop 33
The output Q is inverted by an inverter 36 and sent to a multiplier circuit 42.
．． 43 is input. Next, flip-flop 34
The output Q (FIG. 6(e)) is input to a multiplier circuit 40.41, and the inverted output from the inverter 37 of this flip-flop 34 is input to a multiplier circuit 42.43. The output Q (FIG. 6(f)) of the flip-flop 35 is inverted by the inverter 38 and input to the AND circuit 40.

The AND circuit 43 provides an output Tl as shown in FIG. 6(h) when the surface outputs of the inverters 3i, 37 are at H level. When the output Q of the flip-flop 33 and the output of the inverter 37 are at H level, the AND circuit 42 operates as shown in FIG.
The output T2 is obtained as shown in M), and the AND circuit 41 combines the output from the inverter 36 and the output Q from the flip-flop 34.
When both are at H level, output T3 is output as shown in Figure 6 U)
is obtained, and the AND circuit 40 obtains an output T4 as shown in FIG. 6Fk) when the output of the inverter 38 and the outputs Q of the flip-flops 33 and 34 are all at H level.

In addition, each output Q of the 7-lip frog 33 and 34 and the output of the inverter 38 are connected to an AND circuit 39, and when all of these outputs become H level, an H level is output, and the output is sent to this AND circuit 39. Connected O-circuit circuit 3
2 becomes H level. Since the flip-flops 33 to 34 are not inverted until the reset terminal hole becomes L level, the state of H level is maintained until the reset terminal hole becomes L level, as shown in waveform T4 shown in FIG. 6 (kl). When the reset terminal hole becomes L level, each output direction Tl~T
4 all return to L level.

(Effects of the Invention) As explained above, the present invention allows the interruption period of the intermittent ringing tone to be set at long intervals at the beginning, and then gradually shortened at regular intervals, thereby causing discomfort to the surroundings. The ring tone can be transmitted reliably without any noise.

[Brief explanation of drawings]

Fig. 1 fat, (bl is an intermittent waveform diagram of the ringing tone of a conventional individual selective paging receiver, Fig. 2 is a block diagram of an embodiment of the present invention, and Figs. 3 (a) to (5) are 4 is a circuit diagram of the counter 12 in FIG. 2, FIG. 5 is a circuit diagram of the timer 13 in FIG.
J~(k) is calculated using the time chart shown in FIG. In the figure, ■...Antenna, 2...Radio section, 3.
... Waveform shaping circuit, 4 ... Decoder, 5
...Reset button, 6...Storage section,
7...Alert control unit, 8...Analog switch, 9...Audio frequency generation circuit, 10
...Buffer, 11 ...Speaker, 1
2. Old...Counter, 13...Tie Otsu 14~
17.28~30°39~43...mark/AND circuit, 2
0 to 23, 31. 33 to 35... flip-flop, 24 to 27. 36 to 38... inverter, 32 old... OR circuit.

Claims (1)

[Claims] a receiving section that receives the individual selective calling signal; a counter that outputs a plurality of intermittent ringing cycles having different intermittent periods from when the receiving section receives the individual selective calling signal until issuing a reset command; An individual selective paging receiver comprising: a timer that outputs the ringing tone intermittent cycle in order of the longest intermittent period at regular intervals; and a switch circuit that intermittents the ringing tone of a predetermined frequency based on the output from the timer.