JPS62174582U - - Google Patents
Info
- Publication number
- JPS62174582U JPS62174582U JP6453886U JP6453886U JPS62174582U JP S62174582 U JPS62174582 U JP S62174582U JP 6453886 U JP6453886 U JP 6453886U JP 6453886 U JP6453886 U JP 6453886U JP S62174582 U JPS62174582 U JP S62174582U
- Authority
- JP
- Japan
- Prior art keywords
- counting
- pulse
- display means
- reset signal
- pachinko
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001186 cumulative effect Effects 0.000 claims 2
- 230000000903 blocking effect Effects 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 150000002739 metals Chemical class 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Pinball Game Machines (AREA)
Description
図面は本考案の一実施例を示すもので、第1図
は電気的構成を示すブロツク図、第2図は全体の
斜視図である。
図中、1は計数装置本体、3は玉受容器、5は
投入数表示部、6は交換個数表示部、7は余り数
表示部、8は計数器、9はリセツトスイツチ、1
0は演算表示手段、17は単安定マルチバイブレ
ータ(信号発生回路)、18はゲート手段を示す
。
The drawings show one embodiment of the present invention; FIG. 1 is a block diagram showing the electrical configuration, and FIG. 2 is a perspective view of the entire device. In the figure, 1 is the counting device body, 3 is the ball receiver, 5 is the input number display, 6 is the replacement number display, 7 is the remainder display, 8 is the counter, 9 is the reset switch, 1
0 indicates an arithmetic display means, 17 a monostable multivibrator (signal generating circuit), and 18 a gate means.
Claims (1)
した数の計数パルスをリアルタイムにて発生する
計数器と、上記計数パルスを累計してその累計値
を表示する演算表示手段と、手動操作に応じてリ
セツト信号を発生しそのリセツト信号によつて前
記演算表示手段の累計内容を初期化するリセツト
スイツチとを備えたパチンコホール用計数装置に
おいて、前記計数パルスが出力される毎にその計
数パルスの出力周期より長いパルス幅のキヤンセ
ルパルスを出力する信号発生回路と、前記リセツ
トスイツチ及び演算表示手段間に介在され前記キ
ヤンセルパルスの出力期間中は前記リセツト信号
の通過を阻止するゲート手段とを備えたことを特
徴とするパチンコホール用計数装置。 A counter that generates counting pulses in real time corresponding to the number of pachinko balls or gaming metals that have been thrown in, a calculation display means that totals up the counting pulses and displays the cumulative value, and In a counting device for a pachinko hall, which is equipped with a reset switch that generates a reset signal and initializes the cumulative content of the calculation display means by the reset signal, the output period of the counting pulse is changed every time the counting pulse is output. The present invention further includes a signal generating circuit for outputting a cancel pulse having a longer pulse width, and a gate means interposed between the reset switch and the arithmetic display means for blocking passage of the reset signal during the output period of the cancel pulse. Characteristic counting device for pachinko halls.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6453886U JPH05236Y2 (en) | 1986-04-28 | 1986-04-28 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6453886U JPH05236Y2 (en) | 1986-04-28 | 1986-04-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62174582U true JPS62174582U (en) | 1987-11-06 |
JPH05236Y2 JPH05236Y2 (en) | 1993-01-06 |
Family
ID=30900785
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6453886U Expired - Lifetime JPH05236Y2 (en) | 1986-04-28 | 1986-04-28 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05236Y2 (en) |
-
1986
- 1986-04-28 JP JP6453886U patent/JPH05236Y2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH05236Y2 (en) | 1993-01-06 |
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