JPS62172861A - Original reader - Google Patents

Abstract

PURPOSE:To attain a good picture reading corresponding to the content of a picture to be read by performing a shading correction when a few of gradation is expressed, and performing no shading correction when a multi-gradation is expressed. CONSTITUTION:A picture signal, the timing of which is arranged with a D-type FF50, is inputted to and corrected at a ROM54 in which the arithmetic result of the shading correction is stored. It is constituted so that the output signal of the FF50 can store a picture signal of one line of a main scan at a RAM52 through a gate circuit 51. A D-type FF53 uses its clear input terminal CLR as a correction possible signal, and performs the shading correction when a value is 1, corresponding to the stored content of the RAM52, and performs no shading correction when the value is zero. The correction possible signal is set at the value '1' normally. And when it is a photographing specified mode and a photographing mode, no shading is performed by writing zero on the RAM52, or no shading is performed by using the terminal CLR of the FF53, or a bypass circuit which bypasses the ROM54 is provided.

Description

[Detailed description of the invention] 〔Technical field〕 The present invention relates to a document reading device.

[Prior art]

Conventionally, this type of document reading device has been provided with a circuit for correcting shading caused by uneven sensitivity of a reading sensor, transmission characteristics of a lens, and the like. The correction method is as follows: (1) Using a slit or the like, the amount of light optically irradiated onto the light receiving element is made constant.

(2) A correction circuit is provided that calculates the output of the light receiving element in an analog manner and makes the output uniform.

(3) A/Dj digitally calculates the output of the light-receiving element, and a correction circuit is provided so that the output is uniform.

(4) Combination of (1) and (2) (5) Combination of (+) and (3) As mentioned above, five major methods have been proposed.

The (+) means has the disadvantage that it cannot correct for fine differences in shading between machines or differences in the amount of kneading caused by aging of lamps.

Means (2) allows for ideal correction, but as the frequency increases, the number of special elements in the circuit increases, the cost increases, and adjustments become complicated. It has the disadvantage of being unsuitable.

The method (3) has the disadvantage of causing a quantization error because it applies correction to the A/DL signal. (The A/D used is 6 to 8 bits.) The method in (1) is commonly used in conventional low-speed document reading devices, but the method in (2) is that the circuit is complex in the high-speed version. It's hard to hire someone because of their shortcomings.

Although the method (5) tends to be used in conventional high-speed document reading devices, it still suffers from the drawback (3).

Then, when the original is read by the method (5),
When forming an image of about two or three values, almost no problem occurs.

However, when dithering a photographic original to form an image with multiple gradations, for example, 32 or more gradations, quantization errors for shading correction have conventionally caused streaks that degrade the image.

[Mejiro]

The present invention has been made in view of the above points, and an object of the present invention is to enable good image reading depending on the image content to be read.

That is, the present invention is applicable to gradation expression and binary or3
The purpose is to always obtain high-quality images at low cost by differentiating the image signal correction operation depending on the image processing of the value level.

〔Example〕

Hereinafter, the present invention will be explained in detail based on examples.

FIG. 1 is a simplified configuration diagram of a document reading device to which the present invention is applicable.

A document placed face down on a document table 9 is illuminated with a fluorescent light 2, and an image of the document is formed on a line reading CCD 7 via a reflecting mirror 3.5 and an optical lens 6. Perform reading. The fluorescent lamp 2 and the reflecting mirror 3.5 are moved along the guide rail 8 by an optical system motor (not shown) to scan the document table 9 and perform reading in the sub-scanning direction. The CCD 7 converts the original image into an electrical signal. In this example, uneven light emission of the fluorescent lamp 2, reflection mirror 3.5
The so-called shading caused by uneven density due to dirt, etc., uneven luminous intensity distribution of the optical lens 7, uneven sensitivity of the CCD image sensor, etc. is removed. In this embodiment, a standard white plate l serving as a reference is read prior to the above scanning,
After that, it is scanned and based on the reading signal of the standard white plate,
It performs image signal correction. The standard white board 1 is a board for measuring the above-mentioned image signal, and the entire surface is, for example, white (uniformly painted).

FIG. 2 is a diagram showing an example of the circuit configuration of a document reading device for performing image signal correction according to the present invention.

The document is illuminated by a fluorescent light 15, and the reflected light forms an image of the document on a CCD 7'' through an optical lens 6. C
The CD 7 converts the original image into an electrical signal, and outputs main scanning line data as an analog electrical signal in accordance with the main scanning synchronization signal.

The amplifier circuit 10 amplifies this signal and converts it into an A/D converter I.
After the signal is converted into a digital signal by I, and the shading is corrected by the shading correction circuit 12, it is connected to an external circuit as a digital image signal output.

The external circuit is, for example, a binary signal conversion circuit such as a binarization circuit or a dither processing circuit. The binary signal is, for example, LI3
1', it is used by being connected to equipment such as image electronic files and electronic transmission equipment.

In FIG. 2, a control circuit 21 is a control circuit for controlling the temperature and dimming of the shading correction circuit 12 and the fluorescent lamp 15, and operates upon receiving instructions from the main body control circuit 24.

An operation section 24 is connected to the main body control circuit 23, and issues instructions to start reading the document and displays the status of the apparatus.

The dimming circuit 18 is a control circuit for controlling the light 1 of the fluorescent lamp 15, and performs dimming by controlling the lighting time by pulse width modulation according to instructions from the control circuit 21.

The thermistor 13 is a temperature sensor for measuring the tube wall temperature of the fluorescent lamp 15. The 411 constant output of the thermistor 13 is A/D converted by the A/D converter 22 and sent to the control circuit 2.
1, and the input data controls the heat retention heater 14 and cooling fan motor 16 via the temperature control circuit 19 and driver circuit 20 to adjust the tube wall temperature of the fluorescent lamp 15 to the most fluorescent temperature of around 40 degrees Celsius. Lights are controlled so that they emit light efficiently and stably.

Specifically, the thermistor 13 measures the tube wall temperature of the fluorescent lamp 15, and when the measured temperature is 40°C or less, the heater 1 is turned off.
4 is turned on, the fan motor 16 is turned off, and when the temperature exceeds 40°C, the heater l=1 is turned off and the fan motor 16 is turned on to control the temperature. In reality, the fluorescent lamp itself generates heat due to its own light emission, so it is necessary to take measures such as giving hysterinous characteristics to the above-mentioned on/off temperature settings.

FIG. 3 shows the shading correction circuit 12 and the control circuit 21.
FIG. 2 is a more detailed configuration diagram of FIG.

The image signal output from the A/D converter 11 is timed by a D-type flip-flop 50,
The result of the shading correction calculation is input to the ROM 54 and corrected. D type flip flop 5
The output signal of 0 allows image signals for 1 main scanning lines, that is, CCDI lines, to be stored in the RAM 52 via the gate circuit 51 as necessary.

The RAM 52 stores an image read from the standard white plate I, and by giving this to the address signal line of the readout ROM 54 in synchronization with the actual original read image, the shading correction stored in the ROM 54 can be read. By reading out the calculation results, 411 calculations are performed to remove shading caused by uneven light emission of the fluorescent lamp 2, uneven agricultural power due to dirt on the reflecting mirror 3.5, uneven luminous intensity distribution of the optical lens 7, and the like.

The D type flip-flop 53 is a circuit for adjusting the timing of the image signals read out from RA~152.

The selector 57 is a switching circuit for switching between the address signal output from the CPU 60 and the count signal (-horizontal address signal) of the counter 58 that counts the CLOCK signal when reading the pixel signal from the CCD 7. That is, when writing the image signal data of the standard white board 1 to the RAM 52 and when reading it out and performing shading correction, it is switched to the horizontal address signal of the counter 58, and when the content of the RAM 52 is directly read by the CPU 60, it is switched to the horizontal address signal of the CI'U 60. Switch to output address signal and use.

The counter 58 is initialized by a synchronizing signal H3YNC signal indicating the start of reading one line of main scanning, and repeats the counting operation for each line.

The counter 59 is a counter that counts this H3YNC signal, and is used, for example, when changing the pattern in the sub-scanning direction when performing dither processing.

The timing control circuit 66 receives a command from the CPU 60 and selects the selector 57. Gate circuit 51. This circuit controls the bidirectional bus driver 56 rfrl+.

The timing control circuit 66 controls the following three types of operation modes.

(1) Shading data sampling mode This is an operation mode in which an image signal read from the standard white board 1 is stored in the RAM 52. The gate circuit 51 is
The image signal is written into the RAM 52 by operating the main scanning section for 1942 minutes indicated by the YNC signal and switching the selector 57 to the address signal of the counter 58.

(2) Shading correction mode This is an operation mode in which the image signal input to the D-type flip-flop 50 is corrected based on the image signal written in the RAM 52. At this time, the selector 57 is operated by the address signal of the counter 58, and the RAM 52
From then on, the data written in the above shading data sampling mode is read out sequentially, and the data written in the D type
Take the timing with flip-flop 53, and ROM5
Perform shading correction in Step 4. The gate circuit 51 does not operate at this time.

(3) CPU mode This is an operation mode in which the CPU 60 can directly read and write the contents of the RAM 52. At this time, the bidirectional bus driver 56 is activated, is directly connected to the data bus of the CPU 60, and is used to read the contents of the RAM 52 and perform arithmetic processing, or conversely to change the contents. At this time selector 5
7 is switched to the address 1 word line of the CPU 60, and the gate circuit 51 does not operate.

Now, in the circuit described above, the CPU 60 reads the working RAM 62 according to the control program stored in the ROM 61.
,! 10 ports 63, serial circuit 64, display circuit 65
control using.

The timer 67 is a circuit that provides pulses to the CPU 60 at regular time intervals. The CPU 60 manages time by using this pulse signal as an interrupt signal.

Next, the principle of dimming will be explained using FIG. 11.

In FIG. 1, the horizontal axis indicates an interval of 1 frame, and the vertical axis indicates the gray level of the image signal. In this embodiment, this corresponds to the data read from the standard white board l and stored in the RAM 52 in the shading data sampling mode described above.

In this embodiment, the data stored in the RAM 52 has six hints, with the value 63 being the blackest level and the value 0 being the whitest level.

Now, in FIG. 4, curve a is light 1 of fluorescent light 15.
Curve C indicates a state where the amount of light is insufficient, curve C indicates a state where the amount of light is appropriate, and curve C indicates a state where the amount of light is too large. Since the shading correction method in this embodiment performs correction based on the data read from the standard white plate 1, when the reading is saturated as shown by curve C, correction cannot be performed.

Furthermore, if the amount of light is insufficient as shown by curve a, the amount of correction by calculation increases, resulting in a disadvantage that the S/N ratio of the read image signal deteriorates. Therefore, the amount of light from the fluorescent light 15 is curved, and the whitest point X of the read data is exactly
It is necessary to control the value to be 0.

FIG. 5 shows RAM 5 when the fluorescent light 15 deteriorates after dimming the fluorescent light 15 using the standard white board l.
2 shows an example of stored data.

Curve d shows a state in which the fluorescent lamp 15 has deteriorated so much that even when it is fully lit, the black level remains by a value l and the dimming is insufficient.

Curve e shows a state where both ends of the fluorescent lamp 15 have progressed to blackening and the amount of light at the end of the tube has decreased.

Let the curve `` be normal data, and let the density levels at both ends of the valid section in l frame be the values n and , respectively.Similarly, let the density levels at both ends of the valid section of the curve e be the value m1 and the value j.

As described above, in the shading correction in this embodiment, when the read value of the standard white plate 1 is dark as shown by the curve a in FIG. 4, the S/N deteriorates. Therefore, in order to prevent this, it is possible to define the limit of darkness as a predetermined value α, and compare this with the density level of the above-mentioned effective section to know the deterioration of the fluorescent lamp 15.

The example shown in FIG. 5 shows a state where m>α>n and j>α>k. Of course, in determining the above deterioration, for example,
It goes without saying that it may be determined that the fluorescent lamp 15 has deteriorated even when only one end exceeds the value α, such as m>α and j<α.

Next, the control procedure will be explained using the flowcharts shown in FIGS. 6 to 12.

FIG. 6 is a flowchart showing the main control procedure of the main body control circuit 23.

First, when the power is turned on, the operating section 24 and each drive circuit are initialized in step SPI, and a polling operation is started to start reading.

In step SP2, it is determined whether or not the reading start switch on the operation section 24 has been pressed, and a branch is made.

In the case of starting reading, proceed to step S'P3 and change the reading position of the optical system to the position of the standard white plate l (=
After confirming that the home position is reached, proceed to step SI'4. In step SP4, fluorescent light 1
It is determined whether the temperature adjustment control for maintaining the tube wall temperature of No. 5 at a predetermined temperature has been completed, and if not, stable image reading cannot be guaranteed, so the start of document reading is prevented. If the temperature control has been completed, the process advances to step SP5.

In step SP5, abnormal pixels are detected with the fluorescent light 15 turned off, and in step SP6, the fluorescent light 15 is turned off.
is turned on, and the dimming control of the fluorescent light 15 is performed in step SP7.

In step SP8, it is determined whether there is an error in the dimming control, and if there is an error, an error is displayed and reading of the document is prevented.

If there is no error in the dimming control, the process proceeds to step SP9, where an abnormal pixel is detected with the fluorescent light 15 turned on, and the process proceeds to step 5P18. Note that if the number of abnormal pixels is too large, an error is displayed and the reading operation is prohibited.

In step 5P18, it is determined whether the photo special mode is selected. Whether it is a photo special mote or not will be determined by the service personnel etc.
This is predetermined by a special operation on the operation unit or a hidden switch. If the photo special mode is selected, the process advances to step 5P19, where it is determined whether the photo mode is selected.

In the case of photo mode, the process advances to step 5P20. In step 5P20, in order to not perform shading correction, all "0" is stored in the shading correction RAM 52.
" is written. Also, if the photo special mode is not set or if the photo mode is not set, proceed to step 5 PIO.

By the way, the photo mode is a mode in which gradation is expressed using a dithering method, and the photo special mode is a mode that prohibits execution of a shading correction operation in the photo mode.

In step 5 PIO, the value read from the standard white plate 1 is stored in the RAM 52.

In step 5PII, the abnormal pixels detected in steps SP5 and 9 are corrected, and then in step 5P
At step 12, reading and scanning of the original is started.

In step Sr'13, it is determined whether the required number of document reading scans have been completed, and if not, step Sr'13 is performed.
Return to P7 and repeat the operation described above.

On the other hand, when the required number of original reading scans have been completed, the fluorescent light 15 is turned off, the original reading is completed, and a new reading start switch is activated.

7 and 8 are flowcharts showing the control procedure of the CPU 60 of the control circuit 21. FIG.

In FIG. 7, after turning on the power, in step 5P50, the flag, I10 port 63, serial circuit 64, display circuit 6
After performing the initialization such as 5, the process proceeds to step 5P51.

In step 5P51, it is determined whether or not there is an operation command input from the main body control circuit 23, and if not, the display circuit 65 displays the status of light control, temperature control, etc. If there is a command input, the process proceeds to step 5P52, and branches to each step depending on the content of the command to perform processing. The details of each process are as follows.

・Step 5P53 Turn on the fluorescent light 15, set the flag FLON to 1, and similarly,
Set the flag ERRCNT to 0. The flags, counters, and data used in explaining the flowchart are stored in the RAM 62 and the CPU.
62 refers to data that is read and written for processing.

・Step 5P54 The fluorescent light 15 is turned off and the flag FLON is set to 0.

・Step 5P55 Performs dimming control.

・Step 5P56 The detected error information is transferred to the main body control circuit 23.

・Step 5P57 Abnormal pixels in one frame are detected.

-Step 5P58 Correction processing for the abnormal pixel detected in step 5P57 is performed.

- Step 5P59 The image signal read from the standard white board 1 is stored in the RAM 52 after noise removal, or data "0" in the case where shading correction is not performed is stored in the RAM 52.

- Step SP60 The data stored in the RAM 52 is transferred to the external circuit via the serial circuit 64.

After completing the above processing steps, the process returns to step SPI and repeats the control procedure described above.

FIG. 8 shows a timer process executed at regular time intervals using a pulse signal given by the timer 67. This process is performed after initialization in step 5P50 is performed.
Execution begins.

In step 5P61, a process is performed to control the tube wall temperature of the fluorescent lamp 15 to around 40° C. at which stable light emission is possible.

Next, the procedure for controlling the dimming of the fluorescent lamp 15 will be explained using FIG.

In step 5P150, flags, data, and counters are initialized prior to control. Data FLD
A and TA are dimming data given to the dimming circuit 18; a value of 255 means full lighting, and a value of O means lights out. Data O
F F S E T is a value to be added to or subtracted from data FLDATA. The counter FLCNT is a counter for counting the number of times for repeat control. Counter FLE
RR is a counter for measuring the lighting start-up state of the fluorescent light 15, and counts the number of times when the data read for dimming control is extremely dark.

Note that the image signal handled in this embodiment is 6 bits (directly 0 to 63), and since the RAM 52 uses 8 bits, the upper 2 bits are used for purposes other than storing the image signal. There is.

In step 5P151, the process waits for a period of time until the previously output dimming data changes in the amount of light from the fluorescent lamp 15, and then proceeds to the next step.

In step SP+52, the image signal read from the standard white plate 1 is stored in the RAM 52 in the shading data sampling mode.

In step 5P153, four consecutive pixels of the image signal data stored in the RAM 152 are added as an l block, and the block with the smallest numerical value (the brightest) is detected (=L block, added value S).

In step 5P154, the data 0FFSET is halved, and in step 5P155, the data 0FFSET is
When the value becomes less than 1, a process is performed to set the value to 1. By doing this, the value of data 0FFSET becomes 64.32.16.8.4.2 by repeating the control.
, l, 1. It changes like...

In step 5P156, branching is performed depending on the value of the addition value S.

In step 5P157, since the addition value S is 0, that is, the amount of light is considered to be too large and saturated, the data FL is
The data 0FFSET is subtracted from DATA to control the amount of light to be reduced.

In step 5P158, it is determined whether the data FLDATA has become a negative value, and if it is negative, step 5P1
In step 59, the data FLDATA is set to the value 0, and processing is performed as a dimming error 1.

The dimming error 1 is treated as an error because it is a logically impossible state in which a white level signal is read even though the data given to the dimming circuit 18 indicates that the light is off. In this case, it is possible to consider that a defect has occurred in the dimming circuit 18, the amplifier circuit 10, etc.

On the other hand, if the added value S is not 0, step 5P16
0, it is determined whether the added value S is dark data of 240 or more, and if the value is 240 or more, it is assumed that the fluorescent light 15 is not lit and the counter FLERR is incremented by 1.

In step 5P161, since it is considered that the amount of light is insufficient, control is performed to increase the amount of light by adding data 0FFSET to the data FLDATA.

In step 5P162, data FLDATA is 255
If the value exceeds 255, set the data FLDATA to the value 255. Here, the reason why an error is not made as an insufficient amount of light is that when a fluorescent light is turned on, the amount of light gradually increases from the start of lighting.

At step SP+63, the data FLDATA calculated at the step described above is output to the dimming circuit 18, and the counter FLCNT is incremented by l.

In step 5P164, the dimming control is ended when the counter FLCNT reaches 50, and in step 5P167 it is determined whether the counter FLERR exceeds the value 25. If it exceeds the value, the fluorescent light 15 does not turn on easily or does not turn on at all. It is assumed that the light is not lit and is treated as a dimming error.

At step 5P165, the counters FI and CNT are 25.
It is determined whether or not the
At step 66, it is determined whether or not the counter FLERR exceeds the value 15. If it exceeds the value 15, it is assumed that the fluorescent light 15 is not being turned on easily and the steps 5P151 to 5P1 are continued until the counter FLCNT reaches the value 50.
62 is repeated. After performing the control 25 times or 50 times, the process advances to step 5P168.

In step 5P168, the average value of the effective pixels at both ends described in FIG. 5 is calculated in order to remove noise. (
Average value A) In step SI' 169, the difference between the 1 pixel average value obtained by dividing the addition value S by @4 and the above average value A is calculated, and the difference is the value 15.
If it exceeds the threshold, it is assumed that the end portion of the fluorescent lamp 15 has deteriorated, and processing for dimming error 3 is performed.

The processes of steps 5P169 and 5P169 are performed individually at both ends of the effective pixel.

In step 5P170, it is determined whether the added value S is controlled to be around 0 by checking whether the added value S is less than the value 8.

If the added value S is equal to or greater than 8, processing for dimming error 4 is performed, assuming that the deterioration of the fluorescent lamp 15 has progressed throughout the tube and the amount of light is insufficient.

According to the dimming control described above, it becomes possible to easily detect abnormalities during dimming, and the data 0FFSE
By making the value of T variable, convergence of control is prevented, and when the rise characteristics at the time of lighting are not good, the control time is lengthened, thereby making it possible to perform stable dimming control.

Next, using FIG. 10, the control procedure for shading processing when the mode is not special photo mode or when the mode is not photo mode will be explained.

In step 5P200, the counter CNT is set to 0, and
All the shading buffer portions of the RAM 62 are set to the value O.

In step Sl''201, the image signal read from the standard white board l is stored in the RAM 52 in the shading data sampling mode, and is added to the contents of the previous shading buffer for each corresponding pixel. to be memorized.

In step 5P203, the counter CNT is incremented by 1, and steps 5P201 to 5P203 are repeated until the value reaches 4.

In step 5P204, the contents of the shading buffer are divided by the value 4 to obtain an average value, which is then stored in the RAM 52 (RAM for shading correction), and the shading process ends.

According to the shading process described above, the RAM 52,
By simply processing the data in the RAM 62 with the CPU 60, both signals read from the standard white board 1 are averaged and noise is removed.This can be achieved at a very low cost without using any special adders or dividers. There is. Moreover, a more advanced noise removal method using a devised algorithm can be easily applied by simply changing the control program stored in the ROM 61.

Next, the control procedure for abnormal pixel detection will be explained using FIG. 11.

Steps 5P250 to 5P253 are steps 5P200 to 5P203 of shading processing.
This is a processing step corresponding to step Sr'254.
When you proceed to , the shading buffer has RAM5
The added value of the image data stored in 2 is similarly stored.

The difference from shading processing is that the data stored in the RAM 52 is processed not only for data after dimming but also for data when the fluorescent light 15 is turned off.

In step 5P254, the contents of the shading buffer are divided to obtain an average value.

In step 5P254, the average value AV of all pixels in the effective image section is determined, and then the process proceeds to step 5P255.

In step 5P255, the counter CNT is set to 0,
The following steps 5P257 to 5P261 are used to confirm that the count value has reached the effective pixel number E at step 5P26.
Repeat until it is determined by 1.

In step S I) 257, the value of the shading buffer specified by the contents of counter CNT (for example,
When the stored content of the counter CNT is 100, the difference Z between the 100th data from the beginning of the shading buffer) and the average value AV is calculated.

In step 5P258, the absolute value of the difference Z is compared with a predetermined value C, and if it exceeds the value C, the error is large, so it is determined that the pixel is abnormal, and the process proceeds to step 5P259.

In step Sr'259, the value is 0 in step Sr'53.
The value of the counter CNT is stored in the area of the buffer for storing abnormal pixels (part of the RAM 62) indicated by the contents of the counter ERRCNT, and is accumulated as the address of the abnormal pixel.

In step 5P260, the contents of the counter ERRCNT are incremented by one.

According to the abnormal pixel detection described above, detection is performed when the fluorescent light 15 is off and when the fluorescent light 15 is turned on and dimmed, so if the difference between the abnormal pixel and the normal pixel happens to be small, the detection This prevents leakage and makes it possible to obtain cumulative results from two detections.

FIG. 12 is a diagram showing a control procedure for abnormal pixel correction in which an abnormal pixel detected by abnormal pixel detection is replaced with the immediately preceding normal pixel.

Step 5P300 is a processing step that ends the process when the content of the counter ERRCNT reaches the value 0.

If the value is not 0, step 5P301 to step 5
Execute the process of P303 once.

In step 5P301, the contents (=ADR) of the address indicated by the contents of the counter ERRCNT are read from the beginning of the buffer for storing abnormal pixels.

In step 5P302, RA for shading correction
MS of data corresponding to ADR address from the beginning of M52
Set B to the value 1.

In this embodiment, when the MSB of the RAM 52 is set to the value 1, an operation is performed in which an abnormal pixel is replaced with the previous normal pixel. Also, in step 5P302, A
Although the MSB of the DR address is set to the value 1, the timing may be shifted depending on the circuit configuration, so the MSB of data before and after the ADR address may be manipulated.

Next, FIG. 13 will be explained.

FIG. 13 is a diagram describing the areas surrounding the RAM 52 and ROM 54 in more detail.

The D type flip-flop 50 is, for example, a TTL
It is a 6-bit D type flip-flop like 74LS174, and has a clock input terminal CK and a clear input terminal CLR in addition to a data input terminal and a data output terminal. When the clear input terminal is set to the value 0, the data output terminal becomes the value 0, and the clock input terminal CK is set to -
Holds the signal connected to the data input terminal when the low clock is input.

Therefore, if the data input terminal of the D type flip-flop 50 is pulled up and the signal input to the data input terminal is disconnected, all bits will be 01 or a pseudo It becomes possible to generate a unique image signal pattern. Additionally, if the signal input to the clock input terminal is made so that a rising signal does not occur at an abnormal pixel, the data output terminal will continue to output the normal pixel held by the previous clock, which can be used to correct the abnormal pixel. It is.

AND gate 71 and inverter 72 correct abnormal pixels;
AND gate 70 and inverter 77 are logic circuits for pattern generation.

In addition, in this embodiment, the 6th bit of 152 to R48 (LSB is the 0th bit, the 0th to 5th bits are assigned to image signal storage, and the 7th bit, MSB, is assigned for abnormal pixel detection. CPU6
A similar effect can be obtained by writing an arbitrary 1,0 pattern to 0. In this case, when the value 1 is written in the 6th bit of 1 to 152 to I, all the data output terminals of the D-type frinzo flop 50 become (directly 0).

Based on the same, when the value l is written to the MSB of the RAM 52, the CLOCK signal is gated by the ant gate 71, and the abnormal pixel correction described above is performed without holding the data of the corresponding pixel.

In FIG. 13, D type flip-flop 5
Although the abnormal pixel correction and pattern generation are performed in the D-type flip-flop 55 in the subsequent stage, the abnormal pixel correction and pattern generation can be performed in the D-type flip-flop 50 and the D-type flip-flop 55. It goes without saying that it may be separated as in pattern generation.

The gate circuit 51 uses, for example, a TTL74LS244, a tri-state buffer, etc., controls the gate control signal by a timing control circuit 66, and writes the image signal to the RAM 52 when the gate control signal is set to 0. At this time, by connecting the MSB and 6th bit of the input signal to GND, the RA
A value 0 is written to both bits of M52.

The D type flip-flop 53 is, for example, a TTL
74LS273 is used. The clear input terminal CLR is used as a correction enable signal (heavily used; when @l, shading correction is performed according to the stored contents of the RAM 52, and when the value is O, all outputs become 0, so shading correction is not performed.

The correctable signal may be normally set to (i?r 1) using a dip switch, and set to 0 when confirming whether the shading operation is being performed normally.

In addition, in the case of photo mode in photo special mode, as mentioned above, there is a means to write "0" to the RAM 52 and do not perform shading correction, and the above-mentioned D type flip.
Possible means include using the clear terminal of the flop 53 and not performing noeding correction, or providing a circuit that bypasses the shading correction ROM 54.

〔effect〕

As described above, according to this embodiment, shading correction is performed when there are few gradation expressions, that is, in the case of a character image, and when multiple gradations are expressed, shading correction is not performed. , it is possible to prevent bit error streaks and obtain beautiful photographic images.

[Brief explanation of drawings]

FIG. 1 is a simplified configuration diagram of a document reading device to which the present invention can be applied, and FIG. 2 is a diagram showing the configuration of a specific electric circuit for performing shading correction according to the present invention.
'4 composition diagram, 31:g+ is a configuration diagram that describes Figure 2 in more detail, Figure 1 is an explanatory diagram to explain the principle of dimming control, and Figure 5 is a diagram showing the inferiority of fluorescence +ffts. An explanatory diagram for explaining the principle of summation, Fig. 6 is a flowchart of main control, Fig. 7 is a flowchart of sub-control, Fig. 8 is a flowchart of timer processing, and Fig. 9 is a flowchart of dimming control. Figure 1O is a flowchart of the aging process, Figure 11 is a flowchart of abnormal pixel detection, Figure 12 is a flowchart of abnormal pixel correction,
Figure 3 is a detailed block diagram of shading correction.
2 is a standard white plate, 2 is a fluorescent lamp, 7 is a COD, and 12 is an aging correction circuit.

Claims (1)

[Claims] It has an image sensor and a means for correcting the image read signal using a reference signal obtained by reading a reference surface by the image sensor, and selects whether or not to correct the image read signal by the correction means depending on the image mode. A document reading device characterized by: