JPS62172820A - Automatic control system for signal level - Google Patents

Abstract

PURPOSE:To obtain the automatic level control system of a signal, which is suitable for a high vision transmission system, etc., by detecting the level of a test signal contained in a prescribed time base area, and feeding it back as the reference level signal of an A/D converter of an input side. CONSTITUTION:A testing signal VIT multiplexed in the vertical flyback time of a high vision signal (a multiple sub-sample transmission signal containing no turn-back component between frames in a low band part) has a flat part of about a 50 clock portion after a monopulse (a transmission clock of 16MHz is used). This level (when it is considered by quantization of 9 bits) becomes + or -112. Accordingly, by detecting this level, and operating an up/down counter 10 by a ROM 4, an automatic level control ALC is applied. A time constant of the ALC depends on a bit length of a counter 10, but about several seconds - scores of seconds are desirable.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic signal level control system for a system that converts an analog input signal into a digital signal and outputs the digital signal.

The present invention relates to an automatic signal level control system suitable for configuring a decoder for a high-definition receiver that is compatible with a multiple subsample transmission system, for example.

[Prior Art] A conventionally known ALC (automatic level control) method detects the signal level, smoothes it, and returns it to the reference level of the A/D converter to perform automatic control. There is.

[Problems to be Solved by the Invention] As a high-definition transmission system, a multiple subsample transmission system using offset subsampling between frames and between fields, such as MUSE (Multiple
5ub-Nyquist Sampling Enc
A high-definition television signal sub-sampling transmission system called ODING is known. This multiplex subsample transmission method consists of a first method that has been known in the past (see Institute of Electronics and Communication Engineers technical report IE84-72), and a second method that is not yet publicly known (a patent application filed by the applicant in 1999). 60-
106132)).

The above-mentioned second multiplexing and sub-sampling transmission method is a transmission method that does not include aliasing components between frames in the low frequency part of the encoded transmission signal, and for FM transmission systems, non-linear emphasis is used. is used. It is also possible to baseband multiplex audio.

In any of these cases, if the signal level changes from a specified value, this may lead to deterioration in image quality and sound quality.

Additionally, in general, FM demodulators are highly stable from a level perspective, so it is okay to configure the system by relying on the level stability of the device, but when considering overall economic efficiency, etc. It is better to apply ALC within this range.

[Object] Therefore, an object of the present invention is to provide an automatic level control system for signals that is compatible with high-definition transmission systems and other transmission systems.

[Means for solving the problem] In the present invention, in a system that converts an analog input signal into a digital signal and outputs it, the level of a test signal included in a predetermined time domain is detected, the levels are averaged, and the The average level is fed back as a reference level signal to the input side A/D converter.

In a preferred embodiment of the present invention, the VIT signal (a test signal multiplexed during the vertical blanking period) is included in the first half of the frame pulse;
Vertcal Interval Te5t si
gnal), a signal whose level is known is superimposed, the level is detected, and is fed back to the reference level input terminal of the human-powered A/D converter. Here, the loop time constant of the ALC is set to be sufficiently longer than the clamp time constant of the receiver input, and the DC deviation caused by the ALC operation is absorbed by the clamp circuit.

[Example] Hereinafter, the present invention will be described in detail based on examples.

FIG. 1 is a block diagram showing one embodiment of the present invention. In this figure, 2 is an A/D (analog/digital) converter, 4 is a ROM (read only memory), 6 and 8 are AND gates, 1° is an up/down counter, and 12 is a D/A It is a converter.

FIG. 2 is a timing chart for explaining the operation of the embodiment shown in FIG. 1, and shows the relationship between the VIT signal included in the high-definition signal and the gate signal supplied to the AND gate 6.8. ing. Also, Figure 3 shows RO
It is a memory configuration diagram of M4.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 to 3.

As shown in Figure 2, the VIT signal multiplexed during the vertical line period of a high-definition signal (a multiplex sub-sampled transmission signal that does not include aliasing components between frames in the low frequency range) is 50 clocks after the monopulse. There is a flat part (18M) using IZ transmission lock), and this level is ±112 (considering 9-bit quantization).

Therefore, this level is detected, and the up/down counter IO is operated by the ROM in the operating state shown in FIG. 3, thereby multiplying the ALC.

What is important here is that with such a configuration, simply changing the clamp level does not affect the ALC operation. In other words, it is operating at a normal level,
If only the DC amount deviates, up-counting and down-counting are performed in the opposite manner on the first and second lines of the frame pulse.

This is a feature of the combination of the VIT signal configuration and this method.

Note that the monopulse included in the VIT signal is inserted for a purpose completely independent of this method (for equalizing the amplitude/phase of the transmission line), and the gap between the monopulse and the frame pulse must be flat. be.

The time constant of ALC depends on the bit length of the up/down counter IO, but is preferably about several seconds to several tens of seconds.

Furthermore, since the present embodiment shown in FIG.
and the clamp operation may interfere, causing the ALC to vary the clamp level. However, since the opposite case is impossible as described above, there is no particular problem such as oscillation.

Normally, by adopting the configuration shown in Figure 4, A
The reference level is controlled by setting the time constant on the LC side to be sufficiently longer than the clamp time constant. As a result, the clamp circuit 16 absorbs the deviation of the DC component due to ALC. In FIG. 4, 14 is an A/D converter;
8 is an operational amplifier, RH is the reference upper end level, RL
indicates the reference lower end level.

However, if interference with the clamp level is to be avoided, a configuration as shown in FIG. 5 may be used. In this figure, 14,
18 and 18 are the same as the A/D converter, clamp circuit, and operational amplifier shown in FIG. 4, respectively. Therefore, the difference between FIG. 5 and FIG. 4 is that the feedback signal from the D/A converter is passed through the level inverter 22 and the operational amplifier 20 to the reference upper end level RH.

Note that although the embodiments described so far have been explained using a signal based on a multiple subsample transmission method as an input signal, it is of course applicable to other transmission systems.

[Effects of the Invention] By implementing the present invention, it is possible not only to significantly improve the stability of the required signal level, but also to configure various signal processing devices at low cost.

[Brief explanation of drawings]

Fig. 1 is a block configuration diagram showing a basic embodiment to which the present invention is applied, Fig. 2 is a waveform diagram showing the relationship between the VIT signal and the gate signal, and Fig. 3 is a memory map diagram showing the operating state of the control 110M. , FIG. 4 is a block diagram showing a second embodiment equipped with a feedback loop, and FIG. 5 is a block diagram showing a third embodiment that eliminates interference with the clamp level. 2...A/D converter, 4...-ROM. 6.8...AND gate, lO...up/down counter, 12...D/A converter, 14...A/D converter, 16...clamp circuit. Patent Applicant Japan Broadcasting Corporation Representative Patent Attorney Yoshi Tani - Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Procedural Amendment Statement April 25, 1985

Claims (1)

[Claims] 1) In a system that converts an analog input signal into a digital signal and outputs it, the level of a test signal included in a predetermined time domain is detected, the levels are averaged, and the average level is input. Side A/D
An automatic signal level control method characterized in that the signal is fed back as a reference level signal to a converter. 2) high level and low level of the test signal;
The system determines whether the absolute value of the difference with the clamp level (the center level of the entire dynamic period) is larger or smaller than the reference value, integrates the result, obtains a DC value, and feeds this back. An automatic signal level control system according to claim 1, characterized in that: 3) The signal level according to claim 1, characterized in that the interference of the clamp level is removed by controlling the reference upper end level and lower end level of the A/D converter using a feedback signal. Automatic control method.