JPS6217271B2 - - Google Patents

Description

[Detailed description of the invention]

<Industrial Application Field> The present invention relates to a coin accepting device for a vending machine, and particularly to control of a coin sorting electromagnetic device that sorts genuine coins and counterfeit coins. <Conventional technology> Conventionally, the coin accepting device of a vending machine inspects the authenticity of the inserted coin, operates a coin sorting electromagnetic device based on the inspection output, guides genuine coins to a genuine coin passage, and removes counterfeit coins. The cargo is configured to be guided to a return path. The sorting of genuine coins and counterfeit coins in the coin sorting electromagnetic device is performed by energizing the receiving solenoid. That is, if the inserted coin is a genuine coin, the receiving solenoid of the coin sorting electromagnetic device is energized, thereby guiding the inserted coin to the genuine coin passage, and if the inserted coin is a counterfeit coin, the receiving solenoid of the coin sorting electromagnetic device is energized. The acceptance solenoid is not energized, which directs the input coin to the return path. By the way, this operation of the receiving solenoid is performed for each coin that is inserted, so if, for example, genuine coins are sequentially inserted at a predetermined interval, the receiving solenoid must be energized and de-energized frequently. Repeatedly, this causes unnecessary wear and tear on the mechanism operated by the receiving solenoid, and also causes a lag in timing between coin acceptance and energization of the receiving solenoid. <Problems to be Solved by the Invention> The present invention has been made in view of the above-mentioned points. A timer with an appropriate operating time is provided, and when a coin is accepted, this timer is set, and during this timer operating time, the timer is set. configured to energize the receiving solenoid;
If it is determined that the next coin inserted during this timer operating time is a genuine coin (that is, if a genuine coin is subsequently inserted), the timer is reset, effectively extending the timer operating time, and accepting the coin. To provide a coin accepting device for a vending machine in which a solenoid is continuously energized. <Means for solving the problem> A coin detection section including a plurality of coin detectors that individually detect various coin properties along a coin path, and a determination of the detection output of each coin detector. A determination circuit that integrates the respective determination results and determines whether the coin is genuine or counterfeit; and a determination circuit that is located in the passage behind the coin detection section and is energized only when the determination circuit sends out a genuine coin determination output, and detects the coin in the counterfeit passage. a coin sorting electromagnetic device that closes the coin sorting device and guides the specie coins to the specie passage; and a coin sorting electromagnetic device that starts operating in synchronization with the start of operation of the coin sorting electromagnetic device to ensure that the specie coins are guided to the specie passage. a timer circuit that has an operating time corresponding to the required time and that releases the operation of the coin sorting electromagnetic device at the end of the operating time; and a timer circuit that determines that the next input coin is a genuine coin during the operating time of the timer circuit. The electromagnetic device is characterized in that it further comprises a timer control circuit that resets the operating time of the timer circuit, and the electromagnetic device continues to operate when genuine coins are continuously inserted at intervals greater than a predetermined interval. <Operation> Therefore, according to the present invention, if all the coins sequentially inserted are genuine coins, the receiving solenoid continues to be energized, the genuine coin receiving passage continues to open, and coins are accepted one after another. <Example> Hereinafter, a coin accepting device for a vending machine according to the present invention will be described in detail with reference to an example shown in the accompanying drawings. In FIG. 1, a coin inserted from a coin input port 1 passes through a thickness checking screw 2 and enters a coin inspection passage 3. By adjusting the amount of protrusion of the tip of the screw 2 into the coin passage, the thickness of the coin entering the coin inspection passage 3 is regulated, and counterfeit coins that are thicker than genuine coins are removed by the screw 2. I can stop it. A thread cutting protrusion 4 with a sharp tip protruding into the coin passage in front of the coin inspection passage 3 is used to prevent selling goods from being fraudulently stolen by inserting coins suspended by a thread from the input slot 1. The coin inspection passage 3 has three coin detectors 5, 6,
7 are arranged in order. The first stage coin detector 5 is for detecting the coin diameter, and consists of a primary coil 5a and a secondary coil 5b (see Figures 2 and 4), and the magnetic flux is as shown in Figure 2. The coils 5a and 5b are arranged in such a relationship that Φ is substantially perpendicular to the radial direction of the coin to be tested 8 falling in the coin testing path 3 (substantially perpendicular to the radial surface). Therefore, the larger the coin diameter, the more the magnetic flux Φ is cut, and a detected waveform having a peak value (in this case, a negative peak) corresponding to the coin diameter is obtained from the secondary coil 5b. For example, the coin detectors 6 and 7 in the latter stage are disclosed in Japanese Patent Application No. 1987-
A differential transformer type coin detector as described in the specification of No. 68111 is used to test different coin properties. For example, one coin detector 6 inspects the material of the coin, and the other detector 7 inspects the surface pattern shape of the coin. For this reason, the excitation frequency f ₂ of the primary coil 6a (see FIG. 4) of one coin detector 6 is set to a frequency that makes it easy to detect the coin material, and the
The excitation frequency _f3 of the secondary coil 7a (see FIG. 4) is set to a frequency that makes it easy to detect the pattern shape on the coin surface. When the coin passes through the coin detector 7 at the final stage, the authenticity inspection is completed, and if the coin is genuine, the acceptance solenoid 9
(see FIG. 3) is energized, and the receiving protrusion 10 is attracted in the direction of arrow A. An opening 11 located below the end portion of the coin inspection passage 3 is normally open toward the return passage 12, and the protrusion 10 enters the opening 11 only when the solenoid 9 is energized by detection of a genuine coin. to block the entrance of the return passage 12. Therefore, the coin inspection passage 3 is opened only when the solenoid 9 is energized.
The coins that come out of the coin are guided to a genuine coin passageway 13 and accepted, and at other times, the coins are guided through an opening 11 to a return passageway 12 located below the passageway 13 and returned to a return slot (not shown). It can be done. The circuit shown in FIG. 4 controls the coin-accepting operation in the mechanism of FIG. 1, and provides a counting pulse to the input amount counter when a coin is accepted. The oscillator 14 supplies predetermined excitation frequencies f1 _{to f3 to} the primary coils 5a to 7a of each coin detector 5 to 7, and the frequency _f1 is always supplied to the coin diameter detector 5. However, the power supply to the coin detectors 6 and 7 is switched through gates 15 and 16. Detection signals outputted from two secondary coils 6b, 6c and 7b, 7c connected in reverse phase series of differential transformer type detectors 6, 7 are sent to detection amplifiers 17, 18, respectively.
The alternating current component is removed and input to the OR circuit 19. The detection output from the secondary coil 5b of the coin diameter detector 5 is sent to a detection amplification and phase inversion amplifier 20.
, the alternating current component is removed, and the negative peak waveform is inverted to the positive peak waveform. In this embodiment, since the coin detection waveform of the detector 5 is obtained as a valley-shaped attenuated waveform, this is inverted to a mountain-shaped waveform. A detection signal from the coin diameter detector 5 is applied to comparators 22 and 23 via a line 21, and appears on a line 240 via an OR circuit 19. Therefore, in response to one coin passing through the coin inspection passage 3, the secondary coils 5b, 6b,
Since the detection waveforms occur in order at 6c, 7b, and 7c, only the coin diameter detection waveform 5b' of the detector 5 appears on the line 21, as shown in FIG. 5a.
As shown in FIG. 5c, the line 240 includes a coin diameter detection waveform 5b' and a coin material detection waveform 6 from the detector 6.
b', 6c' and coin surface pattern shape detection waveforms 7b', 7c' from the detector 7 appear in order. line 24
The detected waveforms 5b' to 7c' of 0 are input to comparators 24 to 29, respectively, and compared with reference levels set in each of the comparators 24 to 29. The comparators 22 and 23 detect that a coin has entered the coin diameter detector 5, and the coin diameter detection waveform 5
The level below b' (near the bottom) is the set reference level. The reference level e ₁ of the comparator 22 is somewhat higher than the reference level e ₂ of the comparator 23 (Fig. 5a).
reference). It is assumed that the comparators 22 to 29 output a signal "1" when the level of the input coin detection waveform becomes higher than its set reference level. Therefore, the level of the coin diameter detection waveform 5b' is the reference level _e1
When it becomes higher than , comparator 22 outputs a signal "1" and flip-flop 30 is set. Also,
When the level of the detected waveform 5b' becomes lower than the reference level _e2 , the output of the comparator 23 changes to "0". Therefore, the flip-flop 30 via the inverter 31
is reset, and the output of the flip-flop 30 almost corresponds to the time width of the coin diameter detection waveform 5b', as shown in FIG. 5b. Comparators 24 and 25 function similarly to the comparators 22 and 23, and the respective reference levels e ₃ and e ₄
is the level near the bottom of the mountain-shaped detection waveforms 6b' to 7c', and the levels are somewhat different. As will be described later, when the coin diameter detection waveform 5b' is generated, the reference levels e ₃ and e ₄ are not applied, and the comparators 24 and 25 do not operate.
Flip-flop 3 when the upper reference level e ₃ is exceeded
2 and is reset when the lower reference level _e4 is exceeded, so that the output of the flip-flop 32 becomes the coin detection waveforms 6b', 6c', and 6c', as shown in FIG. 5d.
This almost corresponds to the time width of 7b' and 7c'. Since the levels e ₁ and e ₃ for setting the flip-flops 30 and 32 are different from the levels e ₂ and e ₄ for resetting them, a hysteresis characteristic is provided between the setting and resetting of the flip-flops 30 and 32. Therefore, coin detectors 5, 6, 7
Even if the coin detection waveform obtained from the
It can be obtained exactly from 0.32. If the flip-flops 30 and 32 are set and reset at one level, the coin detection waveform will be disturbed and the set/reset will occur.
When the reset level is raised and lowered in small steps, setting and resetting are repeated frequently, resulting in a large number of pulses per detected waveform. In order to prevent this, two reference levels are used as in this example.
Using e ₁ , e ₂ or e ₃ , e ₄ is extremely effective. Comparators 26, 27 and 28, 29 are paired, respectively, and set the upper and lower threshold levels of window circuits 33, 34 for determining the peak level of the coin detection waveform. For example, if the window circuit 33 is used to detect the peak level of the 10 yen coin detection waveform, the upper limit reference level _H1 set in the comparator 26 sets the upper limit value of the peak level of the 10 yen coin detection waveform. It is something.
The lower limit reference level _L1 set in the comparator 27 is used to set the lower limit value of the peak level of the 10 yen coin detection waveform. Furthermore, assuming that the window circuit 34 detects the peak level of the 50 yen coin detection waveform, the reference level H ₂ of the comparator 28 is the one that sets the upper limit of the peak level of the 50 yen coin detection waveform. The lower limit value set is the reference level _L2 of the comparator 29. Each reference level H ₁ , L ₁ , H ₂ , L ₂ is set to a value corresponding to the coin property to be inspected by the coin detector 5, 6, 7 as the coin passes through the coin detector 5, 6, 7 in order. can be switched in order. Taking the window circuit 33 of a 10 yen coin as an example, as shown in _{FIG .} Switch.

[Table] Similarly, the upper limit reference level H ₂ and lower limit reference level L ₂ of the window circuit 34 for the 50 yen coin have three values e ₁₁ , e ₁₂ ...e ₁₆ corresponding to the detection waveform of each coin property. Switch sequentially. Reference level e ₁ of each comparator 22 to 29
e ₄ , H ₁ to L ₂ (e ₅ to e ₁₆ ), are the reference voltage generation circuit 35
Supplied from. Reference level H ₁ , L ₁ or H ₂ ,
Since the value of L ₂ is switched in order, one window circuit 33 or 34 is required for each denomination even when inspecting the detection waveform peak level regarding the properties of a plurality of coins (three in this example). Now, the output "1" of the flip-flop 30 (FIG. 5b) which occurs when a coin enters the first coin detector 5 satisfies the condition of the AND circuit 36 and sets the flip-flop 37. AND circuit 36
The reset side output of the flip-flop 37 and the acceptance solenoid disconnection detection signal are added to the other inputs of , and since these are normally "1", the conditions of the AND circuit 36 are satisfied. When the coin acceptance solenoid 9 is disconnected, the signal becomes "0", which disables the AND circuit 36, inhibits the operation of the circuit shown in FIG. 4, and prevents the output of counting pulses. The set output of flip-flop 37 is on line 3.
8 and sets the flip-flop 39. The timer 40 is set by the rise of the set output "1" of the flip-flop 39, and the timer operation starts. Operation time of timer 40
_T1 is a time approximately equivalent to the time when the inserted coin finishes passing through the entire length of the coin inspection path 3, that is, all the coin detectors 5, 6, and 7, that is, the coin inspection completion time (see FIG. 5). Operating time of timer 40 T ₁
When the timer 40 ends, an output "1" is generated,
The flip-flop 37 is reset via the OR circuit 41. Therefore, the time when the line 38 becomes the signal "1" corresponds to the operating time _T1 of the timer 40.
Further, the flip-flop 39 is reset by the output "1" of the timer 40 via an AND circuit 42 and an OR circuit 43. On the other hand, when the output of the flip-flop 30 becomes "1", the condition of the AND circuit 49 is satisfied by the set output "1" of the flip-flop 37 and the reset side output "1" of the flip-flop 48. The line 50 becomes a signal "1" due to the output "1" of the AND circuit 49, and the signal " ₁ " is sent to the first stage R1 of the shift register 52 via the OR circuit 51.
Load. Next, when the coin finishes passing through the first coin detector 5, the output of the flip-flop 30 falls to "0" (FIG. 5b), so the falling pulse generating circuit 4
4, one pulse is generated at the falling edge. The falling pulse generating circuits 44, 45, 46, and 47 are circuits that generate one short pulse when the input signal falls from "1" to "0". The output pulse of the falling pulse generation circuit 44 is output from the flip-flop 4.
At the same time, the flip-flop 54 is reset via the AND circuit 520 and the OR circuit 53. Further, the output of the AND circuit 49 becomes "0", so that the signal on the line 50 becomes "0". The signal on line 50 is therefore the output of flip-flop 30 (fifth
This corresponds to Figure b). The signal on line 50 is applied to AND circuits 55, 56 and makes it possible to store the coin diameter test results. Therefore, line 5
The signal “1” of 0 corresponds to the coin diameter inspection period TE ₁ . To explain the operation with reference to window circuit 33, the output of upper threshold comparator 26 is applied to NOR circuit 57, and the output of lower threshold comparator 27 is applied to the set input of flip-flop 58. When the level of the coin diameter detection waveform 5b' exceeds the lower limit reference level L ₁ (e ₆ ), the flip-flop 58 is set and its reset output becomes "0". If the peak level of the detected waveform 5b' does not exceed the upper limit reference H ₁ (e ₅ ), the output of the comparator 26 is "0" and the output of the NOR circuit 57 is "1". When the detection waveform 5b' is almost completed, the flip-flop 30 is reset, so that
The reset output "1" resets the flip-flop 58 via the AND circuit 59, and the output of the NOR circuit 57 becomes "0". Therefore, one pulse is generated from the falling pulse generation circuit 46 and input to the AND circuits 55, 60, and 61. Since the coin diameter inspection period TE ₁ (or just before it ends), the signal on line 50 is "1" and the signal on line 38 is also "1", so the output pulse of the falling pulse generation circuit 46 is A 10 yen coin diameter memory flip-flop 63 is set via an AND circuit 55 and an AND circuit 62. Therefore, "1" is stored in the flip-flop 63 when the diameter of the coin is verified to be a genuine coin. By the way, if the peak level of the detected waveform 5b' is above,
Especially when the peak level does not fall between the lower limit thresholds H ₁ and L ₁ (e ₅ , e ₆ ), the peak level falls below the upper reference level H ₁
(e ₅ ), the output of the comparator 26 becomes "1" and the output of the NOR circuit 57 falls to "0". Then, when the peak of the detected waveform 5b' falls, the output of the comparator 26 becomes "0", the output of the NOR circuit 57 rises to "1" again, and the reset output of the flip-flop 58 is reset to "1", causing the NOR circuit to The output of 57 falls to "0" again. Therefore, the peak of the detected waveform 5b' is the upper limit reference value H ₁ of the window circuit 33 or 34.
, two or more pulses are generated from the falling pulse generation circuit 46 during the coin test period _TE1 . In this case, the first pulse sets the flip-flop 63, but the next pulse resets the flip-flop 63 via the AND circuit 64. All the flip-flops used in this embodiment, including the flip-flop 63, are "reset priority flip-flops." Therefore, flip-flop 63 is preferentially reset by two pulses.
(Even if a set input is added at the same time).
Even if two or more pulses occur during the period _TE1 , the flip-flop 54 is set by the second pulse via the AND circuit 64, and its reset output becomes "0", so the AND circuit 64 is set.
If condition 2 is not satisfied, the third and subsequent pulses are blocked. Therefore, if the peak level of the coin detection waveform does not fall within the upper and lower thresholds of the window circuit, the memory of the test result storage flip-flop 63 (or 64, 65, 66, 67, 68, 69) is "0". It is. Therefore, the flip-flop 54 has a function that substantially cooperates with the discriminating operation of the window circuits 33 and 34. Signal “ ₁ ” of first stage R1 of shift register 52
is applied to the gate 15 and the reference voltage generation circuit 35 via the OR circuit 70, and supplies the excitation frequency f ₂ to the primary coil 6a of the coin detector 6 via the gate 15. In this way, the second coin detector 6 is enabled for detection operation and generates detection waveforms 6b' and 6c' in response to coins falling through the coin detector 5. At this time, the reference voltage generation circuit 35
The AC signal _f2 supplied to the coil 6a via the coil 6a is received, and the DC reference voltage is determined based on this signal _f2.
e ₇ , e ₈ , e ₁₃ , e ₁₄ are generated, and the values of the outputs H ₁ , L ₁ H ₂ , L ₂ are changed to these voltages e ₇ , e ₈ , e ₁₃ , e according to the signal from the OR circuit 70. Switch to ₁₄ . Also, AC signal
If f ₂ or f ₃ is applied, the reference voltage e ₃ , e ₄
is supplied to comparators 24 and 25. As shown in FIG. 5d, coin detection waveforms 6b', 6
A pulse approximately corresponding to the time width of c' is output from the flip-flop 32, and the falling pulse generation circuit 4
5 outputs one short pulse in response to the falling edge of these pulses. At this time, since the signal on the line 50 is already "0", a pulse is output from the AND circuit 71 having an inhibit gate for the signal on the line 50 in response to the falling pulse, and the pulse is outputted to the shift register 52 via the OR circuit 51. The signal " ₁ " of the first stage R1 is shifted to the next stage. shift register 52
has a configuration in which the first read single signal "1" is sequentially shifted by pulses from the OR circuit 51. Therefore, when the detection waveform 6b' is almost completed, the signal "1" is shifted to the second stage _R2 . step
The output “1” of R ₂ continues the f ₂ excitation of the primary coil 6a via the OR circuit 70 and the line 7
A signal “1” is given to 2. Window circuit 33 or 34
operates in the same manner as described above to inspect the peak level of the material, and outputs one pulse per detected waveform in the case of genuine coins. When the peak level of the specie is detected with respect to the detection waveform 6c', since the line 72 is a signal "1", the signal is passed through the AND circuit 60 (or 73 in the case of 50 yen), AND circuit 78 or 79.
10 yen coin material inspection result memory flip-flop 65
(or 68 in the case of 50 yen) stores the signal “1”. When the coin detection waveform 6c' almost ends, the signal "1" of the shift register 52 is shifted to the third stage _R3 by the output pulse of the falling pulse generating circuit 45. Gate 15 is therefore inoperative. Also,
Flip-flop 54 is reset via an AND circuit 74 with an inhibit gate for the signal on line 50 approximately every time the detected waveform is completed. The signal " ₁ " of stage R3 is applied to the gate 16 and the reference voltage generation circuit 35 via the OR circuit 75, and is applied to the primary coil 7a of the coin detector 7 via the gate 16.
Supply excitation frequency f ₃ to . In this way, the last detector 7 becomes capable of detecting operation, and in response to the coin falling through the coin detector 6, the detection waveforms 7b', 7
generate c′. At this time, the reference voltage generation circuit 35
receives the AC signal f ₃ fed to the coil 7a via the gate 16, creates DC reference voltages e ₉ , e ₁₀ , e ₁₅ , e ₁₆ based on this signal f ₃ , and outputs the OR circuit 75
The values of the outputs H ₁ , L ₁ , H ₂ , and L ₂ are switched to these voltages e ₉ , e ₁₀ , e ₁₅ , and e ₁₆ in accordance with the signals from the . Therefore, a pulse is generated from the flip-flop 32 in accordance with the coin detection waveforms 7b' and 7c' (FIG. 5d), and the window circuits 33 and 34 perform a peak level inspection regarding the pattern shape on the coin surface. Detection waveform 7
One pulse outputted from the falling pulse generation circuit 45 corresponding to almost the end of the shift register 5
2 is passed to stage R ₄ and provides a signal "1" on line 76. Therefore, when the peak level of a genuine coin is detected with respect to the detection waveform 7c', the condition of the AND circuit 61 (or 77 in the case of 50 yen) is satisfied, and the coin surface pattern is detected via the AND circuit 80 (or 81). Shape inspection result memory flip-flop 6
6 (or 69 in the case of 50 yen) is stored as a signal "1". When the last detection waveform 7c' is almost completed, the signal "1" of the shift register 52 is shifted to the final stage _R5 by the output of the falling pulse generating circuit 45. The gate 16 is therefore inoperative and only the excitation frequency f ₁ is applied to the primary coil 5a of the coin detector 5, waiting for the next coin to arrive. Further, when only the AC signal f ₁ applied to the primary coil 5a of the first stage coin detector 5 is input to the reference voltage generating circuit 35, that is, when the signals from the OR circuits 70 and 75 are both "0". , generate reference voltages e ₁ , e ₂ , e ₅ , e ₆ , e ₁₁ , e ₁₂ based on the AC signal f ₁ and supply them to comparators 22, 23, 26-29. Now, when the operating time _T1 of the timer 40 ends, the signal on the line 38 becomes "0" as described above, but at this time the coin inspection has already been completed, and the flip-flops 63, 65, 66 or 67, 6
The test results are stored at 8 and 69. If the three coin properties tested are all specie,
If the coin is a 10 yen coin, the outputs of the flip-flops 63, 65, and 66 are all "1", and the output of the AND circuit 82 is "1". Also, if it is a 50 yen specie, flip-flop 67-69
The outputs of the AND circuit 83 are all "1", and the output of the AND circuit 83 is "1". The output of the AND circuit 82 is input to the inhibit gates of the AND circuit 84 and the AND circuit 85, and the output of the AND circuit 83 is input to the AND circuit 8.
5 and the inhibit gate of the AND circuit 84, respectively, to prevent genuine coin signals of different coins from being output at the same time. The output of the final stage _R5 of the shift register 52 is added to the other inputs of the AND circuits 84, 85, and the AND circuits 84, 85 become operational when all coin inspections are reliably completed. The output "1" from the AND circuits 84 and 85 is a genuine coin detection signal, indicating that the inserted coin should be accepted. These outputs are AND circuit 8
6 and 87, the coins are input to a 10 yen coin counter 88 and a 50 yen coin counter 89, respectively, and the number of inserted coins is counted. This counter 88,
The count contents of 89 are used in a vending control circuit (not shown) of the vending machine for vending operations, change dispensing operations, etc. Also, AND circuits 84, 85
The output is applied to the input coin number control unit 90 and counted there, and when the upper limit number of coins in one coin input operation is exceeded, the output of the control unit 90 becomes “0”, and even if the coins inserted thereafter are genuine coins, they are counted. Even if it is possible, acceptance will be prohibited. The control unit 90 outputs "1" only when genuine coins are accepted, and outputs "0" when coins are not accepted due to counterfeit coins or excess coins. Further, the genuine coin acceptance signals from AND circuits 84 and 85 set a flip-flop 93 via an OR circuit 91 and an AND circuit 92. The set output of flip-flop 93 is applied to AND circuit 94, sets flip-flop 95, and starts operation of timer 96. The output of the timer 96 is normally "0" and becomes "1" when the timer operation time ends. Therefore, the AND circuit 94, in which the output of the timer 96 is applied to the inhibit gate, becomes an output "1" at the same time as the flip-flop 93 is set, and the receiving solenoid 9
(See Figure 3). This activation of the solenoid 9 continues until the operating time of the timer 96 ends. Therefore, as soon as the coin passes the last detector 7, if it is a genuine coin, the receiving protrusion 10 attracted by the solenoid 9 will open the opening 1 of the coin passage.
1 and accept coins into the specie passage 13 (the first
(see figure). The operating time T ₂ of the timer 96 corresponds to the time interval between coins when genuine coins are inserted continuously to the extent that double insertion is not performed. When the next coin comes to the position of the coin detector 7 during the operation time of the timer 96, and the stage _R4 of the shift register 52 becomes a signal "1", a signal "1" is applied to the reset input of the flip-flop 95, and the reset is performed. Since it has priority, it is forced to reset. If the coin is a genuine coin, a signal "1" is applied to the set input of the flip-flop 95, so as soon as the reset input falls to "0", the flip-flop 95 is set, and the input of the timer 96 rises, so that the timer is activated. The operating time starts again from the beginning. Therefore, when coins (specified coins) are continuously inserted, the output of the timer 96 remains "0" without interruption, and the solenoid 9 continues to be energized. Of course, if the next successively inserted coin is a counterfeit coin, the output from stage _R5 of the shift register causes the AND circuit 106 (the inhibition is released by the output "0" from the control section 90).
The output of the flip-flop becomes "1", resets the flip-flop 93, and the flip-flop 95 is not set. When the operating time of timer 96 expires, the condition of AND circuit 97 is satisfied, and flip-flop 93 is reset via OR circuit 98. If the receiving solenoid 9 does not operate due to a failure, a signal "1" is applied to the line 99, and the AND circuit 10
0 to set flip-flop 101;
I am trying to issue a failure signal ST. The output of the final stage _R5 of the shift register 52 is applied to a reset signal register (not shown) via a delay circuit 102 to generate a reset signal. This reset signal is for resetting the memory of each flip-flop of the coin receiving device shown in FIG. 4, and the reset signal is output every time one coin is inspected. Next, prevention of double input will be explained. If the previously inserted coin is still in the coin inspection path 3, there is a signal "1" in any of stages _R1 to _R4 of the shift register 52, and stage _R5 is "0". Therefore, the inhibit gate of the AND circuit 103 is
The signal applied from _R5 is "0". Further, when the coin diameter inspection period TE ₁ of the previously inserted coin has ended, the output of the AND circuit 49 is "0", and this is added to the other inhibit gate of the AND circuit 103. In this state, when the next coin enters the coin inspection passage 3 due to double insertion, the output of the flip-flop 30 becomes "1", and the AND circuit 103
The output of becomes "1". Thus, when a double throw is detected, the output of AND circuit 103 sets flip-flop 104, and this set output is applied to the reset signal register (not shown).
Generates a reset signal (not shown). This reset signal causes each flip-flop (especially flip-flops 63 to 69) in FIG. 4 to be reset, and no coin inspection/discrimination operation is performed. Therefore, the receiving solenoid 9 is not energized and all double-inserted coins are returned to the return path 12. When the last coin of the double input coins passes the first detector 5, the output of the AND circuit 105 is "1" and resets the flip-flop 39 via the OR circuit 43, but the output of the OR circuit 43 is "0". When it returns to , the output of flip-flop 37 is "1", so flip-flop 39 is immediately set. Therefore, the timer 40 returns the timer operation to the beginning upon the rise of the output of the flip-flop 39, and restarts the operation time _T1 . As a result, the operation of the timer 40 continues while coins are being inserted twice, and the original operating time T ₁ of the timer 40 has elapsed since the last double-inserted coin entered the coin inspection passage 3. When this occurs, the timer operation ends and an output "1" is generated. This output "1" is applied to the reset input of flip-flop 104 and releases the generation of the reset signal. Therefore, the flip-flops 63, 65 to 69, etc. of the circuit for inspecting and determining coins are released from reset and can operate normally. In this way, timer 40
By delaying the operation, the last double-inserted coin is ensured to enter the return passage 12.
FIG. 4 Normal operation of each circuit is started. In the above embodiment, the coins to be tested are 10 yen and 50 yen, but the present invention is not limited to these and can be applied to any number of different types of coins. In the above embodiment, a transformer type detector is used as the coin diameter detector 5, but a differential transformer type detector having two secondary coils connected in series and in reverse phase may also be used. Further, although differential transformer type coin detectors 6 and 7 are used, transformer type ones may also be used. Further, instead of the shift register 52, a counter and a decoder or a counting circuit formed by combining a plurality of flip-flops and logic gates may be used, and in short, any sequential control circuit may be used. <Effects of the Invention> Since the present invention is constructed as described above, if all the coins sequentially inserted are genuine coins, the receiving solenoid continues to be energized, the genuine coin receiving passage continues to open, and coins are accepted one after another. Therefore, there is no need for frequent opening and closing of the genuine coin receiving passage, which has the effect of suppressing fatigue and wear and tear of the mechanical parts.

[Brief explanation of the drawing]

FIG. 1 is a schematic structural explanatory diagram showing the mechanical parts of an embodiment of the device of the present invention, FIG. 2 is a diagram illustrating an example of the configuration of a coin diameter detector, and FIG. 3 is a diagram showing the line -
4 is a block diagram showing the circuit portion of an embodiment of the device of the present invention, and FIG. 5 is an output waveform timing chart of each part in FIG. 4. 1... Coin slot, 3... Coin inspection passage, 5...
...Coin diameter detector, 6, 7...Coin detector, 9...
Acceptance solenoid, 12... Return passage, 13... Specie acceptance passage, 14... Oscillator, 22-29... Comparator, 33, 34... Window circuit, 35... Reference voltage generation circuit, 40, 96... ...Timer, 52...Shift register.

Claims (1)

[Claims] 1. A coin detection unit including a plurality of coin detectors that individually detect various coin properties along a coin path, and a coin detector that judges the detection output of each coin detector and integrates the judgment results. a determination circuit that determines whether genuine coins are genuine or counterfeit; A coin sorting electromagnetic device that guides the coins to the coin passage, and an operation time that starts in synchronization with the start of the operation of the coin sorting electromagnetic device and corresponds to the time required to reliably guide the coins to the coin passage. a timer circuit which releases the operation of the coin sorting electromagnetic device at the end of the operating time, and an operating time of the timer circuit if the next coin inserted is determined to be a genuine coin during the operating time of the timer circuit. 1. A coin accepting device for a vending machine, comprising a timer control circuit for resetting the coins, and the electromagnetic device continues to operate when genuine coins are continuously inserted at a predetermined interval or more.