JPS62169569A - Ccd 1-dimensional image sensor - Google Patents

Abstract

PURPOSE:To obtain accurate image information by finishing the integration at the 1st storage part when the output of a monitor store part is set at a prescribed level to transfer the integration to the 2nd storage part for storage and then outputting it to a shift register at the next stage. CONSTITUTION:The 2nd charge storage part GAn and gate parts EGn and CGn are provided between a charge storage part FAn and a CCD register CAn. Thus the end of integration is confirmed when the electric charge produced by a photoelectric converter stored in the 1st charge storage part is transferred to the part GAn only with an operation of the gate at the part EGn regardless of the cycle of a transfer clock. In this example, the part CGn, i.e., a clear gate opposite to the part GAn is provided but is not always needed. Here the gate CGn does not need the data after the electric charge is once transferred to the part GAn from the part FAn. This data is needed only the start of reintegration is desired. This need is decided by the sequence of an AF action.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application: This invention relates to a CoDl-dimensional image sensor [Prior Art] FIG. 10 shows the configuration of a one-dimensional image sensor 1 using a conventional COD.

Photoelectric conversion element array, EAn (n=l, 2°...n...
), flood storage element array FAn, charge transfer register CA n
, CBn, gates between them, and an output stage, and the illuminance of the image projected onto the photoelectric conversion element array from the O8 terminal is output as an electrical signal by photoelectric conversion. Further, a monitor photodiode MP is arranged near the photoelectric conversion element array EAn, and the monitor photodiode MP
The integrated value of the photocurrent is output from the GCO5 terminal, and
The base Q voltage of the 2O3, 1\GCO8 signal is output from the DO9O9 terminal.

Here, a detailed explanation will be given regarding the point that the output of the photoelectric conversion element array Et~n is output from the O5 terminal.

The application of the ICG pulse becomes an integration start signal, and the MOS transistor CG between the electric A storage element array FAn and ;-u71
ON L Each charge storage element F, -n is initialized, and the MO8 connected between the floating gate MFG of the monitor switch auto MPII and the 7ij source is turned on.
Turn on I-Lannostar MCG, clear the output of monitor 1st GUIO+:X1p.

Next, after removing the ICG pulse, each photoelectric conversion element EAn':
A charge proportional to the illuminance of the image projected on the photoelectric conversion element EAn is generated in each photoelectric conversion element EAn, and the charge passes through each floating gate and is stored on the charge storage element FAn. The charge generated by the monitor photodiode MP is stored in the charge storage capacitor via the floating gate Ml''G, and a signal indicating the charge storage status is output from the AC/COS terminal in real time.In this way, the AGCOS output or the predetermined level is output. When the amount of charge generated in each photoelectric conversion element EAn is determined to be appropriate for the subsequent processing circuit, the gate SGn is turned on by applying the S I-1 pulse to charge the charge in each charge storage element FAn. The integration is completed by transferring the data in parallel to the transfer register CAn.

Here, the shift gate SGn forms a potential well in the high period of the φ1 clock of the charge transfer register and is connected to the transfer channel CAn that captures the charge, so the generation of the shift pulse SH is in phase with the transfer lock. It is necessary to first transfer the lock to φ, =
After dividing I-T, φ, and forming a bottom well under the shift register CAn, the shift pulse SH is set to High to connect the charge storage element FAn and the noft register CA.
The charges accumulated during the ONt integration time of the transistor SG (MOS) between n and SG are injected into the bottom soyral well formed by φ+H+gh of the soft resistor.

Thereafter, charge transfer registers CAn and cBn are transferred to register C at the cycle of transfer lock φ1 when clock φ1 is High.
An, clock φ, register CB when = High
When n, φ+ = High, the charge is transferred to the cloth in the figure, such as register CAn-1, and register CBO
The voltage is then converted into a voltage and taken out from the terminal O9 via the output stage buffer. As a result, the voltage-converted image information is sequentially output to the O8 terminal from the pixels of the photoelectric conversion element EAI in synchronization with the fall of the transfer lock φ1 after the shift pulse is generated. The timing of these controls is shown in FIG. 1L, and these drive circuits are shown in FIGS. 12 and 13.

The drive circuits shown in Fig. 12 and Fig.
This is the circuit shown in Publication No. 1516. 2 is a one-dimensional image sensor shown in FIG. 10, 10 is a transfer lock pulse generation block, and 2o is a digital signal that forms the basis for determining the focus adjustment state of the photographic lens based on the signal from the one-dimensional image sensor 1. The circuit block 3o is a microcomputer that determines the focus adjustment state of the photographing lens based on the digital signal from the circuit block 20, and also controls each circuit block.

Further, 40 controls the amplification factor of the amplifier in the circuit block 20 based on the output of the brightness monitor circuit in the one-dimensional image sensor 1, and controls the charge accumulation time (photocurrent integration time) in the one-dimensional image sensor 1. AN I and AN 2 are AND circuits that together with an OR circuit ORI form a gate means, and DPI is a flip-flop FFn DC"lTLgr>I'q(!?,
DF2 is a D flip-flop that generates lIk, t2 pull llh +-, e pulses; DF2 is a D flip-flop that generates a shift pulse that transfers the charge accumulated in the charge storage element FAn to the charge transfer register An in the image sensor 1; CLl; is a clock circuit that generates a reference clock pulse, and FF"0 is an R-S flip-flop.

Transfer lock pulse φ1. To explain an example of the circuit configuration of the transfer lock pulse generation block lO that generates φ2, F
FI, FF2...FF6 are flip-flop circuits forming a frequency dividing circuit, and the first stage flip-flop FFI
A clock pulse (period: 2 .mu.sec) from the clock circuit CLI is input manually to the T input of the . flip flop FF3
．． FF4. The Q outputs of FF5 and FF6 are respectively input to the OR circuit ○R2, and the output of the OR circuit 0r (2 is input to one input of the AND circuit AN4. The other input of the AND circuit AN4 is input to the inverter. It is connected to the terminal T22 of the microcomputer 30 via the INI, and when the terminal T22 outputs a "0" signal, the AND circuit AN4 or D outputs the "B" signal of the 0R20. On the other hand, one input of the AND circuit A N 5 is connected to the input circuit CL2, and the other input is connected to the above-mentioned terminal T22. Therefore, when the above-mentioned terminal T22 outputs the "B" signal, , clock circuit C
Outputs the clock pulse from L2. Here, the cycle of the clock pulse output from the clock circuit CL2 is set to be several tens of times shorter than the cycle of the output Q6 of the flip-flop FF6, which is the frequency-divided clock pulse output from the clock circuit CLI. OR circuit OR3 is connected to AND circuit AN4. When any output signal of AN5 is "1", the signal of "B" is transferred to the COD shift register CAn, C in the one-dimensional image sensor l as a lock pulse φ2.
Output to Bn. Also, an inverter is installed in the OR circuit OR3.
N2 is connected, and this inverter rN2 transfers a signal with the opposite phase to φ2 and uses it as a lock pulse φl to be applied to the CCD shift registers CAn and C in the one-dimensional image sensor 1.
Bn and the image signal output circuit VS (see FIG. 1O). The "B" signal from the terminal T22 of the microcomputer 30 is a signal for causing the image sensor to perform an initializing operation.

FIG. 13 shows an example of the brightness determination circuit 40 and the circuit block 20. In this figure, TIO and TI.

T12 are terminals AGCO8 and DOS in FIG. 1O, respectively.

This is a terminal connected to terminal T13. TI5,T
16, a sample designation pulse and a sample designation reset pulse are input manually from the microcomputer 30 via the data bus DPI, respectively, as will be described later. Also, terminal T1
4 is connected to one input of the AND circuit AN2 in FIG. First, the brightness determination circuit 40 will be explained. This circuit uses the output voltage AGC of the brightness monitor circuit MC described above.
Comparators Act, AC2, and Δ3°AC4 are provided for determining in stages the degree of drop after the disappearance of the integrated clear pulse of the OS. The inverting inputs of these comparators are buffer B1
are connected to the terminal TIO via the respective terminals TIO. On the other hand, the non-inverting inputs of these comparisons 11Acl, AC2° AC3, AC4 are connected to the connection point J4 between the resistor R1 and the constant current source 11, and the resistor R
2 and constant current source■ Connection point J5 of 2, resistor R3 and constant current source■
3 connection point J6, connection point J7 of resistor R4 and constant current source T4
are connected to the resistors r(1, R2, R3, R4
is connected to terminal Tll via buffer B2.

If the circuit is connected like this, the connection points J4°J5. J6
．． J7 is connected to resistors R1, R2, R3,
A voltage is generated after subtracting the voltage drop at R4, and the resistance values of resistors R1, R2, R3゜R4 and constant current sources II, 1
2,13. By selecting the current value of r4, the terminal TI
Depending on the degree of voltage drop in the output voltage AGCO8 of the luminance monitor circuit MC inputted to
The outputs of AC2, AC3, and AC4 sequentially change from “0” to “l”
to be reversed. DT3. DT; "4. DT5 is a D flip-flop whose zero power is connected to the outputs of comparators ACI, AC2, and AC3, and the soft pulses from the D flip-flop DF2 are input to their CP large inputs. And , when the shift pulse is input, the D flip-flops DF'3., DT4.DF'5 output the outputs of the immediately preceding comparators AC1, AC2, AC3 to the Q output, respectively, and the ζ output outputs the inverted output. AN6 is an AND circuit with one input connected to the Q output of the D flip-flop DF'3 and the other input connected to the Q output of the D flip-flop DF4, and AN7 has one input connected to the Q output of the D flip-flop DF4. This is an AND circuit whose other input is connected to the Q output of the D flip-flop DF5, and the output of the AND circuit AN6, AND7, the output a of the D flip-flop DF3, and the Q output d of DP5. , furthermore, the output e of the comparator AC4 becomes the output of the brightness determination circuit 40. That is, these outputs are the outputs of the monitor light receiving element MP.
This is a signal indicating the brightness level detected by .

The remaining circuits in FIG. 13 constitute circuit block 20 in FIG. 12. 22 corresponds to the difference between the output voltage Vos of the image signal output circuit VS inputted from the terminal TI2 via the buffer B3 and the output voltage V ref of the reference signal generation circuit RS inputted from the terminal T11 via the buffer B2. This is a subtraction circuit that generates an output V1. 24 is a peak value V2 (lowest level pixel signal) of an image signal corresponding to the accumulated charge of a predetermined value of photoelectric conversion elements excluding the photoelectric conversion elements at both ends covered with an aluminum film in the photoelectric conversion element array EAn. ), and latches and outputs them, thereby forming a so-called dark output correction signal V2.

T15. T16 is an input terminal that receives a zumbling designation pulse and a sampling designation reset pulse for setting the sampling period of the peak value detection circuit 24 from the microcomputer 30 via the data bus DBI.

Reference numeral 26 denotes a differential amplification difference amplifier for the output signals Vl and V2 of the circuits 22 and 24, and the amplifier is configured such that its amplification factor is controlled by the outputs a, b, c, and d of the brightness determination circuit 40 described above. It is. In this amplifier, O
P is an operational amplifier, and its input terminal r1g is connected to circuits 22 and 24 via input resistors R5 and R6, respectively. R7 to R14 are resistors provided for setting the amplification factor of the operational amplifier OP, and R5, R6, f17 . R
When the resistance values of 8, R11, and RI2 are r, f19.
[13 is the resistance value of 2r, RIO, R14 is tf of 4r
fi UC, has a value. ASI to AS8 are analog switches, of which ASI to AS4 have output a.

The feedback resistance value of the operational amplifier OP is set by selectively activating 1-direction R7 to R10 according to b, c, and d, whereas AS5 to AS8 outputs a, b, c, and d.
The bias resistance value of the amplifier ○P is set by selectively activating the resistors R11 to R14 in accordance with this.

That is, A is the amplification factor of the operational amplifier OP, and this amplifier O
The output voltage of P is expressed as Vout=E+(V2-V1)XA,
This is input to the A/D converter ADC. However, E in the above equation is the voltage of the constant voltage source E, and is appropriately set according to the input level range of the A/D converter ADC. Then, each output of the A/D converter ADC corresponding to each pixel signal is
The focus adjustment state of the photographic lens is detected by digital calculation based on a predetermined program, which is input to the terminal T22 of the microcomputer shown in FIG. 2 via the data bus DBI. In this way, the amplifier 26 in FIG. 13 changes the amplification factor according to the output of the brightness determination circuit 40, and
Since it outputs a signal suitable for signal processing by the converter ADC, it is possible to adjust the focal state of the photographing lens over a wide brightness range.

Referring again to FIG. 12, the terminal TI7 of the microcomputer 30 is an output terminal for an integral clear pulse. Furthermore, when the generation of soft pulses is permitted, a signal of "1" is output from the terminal T19 of the microcomputer 30, and the accumulated charge is transferred from the photoelectric conversion element array EAn to the charge transfer registers CAn and CBn as described later. During the transfer, a signal "0" is output that prohibits the generation of soft pulses. The integral clear pulse /l! is output from the terminal T18 of the microcontroller 30. If a soft pulse is not generated by hardware for a predetermined period of time from the i-death point LO, a signal “B” is output. This signal: 1 output from terminal TI7.
, 1) Minute rear pulse H-t:: μ child T6 Honsuke j, Te-
The integral clear gate of the dimensional image sensor-1 is manually inputted to the CG, while the flip-flop FFO is set and its Q output is set to "1" to open the AND circuit ANl.

In addition, when the flip-flop FFO is set, when the "BI" signal that permits the generation of soft pulses is output from the terminal T18, the AND circuit AN2 is also opened. Only when the brightness is high, a "■" signal e is generated at time t2, before a predetermined time (100 msec) has elapsed from the time to when the integral clear pulse disappears.
is output. When the subject brightness is low, the output of the terminal T18 of the microcomputer 30 becomes "B" at time 3. When the subject brightness is high, the output of the AND circuit AN2 becomes "1" at time t2, and the subject brightness If is low, the output of the AND circuit ANI becomes ")" at time t3,
The output of either “B” is connected to D via the OR circuit OR1.
It is input to the flip-flop [)PI47)D input.

The CK (clock) of this D flip-flop is manually supplied with a bracketed clock pulse (period: 2μ) from the clock circuit CLI.
Since the same signal is input to the D input, the Q output of the D flip-flop DPI becomes "I" at the falling edge of the basic clock pulse, and the flip-flop P'FO is reset. The opened AND circuit AN+ or AN2 is closed, and the flip-flops FFI to F in the transfer lock pulse generation block 10 are closed.
F6 is reset and their Q outputs Q1 to Q6 all become "0".

When the AND circuit ANI or AN2 is closed in this way, the Q output of the D flip-flop DFl returns to 0'' at the next falling edge of the reference clock pulse, and eventually the Q output has a positive value of 2 μs. This means that a pulse has been output. This positive pulse is a reset pulse. On the other hand, D
The Q output of the flip-flop DF2 becomes "B" at the fall of the basic clock pulse from the clock circuit CLI immediately after the Q output of the D flip-flop DPI becomes "L".
Immediately after the Q output of the D flip-flop DF'l returns to "0", the Q output returns to "0" at the falling edge of the reference pulse of the same clock circuit. Therefore, at the Q output of the D flip-flop DF2, a positive pulse with a time width of 2 μsec is generated, which rises in synchronization with the falling edge of the reset pulse, and this is a shift pulse. This soft pulse is input to terminals 1 and 21 of the microcomputer 30, and is also input to terminals 1 and 21 of the microcomputer 30 through terminal T7. and is input to the shift gate SGn of the one-dimensional image sensor 1.

The above is a description of the overall circuit configuration in FIG. 12 and the circuit blocks that constitute it. FIG. 11 shows a timing chart when a shift pulse signal is generated during high brightness. The terminal AGCOS, which has been charged to the power saving state by applying the rCG pulse, lowers its potential as the charge accumulation progresses, and at the timing of L2, the shift pulse generation level V=r
(4・■4 is reached, and the output T14 of the comparator AC4 in FIG. 12 is inverted. Based on this signal, the clock circuit C
Flip-flop DF with a maximum delay of 2 μs for one cycle of LI
The output of the flip-flop DF2 is inverted, and the output of the flip-flop DF2, that is, the shift pulse SH is output with a delay of 2 μs for one cycle of the clock circuit CLl. This pulse SH is also formed with one period of 2 μs of the pulse of the clock circuit CLI, and the transfer of charge from the charge storage element PAn to the register CAn is completed at the falling edge of the pulse SH, so that the terminal T1
After a minimum of 4 μSec and a maximum of 6 μSec from the reversal of 4, the substantial charge storage in the charge storage element FAn, that is, the optical integration is completed.

[Problems with the prior art] However, when trying to obtain an image signal of a low-luminance object with higher accuracy, it is necessary to obtain a larger pixel output even at low luminance, that is, the photoelectric conversion element section High sensitivity is required.

Therefore, in the case of increasing the sensitivity, if an attempt is made to obtain pixel output at an appropriate level during high brightness, it becomes necessary to realize image sensor control using an extremely short integration time of about 10 μS.

For this reason, in the conventional method described above, excessive integration of about 6 μSec is performed, resulting in an increase in the average level of the pixel output, causing the problem that the pixel output becomes saturated in the subsequent processing circuit.

[Problems to be Solved by the Invention] This invention is capable of obtaining an image signal with high precision even when the brightness of the subject is low, while also being able to obtain an image signal at an appropriate level without performing excessive integration even when the brightness is high. An object of the present invention is to provide a one-dimensional image sensor that achieves this.

[Means for Solving the Problems] A one-dimensional image sensor of the present invention includes a photoelectric conversion section composed of a plurality of pixels, and a first photoelectric conversion section that accumulates charges from the photoelectric conversion section.
a second storage section to which the charge from the first storage section is transferred in parallel; and a second storage section to which the charge from the second storage section is transferred in parallel, outputting charges corresponding to each pixel in series. CCD
a monitor light-receiving section provided near the photoelectric conversion section; a monitor storage section that collects the output charge of the monitor light-receiving section; A transfer gate that transfers the charge in the storage section to the second storage section.

[Example 1] Fig. 1 shows an example of a one-dimensional line sensor according to the present invention.

Note that the same parts as shown in FIG. 10 are given the same reference numerals.

The difference from FIG. 1 is that a second charge storage section GAn is provided between the conventional charge storage section PAn and the COD renostar CAn.

Gate parts EGn and CGn are added.

As a result, regardless of the transfer lock period, the fcomi charge generated in the photoelectric conversion element stored in the first charge storage section is
It became possible to complete the integration by transferring the charge to the second charge storage section only by operating the n gate.

In this embodiment, a clear gate for CGn, that is, the second storage section GAn, is provided, but it is not necessarily unnecessary. This gate CGn is once changed from FAn to GAn.
This is necessary only when the data is no longer needed after the charge transfer to , and reintegration is to be started. Whether or not it is necessary is determined by the sequence in the AP' operation.

FIGS. 2 to 4 show circuit diagrams for driving the one-dimensional line sensor, and FIG. 5 shows its timing chart.

The circuit shown in FIG.
This is a circuit that applies the DPI output and the reset input of the clock pulse generation block, which were previously explained in FIG. For this reason, the completion of integration is the falling edge of SH1, so the excess integration time is reduced to 2μs, which was the minimum of 4μs and the maximum of 6μs in the conventional example shown in FIG.
s can be shortened to a minimum of 2 μs and a maximum of 4 μs.

The latch signal T13 of the gain switching circuit of the subsequent AGC circuit is also an inverted signal of this SHI signal, and its gain is controlled by the rise of this signal, that is, the value of the monitor output at the time of completion of integration. A timing chart for this circuit is shown in FIG. 5(a).

Figure 3 shows the first part of the one-dimensional image sensor shown in Figure 1.
M between the charge storage section PAm and the second charge storage section GAm
The OS transistor gate EGn is turned on at the start of the integration time of the I-dimensional sensor, and the charges generated by the photoelectric conversion element EAn are passed through the first charge accumulation section FAm and accumulated in the second charge accumulation section GAm, and the accumulation is completed. , that is, the completion of the integration time is ~10S transistor gate EGn
The configuration of the circuit that turns OFF is shown.

A one-dimensional image sensor l outputs the output of a NOR circuit circuit OR1 using human power from three signals: the pulse TI7 of the integration start signal ICG, the forced shift pulse T18 from the microcomputer 30, and the comparator output T14 of the brightness determination circuit 40. The circuit configuration is such that the S)[I gate input is applied, and the inverted signal of the Not"(circuit N0R1 is applied as a latch signal to the brightness determination circuit 40 via the inverter r\3. The NOR circuit circuit OR is activated by the pulse input of the integration start signal rCG.
The output of l is set to ow. In addition, the one-dimensional image sensor IJ) monitor circuit output A G COS becomes 7u pressure of 411i as the standard electrician, and the brightness judgment circuit/10 comparator output T I =I is Low (!: '
: Ru. Naturally, the forced shift pulse T18 from the microcomputer 30 is kept low. In this state, by removing the integration start signal ICG pulse, the NOR circuit NO
The output of Rl becomes i-1-1i, the MOS transistor gate EGn of the one-dimensional image sensor 1 is turned on, and charge storage by the second charge storage section GAn is started.

In the case of high brightness, the output AGCO8 of the monitor circuit drops sharply and a predetermined voltage drop occurs before a predetermined time elapses.
The T14 signal is inverted from Low to High. This signal is applied to the NOR circuit N01''tl in real time,
The output S Hl of the NOR circuit is OVt from I-l-1l.
MOS) of the one-dimensional image sensor and turns off the gate EGl'I of the runnostar. Therefore, the integration is completed immediately after the TI4 signal is inverted. on the other hand,
At low brightness, the TI4 signal does not invert within the predetermined time,
T1 of forced shift pulse of microcomputer 30
8 application causes an inversion of the output SHI of the NOR circuit circuit ORI. That is, in this case, the integration is completed immediately after the forced shift pulse T18 is generated.

At the same time, the T14 signal or T18 signal is connected to the AND gate AN
2, or ANl, respectively, and the output of the OR gate ORI becomes High, and the flip-flops DPI and D
The Q output of F2 becomes [-Tight] sequentially. Since the Q output of the flip-flop DF2 is a soft pulse SH, when it becomes High, the charge stored in the 27th load storage unit GAn is transferred to the corresponding cell of the not register CAn, and after that, φl , φ2, the image outputs are automatically sequentially output. (See Figure 5(b).)
However, if the microcomputer 30 is performing some other operation, it may not be able to check the completion of integration due to the inversion of the T14 signal, and it may not be possible to automatically capture the image output sequentially output from the image sensor.
If this is to be avoided, major restrictions will be placed on the software of the microcomputer 30.

Therefore, the charges accumulated in the second charge storage section GAn are held there until there is a data request from the microcomputer 30, and the charges are transferred from the second storage section GAn to the COD reno star CAn according to the data request signal from the microcomputer 30.
FIG. 4 shows a configuration in which this is realized by modifying the circuit shown in FIG. 2.

Soft pulse 5H (T7) is microcomputer 30
This occurs only when the T18 terminal of the
The charges held in the second charge storage unit GAn continue to be held in the second charge storage unit GΔn until a pulse force is applied to the T7 terminal. Note that the microcomputer 30 detects the inversion of the TI4 signal, and after there is enough room for data acquisition, the
Set r18T18 terminal gh.

In this way, it is possible to set the time point at which the output of the image signal from the CCD register CAn starts during the high brightness time.

Next, an example will be described in which the one-dimensional image sensor 1 having the second charge storage section GΔn shown in FIG. 1 is applied to a multi-point focus detection system.

FIG. 6 shows the optical configuration of the single-lens reflex multi-point focus detection system. 21 is the objective lens of the camera, 22 is the main mirror, 2
3 is a total reflection submirror, 24 is a field mask, 25 is a condenser lens, 26 is a total reflection mirror, 27 is a pair of re-imaging lenses, and 28 is an autofocus sensor.

As shown in FIG. 7, the field mask 24 has four transparent parts 24-1.24-2.24-3.24 arranged in 2 rows and 2 columns.
-4, and limits the optical image to one zone. The light confined to four zones by the field mask 24 passes through the condenser lens 25 and is directed to the re-imaging lens 27 by the total reflection mirror 26.
be divided into a reference part and a reference part for four viewing zones. Then, the light from the zone base C (portion and reference portion) is transferred onto the automatic focus sensor 28 at the reference portions PAL 1 ′, PAL 2 ′,
PAL3', PAL51', reference part PARI', P
Focus detection is performed by forming images in combination with AR2', PAR3', and 1) A R4', and determining the image interval for each zone. Here, it is necessary to obtain an output at an appropriate level for each zone and perform focus detection calculations when the difference in average luminance between the zones is large. To achieve this with a single one-dimensional image sensor, it is necessary to control the integration time of the sensor and the gain of the subsequent amplifier that amplifies the sensor output differently for each zone to obtain the output. . Therefore, we developed the 8th sensor to realize this.
The drive circuit is shown in FIG.

First, the API dimensional sensor will be explained. In FIG. 8, P A L n is a photoelectric conversion pixel array for the reference portion P A L n' of each zone 24-1 to 24-4, and P A R'
n is a photoelectric conversion pixel array for the reference part PARn' of each zone 24-1 to 24-4, M P n is a monitor photodiode for each zone, F A Li, FA Ri (i
=1 to 4) are the floating gates and charge storage element arrays corresponding to the pixels of each zone base section and reference section, S
HI -S +-14 is the respective first soft gate of each zone, GALi is the second charge storage section, 5HGI
, 5HG2 is the second noft game that covers all pixels - 1.
rtg is a CCD register, and one end thereof is provided with an O5 output stage. Each zone's monitor photodiode is connected to a different output stage, and each zone's monitor output 1 and guiode output ΔGCOS I to AGCO6
It is output as 4. Furthermore, a base Q and 71 voltage generation section is provided (1 and outputted from the DOS terminal as a reference voltage for OS and AGCO9n. Each photoelectric conversion pixel column PALi, PA
Is the shaded area Q provided on the output stage side of Ri the dark output? +li
The normal drawing pixel is shielded from light by the mimask and consists of several pixels.

The above-mentioned components are arranged as an integrated circuit on a single substrate as shown in the figure. photoelectric conversion pixel array PALi,
PARi (i = 1 to 4) is the photoelectric conversion pixel shown in Fig. 1 arranged in horizontal rows, and the correspondence in Fig. 1 is as follows: It has the same configuration as the constituent elements FAm and GAm.

Next, the configuration and operation of the drive circuit shown in FIG. 9 will be explained. The drive circuit shown in FIG. 9 has the same basic configuration as the circuit shown in FIG. 13, but the analog signal processing circuit 20 and brightness detection circuit 40 are changed. The monitor output AGCO 9n charged to the reference voltage by the ICG drops in proportion to the average brightness of each zone 24-1 to 24-4.

Here, the monitor output changes from the zone where the predetermined voltage ■4・R4 has dropped to Tn4 (T14.T24.Ta2, T
44) The terminal output is inverted and becomes High, and I
Signal SH that was inverted at the falling edge of CG (T17)
n becomes Low, and the integration of that zone is completed (SH
For convenience, n also represents the signal applied to the first shift gate SHn). Therefore, the charges generated in the photoelectric conversion unit PALiSPARi are transferred to the charge storage element array G.
It does not flow into ALnSGARn, and the charge storage element arrays GALn and GARn maintain the charge at the end of integration. If the integration is completed for all zones before the specified time, T
All n4 signals become high and AND gate ANIO
The output T20 of is inverted to High, thereby notifying the microcomputer 30 that the integration of all C/ is completed.

Appropriate charges are stored in the charge storage units GALn and GARn as image information of each zone. Upon detection of this T20 signal, the microcomputer 30 sets the T18 signal high to sequentially set the two D flip-flops connected in series based on the q clock, thereby adjusting the phase of the transfer lock.
, set the signal to 11ight, then set the second S I-
Turn on the 1-gate SHG+ and 5l-IO2 to transfer the charges of all pixels in the charge storage units GALl, GAL2, GARI, and GAR2 to the CCD renostar Fzg in parallel. Thereafter, pixel outputs are sequentially output from the O5 terminal according to the transfer lock φ2. On the other hand, if the T20 signal is still not detected after a predetermined period of time has elapsed from the start of integration,
The microcomputer 30 forces the T18 signal to I(
By setting SHn corresponding to the pickling method undetermined zone
is set to Low via the NOR gate 4n, and the integration is forcibly completed. In addition, when the TI8 signal becomes High, the two D flip-flops connected in series are set sequentially by the reference clock, thereby adjusting the phase of the transfer lock, and then the charge storage unit GAL1
．． GAL2゜GARI, the charge of all pixels of GAR2 is CO
The parallel transfer to D register Rg is the same as in the previous case.

Also, the first 5l-1 game) S Hnh<ON to OF
The output S of the NOR gate N0R41 at the moment it is reversed to F.
The monitor output level is stored in flip-flops DF3 to DF5 by the inverted signal of H1 to Low, and the gain of each zone is memorized. This gain is utilized for dark detection zones where no inversion of the SHn signal occurs even after a predetermined period of time has elapsed.

After the SH pulse is generated, the AP microcomputer 30 receives a completion signal from an analog-to-digital converter (hereinafter referred to as ADC), determines the pixel position of the output data, and selects the first pixel of each block. Upon arrival, the zone signal is output to the analog processing circuit 20, the multiplexer MX is switched, and the gain of the f amplifier stored in memory for each zone is supplied to the AGC amplifier of the circuit 26. In addition, the output of the dark output correction pixel Q of the first few pixels of each block is sampled and held in circuit 2.1 by outputting the sample designation pulse TI5. By taking the difference between the two, only the optical output of these outputs is extracted, used as image information for each pixel, converted into digital data by an ADC, and manually inputted into the AP microcombuque 30. T16 when inputting the output of each block is completed.
A sample reset signal is output from the terminal to prepare for sample and hold of the output of the dark output correction pixel Q of the next block to be output.

In this way, each block 24-1 to 24-4 accumulates charge in an appropriate integration time determined by the average brightness of each block, and further performs gain control based on the average brightness of each block. An image signal of an appropriate level can also be obtained for the block, regardless of its average brightness.

[Effects of the Invention] As described in detail above, the present invention integrates the output '1' of the photoelectric conversion element of a plurality of pixels by the first accumulation: 1≦ and the second accumulation part which receives this accumulated charge. and a monitor accumulation section that accumulates the output charge of the monitor light receiving section, and when the output of the monitor accumulation section reaches a predetermined value, the integration in the first accumulation section is completed, The charge is transferred to the second storage section, stored in the second storage section, and then output to the subsequent soft register. There is no need for clock synchronization, and there is no longer a delay in the completion of integration.

Therefore, even for a high-luminance measurement target, charge integration does not become excessive, and accurate image information can be obtained.

[Brief explanation of drawings]

Figure m1 is a block diagram showing one embodiment of the C, CDI dimensional image sensor of the present invention, and Figures 2 to 4 are
A detailed circuit diagram of the gate circuit used in the embodiment shown in the figure, FIGS. 5(a) and (b) are time charts showing the operation of the main parts of the circuit in FIG. 1, and FIG. 6 is an example of the embodiment shown in FIG. Fig. 7 is a perspective view of the main parts of Fig. 6, and Fig. 8 is a front view showing the configuration of the integrated circuit of the image sensor used in the application example of Fig. 6. 9 is a circuit diagram showing a circuit used in the application example of FIG. 6, FIG. 1O is a block diagram showing an example of a conventional image sensor, and FIG. The waveform diagrams of FIGS. 12 and 13 are circuit diagrams showing the gate circuit of the circuit of FIG. 10.

Claims (1)

[Claims] (1) A photoelectric conversion section composed of a plurality of pixels, a first accumulation section that accumulates charges from the photoelectric conversion section, and a second accumulation section to which charges from the first accumulation section are transferred in parallel. , a CCD shift register to which charges from the second storage section are transferred in parallel and output charges corresponding to each pixel in series, a monitor light receiving section provided near the photoelectric conversion section, and a monitor light receiving section. It is characterized by comprising a monitoring storage section that accumulates output charge, and a transfer gate that transfers the charge of the first storage section to the second storage section when the output of the monitoring storage section reaches a predetermined value. CCD one-dimensional image sensor.