JPS62169531A - Decoding method for error correcting code - Google Patents

Abstract

PURPOSE:To effectively correct a burst error by performing the correcting processes successively for series of 2-dimensional arrays so as to attain the alternating processes and correcting the series at the other side again after correction of the series at one side in case the correction is impossible for the series at the other side. CONSTITUTION:An address generating circuit 2 produces the address data to read the data on the column and row blocks alternately out of a memory 1 through the column or row block with which the decoding is started. A control circuit 6 produces the control signal to correct again the blocks preceding the block at the other side in case the correction of errors is impossible for the block at the other side after correction of errors of the block at one side when the column and row blocks are corrected alternately. The control signal of the circuit 6 is supplied to the circuit 2. Thus such errors that could not be corrected by a conventional method may sometimes be corrected by this new method. In such a way, correcting capability for burst errors is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of decoding error correction codes such as product codes and cross-interleave codes.

[4 Summary of the Invention] The present invention provides a first series and a second series arranged in mutually different directions in a two-dimensional array of a plurality of symbols of digital data.
In an error correction code decoding method in which a first error correction code and a second error correction code are encoded in each of the sequences, one of the predetermined first sequence and the predetermined second sequence is encoded. First, set the series to be corrected, and then apply correction processing to the series in the two-dimensional array from the set series to the adjacent series so that the first series and second series are processed alternately. During this sequential correction process,
After correction processing of one series, if correction of the other series is impossible, correction processing of the previous series of this other series is performed again, and the number of times of correction processing that is performed again is limited to a predetermined number or less. This makes it possible to improve error correction capability within a predetermined calculation time, and in particular to effectively correct burst errors.

[Conventional technology]

When storing digital data on magneto-optical disks,
Product codes are used to correct errors that occur when writing or reading data.

The product code encodes an error correction code for each column and row of a two-dimensional array (matrix block) of digital data, and a linear code is used as the error correction code.

In the conventional product code decoding method, for example,
As shown in Publication No. 6230, C decoding the error correction code CI in the column direction for all sequences of the code C1.
1 decoding and row direction error correction code C2 decoding is performed as code C2.
C2 decoding is performed alternately on all sequences.

[Problem that the invention seeks to solve]

When correcting burst errors that occur when data is transmitted in a diagonal direction (between diagonals) of a matrix block of a product code, conventional decoding methods calculate the number of repetitions for decoding code C1 and decoding code C2. There was a problem that the error symbol could not be corrected unless it was done multiple times.

Therefore, when the calculation time allocated to decoding one matrix block of a product code is not long enough,
There was a problem where uncorrected error symbols remained.

The above-mentioned problem occurs not only with product codes but also with cross-interleaved codes. In the cross-interleave code, a first error correction code and a second error correction code are encoded for each of two diagonally arranged sequences with different two-dimensional arrays of digital data, and the column direction is the data transmission direction. It is something. As in the past, the first error correction code is decoded for all code sequences, and then the second error correction code is decoded for all code sequences.
A decoding method that performs decoding of error correction codes for all code sequences cannot effectively correct burst errors.

Therefore, an object of the present invention is to provide an error correction code decoding method that can effectively correct burst errors.

Means for Solving Problem c] The present invention provides a first series C1+, C1t, . . . First for each
A second sequence C2, C2□, . In a method for decoding an error correction code encoded with a code C2, a step of setting one of a predetermined first sequence C1n and a predetermined second sequence C2 as a sequence to be subjected to correction processing first; sequentially performing correction processing on the two-dimensional array of sequences from the set sequence to adjacent sequences so that the first sequence and the second sequence are processed alternately;
During this sequential correction processing, after correction processing of one of the first series and second series, if correction of the other series is impossible, correction processing of the previous series of this other series. This is an error correction code decoding method characterized by comprising the steps of performing the correction process again, and limiting the number of times the correction process is performed again to a predetermined number or less.

C action] In the case of a product code in which an error correction code C1 is encoded in the column direction of a two-dimensional array (matrix block) of multiple symbols of digital data, and an error correction code C2 is encoded in the row direction, The column blocks CI+, C1g, . . . CIN, which are the series in the column direction, and the row blocks C2+, C2t, . When transmitting data in a diagonal direction of a matrix block, one column block or one row block contains two or more error symbols, which is more than the correctable error symbol, for example, one error symbol, due to burst errors. An error pattern occurs. In the case of such an error pattern, the number of error symbols is small and the error symbols are processed one after another by alternately processing the column blocks and row blocks for each adjacent block from the column block or row block where the error can be corrected. is corrected. Therefore, when decoding processing is performed within a predetermined time, error correction capability can be substantially improved.

Also, when one series is corrected, by re-performing the previous correction process for the other series, the previous process
Sometimes it becomes possible to correct an error that could not be corrected. This makes it possible to further improve the ability to correct burst errors.

〔Example〕

An embodiment in which the present invention is applied to a product code will be described below with reference to the drawings. FIG. 1 shows a decoding device for implementing the decoding method according to the invention.

In FIG. 1, a memory (RAM) indicated by 1 stores digital data and check symbols constituting a matrix block of a product code.

The data stored in memory 1 is stored on a magneto-optical disk (
This is one sector of data reproduced from (not shown).

The write address and read address of memory 1 are:
Generated by address generation circuit 2. The data of one column block or row block read from memory 1 is input/output IJ? It is supplied to the I11 circuit 3.

The input/output control circuit 3 includes a decoder (C1 decoder) 4 for error correction code C1 in the column direction and an error correction code C2 in the row direction.
decoder (C2 decoder) 5 is connected. The address generation circuit 2 and the input/output control circuit 3 are controlled by a control fml signal generated from the control circuit 6. Control circuit 6
When the address generation circuit 2 generates address data for reading column block data to the memory 1, the memory 1 and the C1 decoder 4 are connected, and the read column block data is transferred to the C1 decoder 4. The data of the column block is supplied to a decoder 4, a correction process is performed on this column block, and the data of the corrected column block is written to the memory 1.

On the other hand, when the address generation circuit 2 generates address data for reading the row block data to the memory 1, the memory 1 and the C2 decoder 5 are connected, and the read row block data is The data is supplied to the C2 decoder 5, a correction process is performed on this row block, and the data of the corrected row block is written into the memory 1.

The address generation circuit 2 generates address data such that column block data and row block data are alternately read from the memory 1 from the column block or row block at which decoding is started. The start block for starting decoding is the control circuit 6.
Set by.

In this embodiment, one of the predetermined column block C1 or the predetermined row block C2,1 is set to the start program. Further, the control circuit 6 controls step a for changing the column block, step b for changing the row block, and the maximum value α of the number of repetitions of the correction process for one sequence.
β is initialized.

Further, when correcting column blocks and row blocks alternately, if error correction of the other block is impossible after error correction of one block, the control circuit 6 corrects the previous block of the other block. A control signal is generated to perform the correction process again, and this control signal is supplied to the address generation circuit 2. Therefore, a determination signal indicating whether correction is possible is supplied from the C1 decoder 4 and the C2 decoder 5 to the control 71 circuit 6. The number of times this correction process is performed again is limited to a predetermined number α and β or less in order to prevent the decoding time from increasing. α and β are
For example, it is set to 2.

FIG. 2 shows the structure of an example of a product code to which the present invention can be applied. As shown in FIG. 2, a coding unit is formed by a matrix block consisting of (M·N) symbols arranged in a matrix of M rows and N columns. An error correction code is encoded for each column block of ((M-p)x(N-Q)) digital data symbols (for example, one symbol is one byte) and for each row block thereof. In the case of a storage device using a magneto-optical disk, (
MP=N-Q=23), and one matrix block has a size of 529 bytes corresponding to one sector. Of these 529 bytes, 5128 bytes are digital data, and the other 17 bytes are additional data such as addresses, identification codes, and CRC codes.

Each of the N column blocks C11, C1g, . . . CI N is a code sequence of the error correction code C1 and includes P check symbols. Similarly, each of the row blocks C2+, C2□, . . . C2M of MIIIU is a code sequence of the error correction code C2, and includes Q check symbols. That is, Q containing the column block CIN
The P row blocks including the row block C2M have the check symbols of code C2 encoded with code C1, and the check symbols of code C1 are encoded with code C2. It is something. Linear codes are normally used as the error correction codes CI and C2. For example, a Reed-Solomon code capable of correcting a one-symbol error is used as the error correction codes C1 and C2, and each column block and row block includes (P=Q=2) check symbols. Furthermore, since the check symbols in the portion where the P row blocks and the Q column blocks overlap are linear codes, the check symbols match between the row blocks and the column blocks.

As shown by broken lines in FIG. 2, data is transmitted in the order of symbols located diagonally (in the diagonal direction) of the matrix block. Transmitting data in a diagonal direction different from the direction of the error correction code CI and C2 series is as follows.
This is to disperse burst errors that occur during transmission into random errors, and to prevent error correction from becoming impossible with the error correction codes CI and C2.

The C1 decoder 4 and the C2 decoder 5 decode the product code shown in FIG. Memory 1 stores all the data of the matrix block reproduced from the magneto-optical disk,
Data is read out from memory 1 for each column block or row block forming a code sequence, and the Reed-Solomon code is decoded. When the column blocks C1, C1□, . . . C1, l of digital data are read out from the memory 1, the input/output control circuit 3
The decoders 4 are connected. Similarly, row blocks C2, C2t, . . . C2 of digital data from memory 1
>+ is read, the input/output control circuit 3 connects the memory l and the C2 decoder 5.

The Reed-Solomon code decoding process includes the steps of obtaining two syndromes S0 and S by multiplying the parity check matrix and the symbol of each block, and checking the magnitude of the error from the syndromes S0 and S1. and correcting the error when one symbol error occurs.

Conventionally, all column blocks C11+Cl2.・・・
- Correction processing is performed by alternately repeating C1 decoding for error correction regarding CIN and C2 decoding for error correction for all row blocks CL, C2t, . . . C2, 4. This invention has a correction capability equivalent to that of conventional correction processing, and is a method that can further shorten decoding time. The code sequence of a column block and the code sequence of a row block are alternately corrected for each program. It is something to do. Third
The figure is a flowchart of a correction processing method according to an embodiment of the present invention.

In FIG. 3, Y represents affirmation and N represents negation. Further, each of a and b is a change step of a column block and a row block, and each of N1 and N2 is a step of changing a column block and a row block. α and β are each a threshold value that limits the number of times this process is performed. Therefore, if (Nl≧α) or (N2
≧β), the correction process for the previous block is not performed. Furthermore, Fl and F2 are flags that are set to G (eg, 0'') when each of the column block and row block can be corrected, and set to NG (eg, ``1'') when they cannot be corrected.

Initial settings are made at the beginning of the decoding process (step ■).

For example, each of step a for changing the column block and step b for changing the row block is set to (a=b=1),
Threshold values α and β are set as (α-β=2), start blocks n and m are set as (n=1) (m-1), the counter is reset, and both count values Nl and N2 are set. It is considered O. Then, these symbols of the start program C111, C2, and I are read out from the memory 1 (step 2).

Next, it is checked from the syndrome whether the column block C1,1, which is the sequence at which decoding is started, can be corrected (step 2). If it is possible to correct the column block CI, i.e.
If there is no error symbol in column block C17 or if there is one symbol error, the process moves to correction processing for column block CI (step 2). After the correction processing of the column block C1, the flag F1 regarding the column block is set to G (step 2). Next, flag F2 regarding the row block
Step ■) to check whether or not is G.

When (F2=G), the count 4MN2 is set to 0 (Step 7).

Next, it is checked from the syndrome whether or not the row program C2 can be corrected (step 2). Row block C2
, if it is possible to correct the row block C2, the process moves to the correction process for the row block C2 (step 2). After the correction processing of row block 02F, the flag F2 regarding the row block is set to G (step [phase]). Next, the flag F1 regarding the column block
It is checked whether or not is G (step 0>. (F1=G
), the count value N1 is set to O (step @),
.

As mentioned above, by steps
, and row block C2, it is checked in step 0 whether the correction has been completed, and if so, the decoding is completed. In step 0, if the correction is not completed, the block numbers (n and m) are respectively (=,
a and ↑b) (step @l), and the processes of steps ◎ to ◎ are repeated. Therefore, L C1n→C2, -C
The sequence of code C1 and the sequence of code C2 are processed alternately for each block in the order of ln+1-〇2, , H...].

Further, in step (2), if the column block C1 cannot be corrected, the flag F1 is set to NG (step O), and the process shifts to the correction process for the row block C2. In step ■, if it is impossible to correct the row block C2, , flag F2 is set to NG (step @),
Move to step ■.

In the correction processing of the column block C1fi in steps ■ to ■, after the correction processing of the column block C1, (F2=
G), in step ■, (N2≧β
) is checked to see if it holds true. If this relationship holds true, proceed to step ■, while (F2 β)
In the case of (m=zn-b, N2=N2+1>) (step 7 step 0).
After correction of 111, when flag F2 is NG,
This is a process for processing the previous row block C2-b again. The count of the counter (ifjN2 indicates the number of times this process is repeated).

In the correction processing of row block C2, in steps ① to 0, processing to return to column blocks C1, . . . - is also performed.

In other words, after the step [phase] in which the row block C2 is corrected (step ■) and the flag F2 is set to G,
The force is checked four times to see if the flag F1 is G (step O).

In the case of (Fl≠G), (N1 × α) (step 0)
In the case of (n=n-2a, N1=N1 +1) (step @l). This step [phase] is a process for reprocessing the previous column block C2, when the flag F1 is NG after the row block C2 has been corrected. For counter counting? jN1 indicates the number of times this process is performed again.

The error correction according to the present invention in which the above-mentioned code CI series and code C2 series are processed alternately for each block is as follows:
This is effective for correcting error patterns as shown in the figure.

For simplicity, FIG. 4 shows a product code in which the matrix block has 7 rows and 7 columns, and symbols indicated by X represent error symbols. - As a simple correction process, all the decoding (C1 decoding) of the column blocks, which are the code C1 series that can correct one symbol error, and the row blocks, which are the code C2 series, which can correct one symbol error, are performed. All decryption (C2
(decoding) is performed once each, the six error symbols surrounded by broken lines are not corrected in either case of (C1 decoding - C2 decoding) or (C2 decoding - C1 decoding).

In this embodiment, the correction process is performed starting from column block cL. Column block C11 cannot be corrected because it contains two error symbols, and step (■-
(2-@), then correction processing is performed on the row block C2. In FIG. 4, the numbers added to each block represent the order in which they are corrected. Row block cL
can be corrected, so the step (■−■−[phase]
), one error symbol is corrected. In step ■, (F 1 =NG) and (NIT
-0), it moves to step [phase] and (n=1
-2=-1) (N1=1). Next, in step @, (n=O) (m=2). Here, CI
. The column block is column block C1? means,
Column block CI is corrected (step ■).

Next, since (F2=G), the process moves to correction processing for the row block C2t. Since the row block c22 cannot be corrected, (F2=NG) (step ■) is determined, and the process moves on to the correction process for the column block Cll. This column block C1
+ has become one error symbol by the correction processing of row block C21, so it can be corrected.

Therefore, a correction is made to column block C1l.

(F2=NG) (N2=0), so (mss3-
1=2), and the correction process for row block C2 is performed again. Since row block C2□ can be corrected, the error symbol is corrected and (F2=G).

Thereafter, all error symbols can be corrected by performing correction processing on the column blocks and row blocks alternately in the order of numbers shown in FIG.

FIG. 5 shows another example of an error pattern for which error correction according to the present invention is effective. Similarly to FIG. 4, x indicates an error symbol. Symbols without an X and ○ mean correct symbols.

Column blocks and row blocks are processed alternately in the numerical order shown in FIG. Blocks C1 and C2+
Since error correction is impossible for both, (F1=F2
=NG), and the process moves to column block C12. Since error correction is not possible for this column block CL, next,
Row block C22 is processed. This row block C2,
contains one error symbol, so error correction is possible and (n=0). By going through step [phase], <n=1) is established, and the correction process for column block CI+ is performed again. As a result of the above-described correction processing for row block C2□, column block CI+ is a block containing one error symbol, so all error symbols in column block C1 are corrected.

Thereafter, column blocks and row blocks are processed alternately in the order shown in FIG. 5, and all error symbols are corrected.

As is clear from the above description, more error symbols can be corrected with approximately the same number of corrections as in the conventional decoding method, and the limited correction processing time can be used effectively. The error patterns shown in FIGS. 4 and 5 are likely to occur due to burst errors when data is transmitted in a diagonal direction of a matrix block, and the correction processing of this embodiment is extremely effective in correcting burst errors. be.

Of course, the present invention can be applied not only to product codes but also to those in which an error correction code is encoded in a diagonal direction of a matrix bronch. Further, as the error correction code, a code other than the Reed-Solomon code can be used. For example, when one symbol is one bit, a BCH code can be used.

〔Effect of the invention〕

According to this invention, due to a burst error during transmission, 2
Regarding the sequences of both error correcting codes C1 and C2, an error pattern with many sequences containing multiple error symbols (an error pattern that can be finally corrected by repeating C1 decoding and C2 decoding several times) is calculated. When decoding, the number of steps can be reduced compared to conventional decoding methods, and the decoding time can be shortened.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a route map used to explain the code structure of the embodiment of the invention, and Fig. 3 is a diagram used to explain the correction process of the embodiment of the invention. The flowcharts used, FIGS. 4 and 5, are the lines used to explain the correction processing of an embodiment of the present invention. Explanation of main symbols in the drawings 1: Memory, 2 Near address generation circuit, 3: Input/output control circuit, 4: C1 decoder, 5: C2 decoder, 6:
control circuit. Agent Patent Attorney Tadashi Sugiura Chicho Lock Diagram 1 Figure Area Code Figure 2 Figure 4 Kuu-Nozu Turn 5 7 Kuuichi Pattern Figure 5

Claims (1)

[Scope of Claims] A first error correction code is encoded on each of a first series consisting of a plurality of symbols arranged in a first direction of a two-dimensional array of a plurality of symbols of digital data; A method for decoding an error correction code in which a second sequence of symbols arranged in a second direction of a two-dimensional array is encoded with a second error correction code, comprising: setting one of the series and the predetermined second series as the series to be subjected to correction processing first; and setting the above so that the first series and the second series are processed alternately. The above 2.
Between the step of sequentially performing the correction process of the series of the dimensional array and the correction process performed sequentially, after the error correction process of one of the first series and the second series, the correction of the other series is performed. Error correction characterized by comprising the steps of: performing the correction process again on the previous series of the other series when the correction process is not possible; and limiting the number of times the correction process is performed again to a predetermined number or less. How to decode the code.