JPS62169351A - Dhd type diode - Google Patents
Dhd type diodeInfo
- Publication number
- JPS62169351A JPS62169351A JP61011519A JP1151986A JPS62169351A JP S62169351 A JPS62169351 A JP S62169351A JP 61011519 A JP61011519 A JP 61011519A JP 1151986 A JP1151986 A JP 1151986A JP S62169351 A JPS62169351 A JP S62169351A
- Authority
- JP
- Japan
- Prior art keywords
- bump electrode
- electrode
- bump
- silicon oxide
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 abstract description 14
- 238000007789 sealing Methods 0.000 abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 12
- 239000011521 glass Substances 0.000 abstract description 4
- 238000005452 bending Methods 0.000 abstract description 2
- 229920001721 polyimide Polymers 0.000 abstract description 2
- 239000009719 polyimide resin Substances 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
、産ｉし１利ｊし辷「
本発明は、全高の高いバンプ電極を備えているＤＨＤ型
（ガラス封止型の略）ダイオードに関し、前記バンプ電
極を補強したものである。[Detailed Description of the Invention] The present invention relates to a DHD type (abbreviation for glass sealed type) diode equipped with a bump electrode having a high overall height, and a device in which the bump electrode is reinforced. It is.
上米■肢徂
従来のＤＨＤ型ダイオードの一例を第２図に示すと共に
説明する。An example of a conventional DHD diode is shown in FIG. 2 and explained below.
同図において、符号１は例えばＮ形のシリコンからなる
半導体基板で、その表面側の中央部分にはＰ影領域２が
埋め込まれている。半導体基板１の表面にはシリコン酸
化膜３が被着されていて、Ｐ影領域２の上部が窓開けさ
れている。この窓開は部分つまりＰ影領域２の表面には
、バンプ盛上げ電極層４が被着されていて、バンプ盛上
げ電極層４上には略台形状に膨出するＡｇなどのバンプ
電極５が形成されている。In the figure, reference numeral 1 denotes a semiconductor substrate made of, for example, N-type silicon, and a P shadow region 2 is embedded in the center portion of the front surface thereof. A silicon oxide film 3 is deposited on the surface of the semiconductor substrate 1, and a window is opened in the upper part of the P shadow region 2. A bump build-up electrode layer 4 is deposited on the surface of this window opening, that is, the P shadow area 2, and a bump electrode 5 made of Ag or the like is formed on the bump build-up electrode layer 4, which bulges out in a substantially trapezoidal shape. has been done.
このようなダイオードでは、バンプ電極５の膨出部５ａ
の上面の面積が大きくなるにつれてＣＬ（電荷容量）が
大きくなる。そのため、前記面積を小さくしてＣｔを小
さくしようとすると、バンプ電極５と図外の外部リード
（デュメソト線）との接触状態が悪くなると共に通電時
における熱放散も小さくなって、順方向電圧が大きくな
るという特性劣化を余儀なくされる。In such a diode, the bulge portion 5a of the bump electrode 5
CL (charge capacity) increases as the area of the top surface increases. Therefore, if an attempt is made to reduce Ct by reducing the area, the contact condition between the bump electrode 5 and the external lead (not shown) (Dumesoto wire) will deteriorate, and heat dissipation during energization will also become smaller, resulting in a lower forward voltage. As the size increases, the characteristics deteriorate.
このようなことから、第３図に示すような、全高の高く
かつ断面形状が略逆さ凸形状のバンプ電極６が提案され
ている。図例のハンプ電極６は、バンプ盛上げ電極層４
と同径な比較的細長い柱部６ａと、柱部６ａの上部に連
結した略台形状の膨出部６ｂとからなる。このような構
成のバンプ電極６によると、半導体基板１と膨出部６ｂ
間の距離が柱部６ａの高さ分だけ増し、この間のＣｔを
小さくできる。よって、柱部６ａの長さ分に基づいて膨
出部６ｂの上面の面積を大きくできるので、第２図に例
示したダイオードよりも特性を改善できる。For this reason, a bump electrode 6, as shown in FIG. 3, has been proposed which has a high overall height and a substantially inverted convex cross-sectional shape. The hump electrode 6 in the illustrated example is a bump electrode layer 4
It consists of a relatively elongated column 6a having the same diameter as , and a substantially trapezoidal bulge 6b connected to the upper part of the column 6a. According to the bump electrode 6 having such a configuration, the semiconductor substrate 1 and the bulge portion 6b
The distance between them increases by the height of the pillar portion 6a, and the Ct between them can be reduced. Therefore, since the area of the upper surface of the bulging portion 6b can be increased based on the length of the columnar portion 6a, the characteristics can be improved compared to the diode illustrated in FIG.
Δ口 く１ゞ しよ゛と る口 占
しかしながら、第３図に示すバンブ電極６では、その柱
部６ａが比較的細長いために、シール時においてシール
圧に耐えきれずバンブ電極６が折れ曲がったり、或いは
基板１の一部とともにもげたりすることがある。また、
シール時において混入したシリコン屑などの異物７ （
第３図参照）が、組立後においてバンブ電極６の膨出部
６ｂの下面と半導体基板１との間で立ってショートする
といった異常が発生することもある。However, since the pillar portion 6a of the bump electrode 6 shown in FIG. 3 is relatively long and thin, the bump electrode 6 may not be able to withstand the sealing pressure during sealing and may bend. , or it may peel off along with a part of the substrate 1. Also,
Foreign matter such as silicone debris mixed in during sealing 7 (
(see FIG. 3), an abnormality may occur such as a short circuit occurring between the lower surface of the protruding portion 6b of the bump electrode 6 and the semiconductor substrate 1 after assembly.
本発明はこのような点から創案されたもので、シール時
においてバンブ電極が折損したり基板の一部と共にもげ
たりすることを防止できるＤＨＤ型ダイオードを提供す
ることを目的としている。The present invention was devised from these points, and an object of the present invention is to provide a DHD type diode that can prevent the bump electrode from breaking or peeling off along with a part of the substrate during sealing.
１」 占 −°ｌ−るための一
本発明にがかるＤ１１Ｄ型ダイオードは、断面形状が略
逆さ凸形状のハンプ電極の柱部周辺に当該バンプ電極を
支える絶縁層を備えている。1. A D11D type diode according to the present invention includes an insulating layer supporting the bump electrode around the pillar portion of the bump electrode having a substantially inverted convex cross-sectional shape.
皿
絶縁層によりバンブ電極の柱部および膨出部が支えられ
る。絶縁層によりバンブ電極の膨出部と半導体基板とが
電気的に分離される。The plate insulating layer supports the columnar portion and the bulge portion of the bump electrode. The insulating layer electrically isolates the protruding portion of the bump electrode from the semiconductor substrate.
実見±
以下、図面を参照して本発明の一実施例を詳細に説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.
第１図において、符号１０はＮ形のシリコンからなる半
導体基板を示しており、その表面側の中央位置にはＰ影
領域２０が埋め込まれている。半導体基板１０の表面は
シリコン酸化膜３０で覆われていて、Ｐ影領域２０の上
部が窓開けされている。シリコン酸化膜３０の表面は例
えばポリイミド樹脂やガラスなどの絶縁層４０で覆われ
ていて、シリコン酸化膜３０の窓開は部分のＰ影領域２
０上にはバンブ盛上げ電極層５０が被着されている。バ
ンプ盛上げ電極層５０の上部には断面形状が略逆さ凸形
状のＡ、 ［などからなるバンブ電極６０が形成されて
いる。このバンブ電極６０は、絶縁層４０とシリコン酸
化膜３０の各窓開は部分に位置する比較的細長い柱部６
１と、柱部６１の上端に連結した略台形状の膨出部６２
とからなる。In FIG. 1, reference numeral 10 indicates a semiconductor substrate made of N-type silicon, and a P shadow region 20 is embedded at the center of the front surface thereof. The surface of the semiconductor substrate 10 is covered with a silicon oxide film 30, and the upper part of the P shadow region 20 is opened. The surface of the silicon oxide film 30 is covered with an insulating layer 40 made of, for example, polyimide resin or glass, and the window opening of the silicon oxide film 30 is in the P shadow region 2 of the part.
A bump-raised electrode layer 50 is deposited on top of the bump electrode layer 50 . A bump electrode 60 having a substantially inverted convex cross-sectional shape and having a shape such as A, [, etc.] is formed on the upper part of the bump build-up electrode layer 50. This bump electrode 60 has a relatively elongated pillar portion 6 located at each window opening of the insulating layer 40 and the silicon oxide film 30.
1, and a substantially trapezoidal bulge 62 connected to the upper end of the column 61.
It consists of
このようなバンブ電極６０を備えたダイオードでは、シ
ール時において、バンブ電極６０に対してシール圧が加
わっても、絶縁層４０によって膨出部６２の下面および
柱部６１が支えられるようになっている。結果的にシー
ル時においてバンブ電極６０が折れ曲がったり、基板の
一部とともにもげたりすることが防止される。そして、
絶縁層４０の膜厚を厚く （約１０〜２０μｍが可能）
することでバンブ電極６０の全高を高くできるのでＣｔ
特性を改善できる。In a diode equipped with such a bump electrode 60, even if sealing pressure is applied to the bump electrode 60 during sealing, the lower surface of the bulge 62 and the pillar portion 61 are supported by the insulating layer 40. There is. As a result, the bump electrode 60 is prevented from bending or peeling off along with a portion of the substrate during sealing. and,
Increase the thickness of the insulating layer 40 (approximately 10 to 20 μm is possible)
By doing so, the total height of the bump electrode 60 can be increased, so Ct
Characteristics can be improved.
これに伴い膨出部６２の上面面積を大きくできるから、
外部リード（図示省略しているデュメット線のこと）と
の接触状態が良好となると共に、通電時における熱放散
が向上するので、順方向電圧を小ざくできるといったダ
イオードの特性向上にも貢献できる。Accordingly, the upper surface area of the bulging portion 62 can be increased.
This improves the contact with the external lead (dummet wire, not shown) and improves heat dissipation during energization, which contributes to improving diode characteristics such as reducing forward voltage.
さらに絶縁層４０は、シリコン酸化膜３０と同様にパシ
ベーション膜にもなるので、シール時においてシール内
に混入したシリコン屑などの異物が原因となる半導体基
板１０と膨出部６２間のショートを防止させる役目もす
る。Furthermore, since the insulating layer 40 also serves as a passivation film like the silicon oxide film 30, it prevents short circuits between the semiconductor substrate 10 and the bulge 62 caused by foreign matter such as silicon chips mixed into the seal during sealing. It also serves as a guide.
なお、絶縁層４０は上記実施例のようにシリコン酸化膜
３０の表面全面に被着する必要もなく、例えばバンブ電
極６０の柱部６１の周囲に膨出部６２の直径よりも若干
大きく形成するだけでも上記実施例と略同等の効果は期
待できる。It should be noted that the insulating layer 40 does not need to be deposited on the entire surface of the silicon oxide film 30 as in the above embodiment, but may be formed, for example, around the columnar part 61 of the bump electrode 60 to be slightly larger in diameter than the bulging part 62. Even with this alone, substantially the same effect as the above embodiment can be expected.
発皿辺盈１
本発明によれば、シール時においてシール圧がバンブ電
極に加わっても該バンブ電極の柱部および膨出部を絶縁
層によって支えているので、バンブ電極が折れ曲がった
り、基板の一部とともにもげたりするという従来の不具
合を防止できる。しかも、絶縁層の膜厚を変えることに
よりバンブ電極の高さ設定に自由度が増すので、従来例
で説明した全高の高いハンプ電極よりもＣｔの特性向上
や外部リードとの接触面積増大などの実現が容易である
。According to the present invention, even if sealing pressure is applied to the bump electrode during sealing, the pillar portion and the bulge portion of the bump electrode are supported by the insulating layer, so that the bump electrode may be bent or the substrate may be damaged. This can prevent the conventional problem of peeling off along with some parts. Moreover, by changing the thickness of the insulating layer, the degree of freedom in setting the height of the bump electrode increases, so it is possible to improve Ct characteristics and increase the contact area with external leads compared to the hump electrode with a high overall height as explained in the conventional example. Easy to implement.
さらに、絶縁層はシリコン酸化膜と同様にパシベーショ
ン効果があるため、パシベーションがシリコン酸化膜と
で２重構造になり、またＰＮ接合までの沿面距離が増す
ことから、シールガラスに含まれる汚染源に起因する素
子の特性劣化を防ぐことができる。Furthermore, since the insulating layer has a passivation effect similar to the silicon oxide film, the passivation becomes a double structure with the silicon oxide film, and the creepage distance to the PN junction increases, resulting in contamination sources contained in the seal glass. It is possible to prevent characteristic deterioration of the device.
第１図は本発明の一実施例であるＤＨＤ型ダイオードの
縦断面図、第２図は従来のＤＨＤ型ダイオードの縦断面
図、第３図は従来の他のＤＨＤ型ダイオードの縦断面図
である。
４０・・・絶縁層
６０・・・バンプ電極
６１・・・柱部。
特許出願人 ローム株式会社
代理人 弁理士 大 西 孝 治
第１図FIG. 1 is a vertical cross-sectional view of a DHD diode that is an embodiment of the present invention, FIG. 2 is a vertical cross-sectional view of a conventional DHD diode, and FIG. 3 is a vertical cross-sectional view of another conventional DHD diode. be. 40... Insulating layer 60... Bump electrode 61... Pillar portion. Patent Applicant: ROHM Co., Ltd. Agent, Patent Attorney: Takaharu Ohnishi Figure 1
Claims (1)
ンプ電極の柱部周辺に当該バンプ電極を支えるように形
成された絶縁層とを備えていることを特徴とするＤＨＤ
型ダイオード。(1) A DHD comprising a bump electrode having a substantially inverted convex cross-sectional shape, and an insulating layer formed around a columnar portion of the bump electrode to support the bump electrode.
type diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61011519A JPS62169351A (en) | 1986-01-21 | 1986-01-21 | Dhd type diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61011519A JPS62169351A (en) | 1986-01-21 | 1986-01-21 | Dhd type diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62169351A true JPS62169351A (en) | 1987-07-25 |
Family
ID=11780238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61011519A Pending JPS62169351A (en) | 1986-01-21 | 1986-01-21 | Dhd type diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62169351A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020077723A (en) * | 2018-11-07 | 2020-05-21 | ローム株式会社 | Semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4830790A (en) * | 1971-08-23 | 1973-04-23 | ||
| JPS57139942A (en) * | 1981-02-23 | 1982-08-30 | Seiko Instr & Electronics Ltd | Manufacture of semiconductor device |
-
1986
- 1986-01-21 JP JP61011519A patent/JPS62169351A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4830790A (en) * | 1971-08-23 | 1973-04-23 | ||
| JPS57139942A (en) * | 1981-02-23 | 1982-08-30 | Seiko Instr & Electronics Ltd | Manufacture of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020077723A (en) * | 2018-11-07 | 2020-05-21 | ローム株式会社 | Semiconductor device |
| US11842971B2 (en) | 2018-11-07 | 2023-12-12 | Rohm Co., Ltd. | Semiconductor device with electrodes having a columnar portion |
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