JPS62168479A - Image reproducing device - Google Patents

Abstract

PURPOSE:To suppress an image shift of a motion part between fields by supplying alternately to a display part, a video signal of the preceding one field which has been brought to an interpolation processing between the fields, and a video signal of the succeeding one field which has been held in a memory. CONSTITUTION:Between memories 13, 21 and 23, and multiplexers 19, 24 and 25, interpolating circuits 26, 28 and 30 for Y data, R-Y data, and B-Y data, and averaging circuits 27, 29 and 31 are provided, respectively. At the time f a static reproduction, optional continuous video signals of two fields which have been inputted to an input terminal 1 are held in memories 17, 20 and 22 and the memories 18, 21 and a23. In this state, by the interpolating circuit and the averaging circuit, the video signal of the preceding one field is brought to an interpolation processing between the fields by using the video signal of the succeeding one field, and this video signal which has been brought to the interpolation processing, and the video signal of the succeeding one field are fetched alternately from the multiplexers 19, 24 and 25 at every one field and applied to a display part.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention provides a method for static reproduction of l-frame images by alternately supplying inputted two consecutive fields of video signals to a display unit for each field. The present invention relates to an image playback device with a still playback function.

[Conventional technology]

2. Description of the Related Art Conventionally, a television receiver, which is an example of an image reproducing apparatus, has a digital system that digitizes and processes a received analog video signal.

Digital television receivers are usually called digital televisions, and are published by Nikkei McGraw-Hill, a magazine published by Nikkei McGraw-Hill.
On page 223 of the November 23, 1988 issue of "Nikkei Electronics", there is a description of a West German ITT digital television constructed as shown in FIG.

In FIG. 6, fi+ is a video signal input terminal into which the color video signal (composite video signal) output from the intermediate frequency amplification section is input, and 121 is a digital converter (hereinafter referred to as digital) connected to the input terminal ill. The conversion is referred to as A/D conversion), (3) is connected to the A/D converter (2) and the luminance signal below C is referred to as Y), (4
) is the color signal filter (
(hereinafter the color signal is referred to as C), (5) is the C filter (4)
The color decoder (6) is connected to the Y filter (3
) 2 and a color decoder (6).

(7), (a), (9) are matrix circuits (6
] three analog converters (hereinafter analog conversion is referred to as D/A conversion), αQ, fll+,
++21 is the three amplifiers connected to the D/A converter (7), (8), and (9), respectively, and ++31 is each amplifier α0
．． (Color picture tube connected to Il+, +121 (
(hereinafter referred to as CRT) and constitutes a display section.

The video signal of the input terminal il+ is 1 in 2 fields.
It consists of an interlaced video signal in which a frame is formed, and the video signal at the input terminal +11 is sent to the A/D converter 121.
The video signal is converted into digital by the A/D converter (21) and a digital video signal is output to the filter f31, +41.

Furthermore, the Y component of the video signal is removed by the Y filter (3), and digital data of the Y component, that is, Y data, is output from the filter (3) to the matrix circuit (6).

Further, the C filter (4) extracts the C component of the digital video signal, and the filter (4) outputs digital data of the C component, that is, C data, to the color decoder (5). Then, the color decoder (5) converts the input g, f+ C data into two types of color difference signal data, namely RY.

The R-Y and B-Y data are converted into B-Y data, and the R-Y and B-Y data are input to a color decoder (5). 2. R9B is red,
A blue primary color signal is shown, R-Y and B-Y are red, and color difference signals between the back primary color signal and Y are shown.

Roughly speaking, the matrix circuit (6) performs madrisk processing on the input Y data 2 and R-Y, B-Y data,
Three primary color data, that is, R, B data 3 and green primary color signal data, C data, are formed, and the R, G, and B data are output to D/A converters (7) to (9) and 4. .

And the D/A converters (7) to (9) are 3 of JG and B.
The primary color data is converted into analog signals to form three analog primary color signals, and each analog primary color signal is sent to an amplifier αc.
)-(+2)n respectively to the CRT Q31.

Therefore, a reproduction screen of one frame each formed by two consecutive fields of the video signal of the input terminal fl+ is displayed on CR and TO3.

In the case of FIG. 6, separation of Y and C, matrix processing, etc. can be performed digitally, so it can be formed and manufactured using a digital collector circuit.

This simplifies adjustments, etc.

By the way, in the case of Fig. 6, only normal playback can be performed in which the screen of each received l frame is sequentially displayed on the CRT u, but by using field memory, the input terminal f
It is possible to perform static playback of a screen of an arbitrary l frame of video signals of l+, making it possible to form a so-called digital television with a static playback function.

For example, as shown in FIG. 7, between the A/D converter 121 and the filters +31 and +41, there are two memory circles, te, each having a capacity of 1 field, each consisting of a refresh memory.
51 in series, and a multiplexer !161 that selectively outputs the data held in memories +141 and t+m to filters (31 and +41), and under the control of a playback control section (not shown), during normal playback, the memo IJ1141 ,
+151 is refreshed every field, and the multiplexer (memo +61! J Q41,
(151 is controlled to selectively output one of the retained data, and during static playback, the memory 'J++41, (1ω refresh is prohibited and the multiplexer t1
By controlling the memo IJ++41, (151) to alternately select and output each field of the retained data, a digital television with a still playback function capable of normal playback and still playback is formed.

In other words, during normal playback, memo IJ +141, (
By refreshing the memory f151, digital video signals of one field each delayed by one field are sequentially read from the video signal of the input terminal +11 from the memory 1141 to the multiplexer 161. A digital composite video signal of one field each delayed by two fields from the video signal of f11 is successively outputted from the i1 port. At this time, the multiplexer (lo is the memory 1141).

In order to select one of the retained data in (15) and output it to filters +31 and +41, CRT t+a
+ has memory f+41. [Similar to the case where 151g and multiplexer uG are not provided, each one-frame image is sequentially reproduced and displayed, and normal reproduction is performed.

On the other hand, during static playback, refreshing of the memory t141,051 is prohibited, and the memory 114. Q51, any 1
Two consecutive fields of digital video signals forming a frame are held one field at a time, and the digital video signal of the first field of the two consecutive fields is repeatedly read out from the memo 1JQ51 to the multiplexer 061. The digital video signal of the last one of the two consecutive fields is repeatedly read out from the multiplexer. At this time, the multiplexer (
161 notes alternately for each l field! j +151
．． In order to repeatedly output the data of Qa, the filter +31. +41, the digital video signal of the previous I field and the digital video signal of the next one field are input repeatedly for each field, CRT.
(+g contains the continuous 2 stored in memory α4° (151)
An i-frame playback screen based on a field digital video signal is repeatedly displayed, and static playback is performed.

Further, as shown in FIG. 8, between the Y filter (3) and the matrix circuit (6), there are two memories [+71. +181 series circuit and both memories +
In addition to providing a multiplexer 091 that selectively outputs the held data of 171° (181) to the matrix circuit (6), a color decoder (5) and a matrix circuit (6) are provided.
and a series circuit 3 of the two field memories IJ'E and t231 to which the R-Y data is input, and a series circuit 3 of the two field memories IJ'E and t231 to which the B-Y data is input. and a multiplexer +24 that selectively outputs the data held in the memory ■, +211 to the matrix circuit (6).
12, and a multiplexer ω that selectively outputs the data held in memo 1J12Z, (231) to the matrix circuit (6), and based on the control of the playback control section, each memory Q71.α&, (211 to S and Each multiplexer +
191, (Foundation), (Company) in Figure 7 Memory! 141.
(Even if controlled in the same manner as 151g and multiplexer 00, a digital television with a still playback function that can perform normal playback and still playback is formed.

S, each memory αη1181, 1201-Elf is a memory ++41. Like a51, it consists of a refresh memory with a capacity of one field.

That is, in the case of FIG. 8, the video signal input to the input terminal fi+ is separated into Y data S and R-Y, B-Y data, and Y data 2 and R-Y, B-Y data are separated. (′
n each of two memories 071. a81S and rzoH, (
211, '22, [By inputting to the series circuit of Z31, during normal playback, Memo U +171.1201
．． 122 to the multiplexer (191, !241. side), the Y data 3 of the video signal of each field delayed by the I field, and the R-Y, B-Y data are output, and the memory state, 1211. .1231 to the multiplexer (191, e!41, Y data 2 and R-Y of the video signal of each 1 field delayed by 2 fields)
, B-Y data is output, at this time multiplexer f19), 1241. ff1ffi is 2 each
Memo January 171. fly, 201.121+,
In order to select one of the held data of '2Z, +231 and output it to the multiplex circuit (6), the CR
, T +131, the images of one frame each are sequentially reproduced and displayed, and normal reproduction is not performed.

Also, during static playback, each memory f171. ff81
．． Refreshing of views from m to m is prohibited, and the Y data of two consecutive fields of IS image signals forming any one frame are stored in the memory 171. The R-Y data and B-Y data of the video signal of the two consecutive fields are stored in the memories 121+ and n, respectively.
+231 and 4 each hold 1 field, and each multiplexer (191, +241, 2 each on the outside)
Memo January 171. ff81. '201. (2
In order to alternately select and output 1+, 10%, and 10% data for each l field, the matrix circuit (6)
Y data 8 and R, -Y, B- of the field video signal
Y data and Y data 8 of the video signal of the next 1 field
and R, -Y, B-Y data are input 2n alternately for each field, and one frame is reproduced based on the continuous two-field video signal forming any one frame on the CRT ff3, and the field is displayed repeatedly. , static playback is performed.

[Problem that the invention seeks to solve]

By the way, when a frame image formed by two consecutive fields of video signals is a moving image, if there is a moving part between fields, image blurring occurs in the moving part.

In the case of digital televisions with a static playback function shown in Figures 7 and 8, during normal playback, each
Since the image of the frame is played next around 1 and the reproduced image changes sequentially in units of 1 frame, image blurring due to the moving part between the fields is not very noticeable.However, during static playback, CRT Since one frame of image is repeatedly reproduced in Q3 and there is no change in the reproduced image, there is a problem in that image blurring due to the moving part between the fields is noticeable and good still reproduction cannot be performed.

[Means for solving problems]

This invention was made with the above points in mind,
In an image playback device with a still playback function that performs still playback of an image of 1 frame by repeatedly supplying two inputted consecutive fields of video signals to the display unit field by field, the two consecutive fields are memory means for holding a video signal one field at a time;
interpolation processing means for performing inter-field interpolation and processing using video signals of the fields; and interpolation processing means for performing inter-field interpolation and processing using the video signals of the fields, and the video signal of the one field of the light that has been subjected to the inter-field interpolation processing during still playback, and the video signal of the one field of the light that is held in the memory means. The present invention is an image reproducing apparatus characterized by comprising a selection output means for alternately and repeatedly outputting a field video signal and a field video signal for each field.

[Effect]

During static playback, the continuous 2 data stored in the memory means
Among the video signals of the fields, the video signal of the previous field is subjected to inter-field interpolation processing using the video signal of one field of the edge, and the video signal of the previous field subjected to the inter-field interpolation processing is displayed on one display section. Since the signal and the video signal of one field after being stored in the memory means are output repeatedly for each field, the playback screen displayed on the display section is changed by inter-field interpolation processing.
Image blur caused by moving parts between fields is suppressed.
, this is the screen.

〔Example〕

Next, the present invention will be explained in detail with reference to FIGS. 1 to 5 showing embodiments thereof.

3 in Fig. 1, the same symbols as in Fig. 8 indicate the same things, and the differences are the memo IJ +181 and the multiplexer;
191, an interpolation circuit 8 to which the Y data of the memory t18 is input, and an averaging circuit to which the output data of the interpolation circuit and the Y data of the memory fl are input; Between the memory 21) and the multiplexer +241, there is an interpolation circuit 2812 into which the RY data of the memo IJ 1211 is input, and the output data of the interpolation circuit/ball and the RY data of the memory 20) are input manually. An averaging circuit Q3 is provided, and between the memory 1231 and the multiplexer 0, the BY data of the memory/bottom is inputted.
, the interpolation circuit type, the output data of the interpolation circuit calculation, and the memo IJ
Averaging circuit '3 to which 122 B-Y data is input
1).

3. Memory ++71. Bl prisoner, 201 to 1 degree formation of memory means, interpolation circuit 2G, 1281. and averaging circuit t271. +291. The interpolation processing means is formed by C(I+), and the multiplexer (19
) , 1241 , (25() forms the selection output means.

And during static playback, each memo IJ +171, 181
, 1201 to 1201 to prohibit refresh n, and the Y data 3 and R-Y, B-Y data of any two consecutive fields of video signals input to the input terminal fll are stored in two memories n71. t+s+2 and ω, (211, 弼, 17
One field is held for every 3.

That is, the two consecutive fields of video signals are stored in the memory; 171.1+81. without being separated into Y data 2 and R, -Y, BY data.硼~＠ holds one field at a time in the memory means formed by @, and at this time, the memory states 2 and 1,1231 of the second stage 1 contain the Y data 8 of the first field of the two consecutive fields and the general information. -Y, H-
The Y data is held in the previous stage memory (1η and 201.λ2 holds the Y data 2 and I(, -Y, B-Y
Data will be retained.

The Y data 2 and R-Y, B-Y data of the l field ahead of the memory 1181g and 3+1:231 are transferred to the interpolation circuit 261. (281, ■ Soi, entered in Zowa.

By the way, the interpolation circuit (1), W, and +3011 each include a tH delay circuit (DLa) for delaying one horizontal scanning period (hereinafter referred to as IH), an addition circuit (AD), and a division circuit (DV).
a) is configured as shown in FIG.
and (2+1. Y data 2 of 1 field ahead of g3
and I(, -Y', B-Y data are input to the delay circuit (DLalS) and the adder circuit (AD) through the input terminals (il) of the four interpolation circuits m and 281., respectively, and From the delay circuit (DLal to the adder circuit (AD7°),
Y data 2 and R-Y of input terminal (i), B-Y data 4, IH delayed Y data 2 and R-Y, B-
Y data is input.

Then, digital addition data of the data of the input terminal (1) and the data before IH of the data of the input terminal (1) is outputted to the division circuit (DVa), and from the division circuit (DVa) Data obtained by digitally subtracting the level of the digital addition data to 1/2 is output to each averaging circuit n, s, (313) through the output terminal (0) of rm, 1301.

That is, each interpolation circuit '261. ．． 2Fl121301
As shown in Fig. 3, the Y data 2 of input terminal (1)
and R, -Y.

By averaging the B-Y data Sowazoj and the Y data S input before IH and the R-, Y, BY data Sowazoj, the memories (l&2 and e211) are stored.

Y data B and R- of the next field held in the rut
The Y, B-Y data is processed within the Sohazowa field.

2. In Figure 3, the solid line! ,−,,! . , 1PI+
1 is input to the input terminal (凰).
scanning line, 0 mark is each scanning line in-+, in,
pixel point of in++, dashed line) 1. ! n+1' is the scanning line h, the IH scanning line after intra-field interpolation processing that is sequentially output from the output terminal (0) corresponding to NOR+1;
The X mark is the scanning line! 7′,! , +1′ pixel point,
The arrow in the figure is a scanning line! The pixels of each X mark of 2no n+1' are connected to the adjacent two scanning lines Jn-+, jlrl, noise j
)? It is shown that I+s is formed by phasing the data of two pixels at the same vertical position.
The previous one field of Y data 2 and R, -Y, BY data that have been subjected to intra-field interpolation processing by pa, msowazoj are sent to the averaging circuit 1271. @, ! II.Enter each one separately.

and averaging circuit port, e291. e(+1 is the Y data 2 of the previous l field that has been subjected to intra-field interpolation processing, and each of the R, -Y, BY data, and the memory (1η.

・Add and average the Y data 3 of one field and the R-Y, B-Y data after being held in 201.221, and perform the inter-field averaging process. and R-Y, B-Y data, respectively, and Y data S and R-Y, B- of the l field.
The Y data is sent to multiplexers ++9)g and 1241. Output to each saddle.

Therefore, the previous one field of Y data B and R, -Y held in the memory (1813 and ■u, I231)
, B-Y data are processed by the interpolation circuit edge, egg, ■, intra-field interpolation processing, and the averaging circuit 2η, '21Fl, e31
Based on the inter-field averaging process of 1, the memory (1
η2 and QOl.

After inter-field interpolation processing is performed using one field of Y data and R-Y, B-Y data held in 1221, the multiplexer (+91:Fi,!:Bi!241.+25i Sonezoj, The input is interrupted.

That is, interpolation circuit 1261. The interpolation processing means formed by e2J +30Ij and the averaging circuit H, 2L e (I+) separates the data into Y data 3 and R, -Y, B-Y data and stores them in the memory Q81. (211, +231).
1 field of video signal, Y data and R-
Separate and memo into Y and B-Y data! J f+71. ．． 2
1+1,! Inter-field interpolation processing is performed using the one-field video signal held in 221, and the previous one-field video signal subjected to inter-field interpolation processing is sent to the selection formed by multiplexers [191E and (24J, !!6+). It is input to the output means.

and multiplexer +191g and 24), ・261
In addition, the averaging circuit 12718 and e29. Interfield interpolation processing from +311 is performed, and the memory f1 is stored together with the Y data of the previous field and R-Y, B-Yf-9.
7) 1 field of Y data 3 and R-Y, B-Y data after being held at 201°2z are input to the multiplexer during static playback. ! 91: Y data 3 and RY of one field after riyohi 241 and 251 have been subjected to field inter-field processing based on the control of a reproduction control unit not shown.

The B-Y data and the Y data 2 and 1 (, -Y, B-Y data) of the next field are alternately and repeatedly output to the matrix circuit (6) every l field.

Therefore, in the C RT Q:l forming the display section,
Three primary color signals based on the previous one field video signal subjected to inter-field interpolation processing, and three primary color signals based on the one field video signal after being stored in the memory means,
The reproduction screen of 1 frames consisting of the previous 1 field subjected to inter-field interpolation processing and the subsequent 1 field stored in the memory means is repeatedly displayed, and static reproduction is performed.

Then, since the video signal of the previous one field is subjected to interfield interpolation processing and supplied to the CRT I+31, the video signal of the previous one field is
Image blur in the moving part between fields is suppressed, and good still playback with little image blur can be performed.

By the way, the interpolation circuit (to) and f2J1311n may be configured as shown in FIG. 4 instead of being configured as shown in FIG. 2.

The difference between FIG. 4 and FIG. 2 is that the data at the input terminal (1) is serially connected to the input terminal (il) for one pixel period.

That is, two l-clock delay circuits (DLb) and (DLc) that delay l-clock period are connected, and a delay circuit (DLa) is connected in series to the output terminal of the delay circuit (DLa).
Two 1-clock delay circuits (DLd) and (DLe) similar to DLb) and (DLc) are connected in series, and the input terminal fi) and the delay circuit (DLbl,
Three multiplication circuits (MPa), (MPb), which multiply the output data of (DLc) by a predetermined constant Sowazo 4,
(MPc), a delay circuit (DLaL(DLd),
Three multiplication circuits (MPd), (MPe), (
MPf) and an adder circuit (ADbl) that adds the output data of each of the multiplier circuits (MPa) to (MPf) and outputs the result to the divider circuit (DVb).

In addition, the multiplier circuit (MPa), (MPc l, (M
Pa), (The constant of MPf 1 is set to the same constant α1, and the multiplier circuit (MPbl.

The constant of (MPe) is set to the same constant α2.

Further, the division circuit (DVb) digitally divides the output data of the addition circuit (ADb) by l/(4α1+mu2).

In the case of Fig. 4, the delay circuit (DLb), (D
The output data of Lc ) becomes pixel data delayed by one pixel from the data of the input terminal (i), and the output data of the delay circuits (DLd) and (DLe ] are delayed by one pixel from the data of the delay circuit (DLa). Since both data are delayed by a pixel, the adder circuit (AD) is loaded with data from adjacent 2H scanning lines, such as scanning line no n-1, noa sowazo n.
The data of three consecutive pixel points will be input,
The data output from the division circuit (DVb) after the intra-field interpolation process is divided vertically by 2 as shown by the arrow in FIG.
and a plurality of data in the horizontal direction, that is, data from six adjacent drawing slips.

8 in FIG. 5, the same symbols as in FIG. 3 indicate the same things.

By the way, the intra-field interpolation processing of the interpolation circuits 2e, 2PJ, 2) generally becomes more efficient as a large number of data in the vertical direction and horizontal direction, that is, a large number of adjacent data, is used. .

Furthermore, the more precisely the intra-field interpolation process is performed, the better the inter-field interpolation process can be performed.

On the other hand, as the number of base data used for intra-field interpolation processing increases, the configuration of the interpolation circuits W, 12δ, +301 becomes more complex.

In the case of Fig. 2, intra-field interpolation processing is performed using only 2 vertically adjacent fields, which greatly simplifies the configuration, and in the case of Fig. Since intra-field interpolation processing is performed using data, more accurate interpolation processing can be performed than in the case of FIG.

8. During normal playback, memory a71. ++8+ E and: 201 to 201 are refreshed, and the multiplexer (+91E and 24+, 12151 is, for example, memory (lη2 and 20).

Since the Y data and R-Y, B-Y data between them are held in the respective selected outputs, the three primary color signals of each field of the video signal of the input terminal fi1 are
The images of one frame each supplied to the next CRT are sequentially reproduced and displayed, but normal reproduction is not performed.

By the way, in the actual gun example, since the video signal input to the input terminal fi+ is a color video signal, Y.

It is necessary to perform C separation, and the memo for Y is IJ fiη,
0812 and interpolation circuit, averaging circuit Q71, memory for C (20) to (2318 and interpolation circuit, +301
．． Averaging circuit 29.

(Although 311 is provided, in the case of a monochrome video signal,
For example, Memo 1JQ71. An example of α812, an interpolation circuit, and an averaging circuit (271) may be provided.

Further, in the above embodiment, the application is applied to a digital television with a still playback function that digitizes and processes input video signals, but the image playback device 2 with various still playback functions that digitize and process Of course, the present invention can be applied to various image reproducing apparatuses with a still reproduction function that perform non-transitory processing.

Furthermore, in the embodiment described above, an example of an interpolation circuit is provided to perform interfield interpolation processing by performing intrafield interpolation processing 2 and interfield averaging processing.

, 2J1301 and averaging circuit 2'71. Although the interpolation processing means is formed using the above-mentioned aq, yi), it goes without saying that the interpolation processing means may have a structure other than that of the embodiment.

[Effects of the Invention] As described above, according to the image reproducing apparatus of the present invention, during static reproduction, the first field of the video signal of two consecutive fields held in the memory stage is converted into the second field of the video signal.
Interfield interpolation processing is performed using the video signal of the field, and the selection output means outputs one field of video signal that has been subjected to the interfield interpolation processing and one field of video signal that has been stored in the memory means. By alternately supplying the signal to the display unit every field, image distortion in the moving portion between fields of two consecutive fields of video signals is suppressed, and good still playback can be performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of an image reproducing device according to the present invention, FIG. 2 is a detailed block diagram of each interpolation circuit in FIG. 1, and FIG. Figure 4 is a block diagram of another example of each interpolation circuit in Figure 1, Figure 5 is a diagram explaining the processing in Figure 4, Figure 6 is a block diagram of a conventional digital television, and Figures 7 and 8 are FIG. 6 is a block diagram that is an improved version of FIG. 6; (1)...Input terminal, (2)...A/D converter, (3
)...Y filter, (4)...C filter, (5)
...color decoder, (6) ...matrix circuit,
(7) to (9)...D/A converter, α stage -f+21
...Amplifier, (131...CTR, Q71.α stage,
(201-Glance...Memory, (191, t241. f
2a... multiplexer, (261, 281, handling...
・Interpolation circuit, 1271.1291. (311...Averaging circuit. Agent Patent Attorney Fuji 1) Ryotabe No. 27

Claims (1)

[Claims] (1) In an image playback device with a still playback function that performs still playback of one frame of image by repeatedly supplying two inputted consecutive fields of video signals to the display unit field by field, the continuous a memory means for holding two fields of video signals one field at a time; and a memory means for holding the previous one field video signal held in the memory means,
interpolation processing means for performing inter-field interpolation processing using the video signal of the next one field; and interpolation processing means for performing inter-field interpolation processing using the video signal of the previous one field that has been subjected to the inter-field interpolation processing during still playback, and the video signal of the previous one field held in the memory means. 1. An image reproducing apparatus comprising: selective output means for alternately and repeatedly outputting a field video signal for each field.