JPS62168412A - Digital filter - Google Patents

Abstract

PURPOSE:To form each tap to the same pattern by providing a selecting circuit for selecting and outputting a signal which has been shifted by one clock each, as a delay output of each tap, in a finite impulse response (FIR) type digital filter which has been constituted by arranging in cascade taps consisting of a delay means, a multiplier and an adder. CONSTITUTION:An output of each stage of a shift register for constituting a delay means DL of each tap 3a-3c is inputted to a multiplier MP through a selecting circuit SL. As for the selecting circuit SL, a selecting signal is inputted to terminals 4a-4c, and the circuit is controlled so that a delay output which has been shifted by one stage each at every tap is selected. As a result, an addition input which has delayed a result of addition of the pre-stage by one stage by a latching circuit, and an output of the multiplier of the tap concerned are matched as to its timing, and can be added by an adder of the tap concerned, as they are.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital filter that digitally processes a sequential signal formed by time-division multiplexing a plurality of types of digital signals.

[Conventional technology]

Conventionally, finite impassion response (Finite Im
A pulseResonance) type filter C (hereinafter referred to as FIR digital filter) has input, output, number of taps, and tap coefficients as X(n), Y(n), N
, H(k) (!: If L fc, output Y(n)
It is shown by the following equation. Note that n, 1( is υ, 1.″:
, . . . N indicates the number of M.

Note that the number of taps indicates the number of delay elements that delay and output the input X(n) by l clocks (unit amount), and the tap coefficient indicates the coefficient by which the output f of each delay element is multiplied.

Y (n) = N As described in the Japanese First Edition), the configuration is basically as shown in Figure @4, where the input X(rl) is connected to N! I! (7) Delay element (DDt 2),...
, (DN), the multipliers (Mo), (Mt), (M2), -, (11
viN) Ni! , Li, input X(n) and output X(n-tLX(n-2) of each delay element (Dl) to (DN)
L・−, X(t) and each tap coefficient H(o), T(
(1), H(2), ..., H(N-1) are digitally multiplied, and each multiplier (MO) to (MN)
The outputs of are added by the adder (A), and the output Y(n)
From the adder (A) to the ilter, each delay element (DI) ~(
Using a shift register for DN), each multiplier (
Using digital multipliers and digital adders for MO) to (MN) and adder (A); thus formed.

By the way, the digital filter receives a sequential signal formed by time-division multiplexing multiple types of digital signals as input X(
n), there is one that performs filter processing on the input X (n).

Then, M types of digital signals are converted into one of the predetermined clock signals.
When filtering sequential signals formed by time division multiplexing for each clock, each delay element (Dl) to (
DN) is configured as shown in Figure @5 using a column circuit of M (M is an integer) shift registers, and in the same figure,
(Rt), (R2), (Ra), . . . , (RM) are M shift registers of each delay element (D]) to (DN), which are connected in series.

A digital filter configured in the same way as the digital filter shown in Figure @5 is also described in, for example, Japanese Patent Laid-Open No. 59-92410.

Since each shift register (R1) to (RM) delays one clock of the sequential signal forming the input X(n) in synchronization with the predetermined clock signal, each delayed
Shift register (R1) at the same position from t) to (DN)
~(RM) outputs l clocks of the digital signal of the same plate, which is shifted by one period, and the output Y(n
) is time division multiplexing 1 of the filtered signal of each digital signal.
It becomes the number.

By the way, when forming the digital filter shown in Figure @5 by integrating it, the adder (A)
As shown in Figure @6, N adders (AIL
It is formed by a series circuit of (Al, . . . , (AN)).

In other words, in the case of diagram @6, it is formed by connecting N@ cascaded taps consisting of one delay element and the multiplier and adder corresponding to the delay element, and in this case, each tap has the same circuit pattern. , it becomes possible to form an integrated digital filter.

By the way, the multiplication in each multiplier (MO) to (MN) and the addition in each adder (A1) to (AN) each require a time of at least several +n sec, and in the case of FIG. The more adders there are, the longer it takes to obtain an output.

When the number of adders (AI) to (AN) connected in series increases based on the number of taps N (D increases S), and the so-called time delay of calculation increases, in the case of a sequential signal with a high clock rate, Output Y(
n) will no longer be obtained.

Therefore, in the case of FIG. 6, when the number of taps N is large, it becomes impossible to filter a sequential signal with a high clock rate.

Therefore, as shown in FIG. 7, each adder (A1) to (AN
), a latch circuit (L) that delays the input signal by one clock and outputs it is inserted, and a multiplier (M
2) Between the ~(MN) and the adders (A2)~(AN), there are 1st stage, 2nd stage,..., N-2th stage of latch circuits (L),
N-tier. Insert each slave circuit and connect each launch circuit (L
) is driven by the same clock signal S as the clock signal that drives the shift registers (R1) to (Rht),
It is possible to solve the above-mentioned inconvenience.

In other words, in the case of diagram @7, for example, the adder at ta (
The output signal of A1) and the output signal of the multiplier (M2) at time ta are added by the adder (A2) at time b one clock later, and by repeating the same operation, the output signal is added after N clocks. At time tN, the output signals of the multipliers (Mo) to (MN) at time t1 are output from the adder (AN), and each tap performs multiplication and addition only once within one clock, and outputs Y. (n), filter processing of sequential signals with a high clock rate is effective even when the number of taps N is large.

[Problem that the invention seeks to solve]

By the way, in the case of FIG. 7, the number of latch circuits (L) increases as the taps are located at later stages. For example, when the number of taps N is large, a significantly large number of latch circuits (L) are provided. This results in a problem that the configuration becomes extremely complicated and that each tap cannot be formed with the same circuit pattern, making integration difficult.

[Means for solving problems]

This invention was made with the above points in mind,
In a digital filter that digitally filters a sequential signal formed by time-division multiplexing a plurality of types of digital signals every clock of a predetermined clock signal, a signal is input to the input terminal of the J sequential signal in synchronization with the clock signal. A plurality of delay means each consisting of a cascade circuit of delay stages corresponding to the number of types of the digital signal that delay one clock of the sequential signal are connected in series, and for each delay means,
a selection circuit that selects and outputs the output signal of a predetermined delay stage shifted by one stage for each delay means; a multiplier that digitally multiplies the output signal of the selection circuit by a predetermined coefficient; An output signal is input to one input terminal, and the adder performs digital addition, and the adder is connected to the output terminal or the other input terminal, and outputs the input signal after delaying it by one clock of the clock signal. Equipped with a latch circuit to
The digital filter is further characterized in that the output terminal of the adding circuit of each delay means is connected to the other input terminal of the adding circuit of the next digital delay means or to the latch circuit.

[Effect]

Therefore, for each delay means, that is, for each tap of the filter, one selection circuit is formed by providing one multiplier, adder, and latch circuit, and each delay means is formed from a cascade circuit of delay stages of digital type. and one of each delay means
The output signals of the delay stages shifted by stages are multiplied by the coefficients at the same timing, and the input signal of the other input terminal of each adder or the output signal of the output terminal is delayed by one clock. is each adder (Ml) in FIG.
(MN), and the filter processing output Y(n) is output from the adder or latch circuit of the final stage delay means, and the sequential signal filter processing is be exposed.

〔Example〕

Next, the present invention will be explained in detail with reference to FIGS. 1 to 3 showing embodiments thereof.

(1 Example) First, Figures @1 and 2 showing Example 1 will be explained.

In FIG. 1, (1) is a signal input terminal, which is a J-bit signal formed by time-division multiplexing M types of J-bit (Jl is an integer) digital signals every clock of a predetermined clock signal. Signals are input sequentially.

(2) is a clock input terminal, into which the predetermined clock signal is input. (3a), (3b), --...
, (31:1) are the first to Nth taps of the filter, and as shown in FIG. 2, the delay means (DL)
, selection circuit (SL), multiplier Bap), adder (AD
) and one latch circuit (LT) are formed using the same circuit pattern.

(4a), (4b), +++, and (4n) are the first to @N selection terminals provided for each tap (3a) to (3n), into which a selection signal for delay stage selection described later is input, respectively. be done. (5a), (5b), -, (5
n) are @1 to N-th coefficient input terminals provided for each of the taps (3a) to (3n), into which tap coefficient signals to be described later are respectively input. (6) is a signal input terminal connected to the latch circuit (LT) of tap (3n).

And delay means (SL) of each tap (3a) to (3n)
are J-pinto M shift registers (SRx), (SR2), (SRs), . . . forming M delay stages.
The two circuits formed by the cascade circuits (SR, y-a) and (SRbt) are connected in series to the input terminal (1).

Further, the output signals of each shift register (SR1) to (SRM) are input to the selection circuit (SL), and the output signal of the selection circuit (SL) is input to one input terminal of the multiplier (MP). The output signal of the multiplier (MP) is input to one input terminal of the adder (AD), and the output signal of the adder (AD) is input to the adder (of the next tap) via the latch circuit (LT). AD) is input to the other input terminal.

Note that only the adder (AD) of the first tap (3a) has its other input terminal grounded.

Further, the output terminal of the adder (AD) of the Nth tap (3n) is connected to the output terminal (6) via a latch circuit (LT).

Furthermore, a multiplier (MP) for each tap (3a) to (3n)
The tap coefficient signals of the input terminals (5a) to (5n) are manually input to the other input terminal of the input terminal.

In addition, each shift register (SR1) to (SRM) of each tap (3a) to (3n) and each latch circuit (LT)
are each driven by a clock signal at the input terminal (2).

To simplify the explanation, M=20. Assume that N=7 and that signals are sequentially formed by time division multiplexing of 20 types of J-bit digital signals.

At this time, each digital signal is NO, 1, NO, 2,...
・.

If the signal is No. 20, then the input terminal (1) will receive a signal from No. 1 to N in synchronization with the clock signal of the input terminal (2).
One clock of the signals of O, 20 is input repeatedly in sequence, and at this time, each shift register (SR1) to (SRM) of each tap (3a) to (3n) is inputted sequentially in synchronization with the clock signal. In order to delay the signal by one clock, each tap (3a
) to (3n) at the same position, for example, the shift register (SR1) of each tap (3a) to C3n)
, each 1 of the same type of digital signal delayed by one period
The clock minutes are output.

On the other hand, the selection circuit (SL) of each tap (3a) to (3n) selects the output of a predetermined shift register shifted by one stage of each delay means (DL) by the selection signal of the input terminal (4a) to (4n). Select and output signals.

For example, the selection circuit (SL) of tap (3a) is
If you select and output the output signal of the shift register, that is, the 13th stage shift register, tap (3b)
The selection circuit (SL) selects and outputs the output signal of the 14th stage shift register, and the selection circuit (SL) of each subsequent tap selects and outputs the output signal of the 15th stage, 16th stage, etc. shift register. Each output signal is selected and outputted, and a selection circuit for the final stage tap, that is, the seventh tap (3n)
SL) selects and outputs the output signal of the 199th shift register, that is, the shift register (S'RM-1).

Then, at time t1, the 1 [period (20
If l clocks are output with a shift of l clocks (clocks), at this time, one clock of the NO, 1 signal is output from the selection circuit (SL) of the tap (3a) to the multiplier (MP), and the multiplier (MP ), the input signal of 1 is digitally multiplied by a predetermined coefficient set by the tap coefficient signal of the input terminal (5a), for example, a coefficient such as the tap coefficient H(0) in Figure @7, Multiplyed data for one clock of NO and 1 signals is output from the multiplier (MP) to the adder (AD).

By the way, since the other input terminal of the adder (AD) of tap (3a) is grounded, the multiplied data of the multiplier (MP) of tap (3a) is sent to the latch circuit (LT) via the adder (MP). is input.

Then, at time t2, one clock after time t1, each tap (
N0 from the 14th stage shift register of 3a) to (3n)
01 signal for one clock is output, and at this time, the output signal of the 14th stage shift register of tap (3b) is t.
At 1 o'clock, one clock of the NO, 1 signal output from the 13th stage shift register of tap (3a), one cycle of one clock, is generated, and this one clock is used as the selection circuit of tap (3b). (SL) to the multiplier (MP).

Furthermore, the multiplier (MP) of the tap (3b) outputs the output signal of the selection circuit (SL), that is, the predetermined coefficient set by the tap coefficient signal of the input terminal (5b), For example, a coefficient such as the tap coefficient H(1) in FIG. Output.

By the way, at time t2, the adder (AD) of tap (3b)
The launch circuit (L) of tap (3a) is connected to the other input terminal of
One clock's worth of multiplication data of the NO, 1 signal from T), that is, one clock's worth of multiplication data of the NO, 1 signal calculated by the tap (3a) at time tx is input.

Therefore, the adder (AD) of tap (3b) is t2
At times, the latch circuit ( LT).

Thereafter, the same operation is repeated, and at time t7, six clocks after time t1, the adder (3n) of the seventh tap (
AD) to the latch circuit (LT), each tap (3a) ~
(3n), the calculation data for 7 clocks of the NO, 1 signal is output, and one clock later, that is, when the NO, 1 signal is input again to the input terminal (υ), the NO, 1 signal is input again to the input terminal (υ). The filtered signal is sent to the output terminal (
6) is output.

Since the above-mentioned operation is applied to each clock of the clock signal of the input terminal (2), the seventh clock signal is applied to the output terminal (6).
A signal similar to the output Y(n) in the figure, that is, the input terminal (1
) is obtained by filtering the sequential signals, and at this time, M=20 and N=7 are set, and the tap (3a) is set to select the output of the 13th stage shift register. Therefore, when one clock of each digital signal is input to the input terminal (1), a signal obtained by filtering each digital signal is output to the output terminal (6).
The signal at the input terminal (1) and the signal at the output terminal (6) become the same type of signal.

Therefore, in the case of the above embodiment, each tap (3a) to
(3n), that is, a digital filter is formed using one latch circuit (LT) for each delay means (DL),
In this case, each tap (3a) to (3n) only needs to perform one multiplication and addition during one clock of the clock signal, so even if the number of taps N increases, Similarly, filtering of sequential signals with high clock rates becomes difficult.

Since each of the taps (3a) to (3n) is formed of the same circuit pattern with a simple structure including one latch circuit (LT), integration can be easily performed with a simple structure.

In addition, since the signal at the input terminal (1) and the signal at the output terminal (6) are the same type of signal, for example, when forming a digital equalization circuit using a digital filter,
Timing processing etc. can be done easily.

Basically, the delay stages selected by the delay means (SL) of each tap (3a) to (3n), that is, the shift register, need only be shifted by one stage, for example, M=20.
, N=7 (7) Tokini, tap (3a) (7)
Of course, a shift register other than the 13th shift register may be selected.

Furthermore, it is also possible to form each delay stage using a memory or the like instead of each shift register (SR+) to (SRM).

By the way, if the clock rate of the sequential signal becomes significantly high, for example, on the output side of the selection circuit (SL) of each tap (3a) to (3n) or on the output side of the multiplier (MP),
Furthermore, it is only necessary to form a necessary number of latch circuits, and in this case, the selection circuit (S
By shifting the position of the predetermined delay stage selected by L) forward or backward, the signal at the input terminal (1) and the signal at the output terminal (6) can be made to be the same type of signal.

(Other examples) Next, FIG. 3 showing another embodiment will be explained.

In Figure @3, the same symbols as in Figures @1 and 2 indicate the same things, and the differences are for each tap (3a) to (3n).
) is connected to the other input terminal of the adder (AD), and the shift register selected by the selection circuit (SL) of each tap (3a) to (3n) is connected as shown in Fig. 1. The point is that the shift register is placed one stage later.

Therefore, in the case of this embodiment as well, one latch circuit (L
A digital filter is formed using T), and
Even if the number of taps N becomes large, filter processing of sequential signals with a high clock rate can be performed, and the signal at the input terminal (1) and the signal at the output terminal (6) become the same type of signal.

[Effects of the Invention] As described above, according to the digital filter of this invention,
Each delay means is composed of a serial circuit of delay stages of the digital signal type, and the output signals of the delay stages shifted by one stage of each delay means are multiplied by coefficients at the same timing, and each adder is multiplied by a coefficient at the same timing. Since the input signal at the other input terminal or the output signal at the output terminal is delayed by one clock by the latch circuit, a simple selection circuit with one multiplier, adder, and latch circuit is provided for each delay means, that is, for each tap of the filter. With this configuration, it is possible to perform filter processing on sequential signals with a high clock rate, and it can be easily integrated.

[Brief explanation of drawings]

1 to 3 show embodiments of the digital filter of the present invention, FIG. 1 is a block diagram of one embodiment, FIG. 2 is a partial block diagram of FIG. 1, and FIG. 3 is a block diagram of another embodiment. Embodiment Block Diagrams Figures 4 to 7 are block diagrams of conventional digital filters, respectively. (1)...Signal input terminal, (2)...Clock input terminal, (3a) to (3n)...1st to Nth tap, (6)...Signal output terminal, (DL) ... Delay means, (SRI) ~ (SRN+) ... Shift register, (
SL)...selection circuit, (MP)...multiplier, (AD
)... Adder, (LT)... Latch circuit. Agent: Patent Attorney Ryutabe Fujita ゛1g2 Figure 4 Figure 5

Claims (1)

[Claims] (1) In a digital filter that digitally filters a sequential signal formed by time-division multiplexing multiple types of digital signals every clock of a predetermined clock signal, an input terminal of the sequential signal is synchronized with the clock signal. A plurality of delay means each consisting of a column circuit of delay stages corresponding to the number of types of the digital signal which delay one clock of the sequential signal are connected in series; a selection circuit that selects and outputs an output signal of a predetermined delay stage shifted by a stage; a multiplier that digitally multiplies the output signal of the selection circuit by a predetermined coefficient;
The output signal of the multiplier is input to one input terminal, and the adder performs digital addition, and the adder is connected to the output terminal or the other input terminal of the adder, and delays the input signal by one clock of the clock signal. and a latch circuit that outputs an output signal, and an output terminal of the adding circuit of each of the delay means is connected to the other input terminal of the adding circuit of the next digital delay means or the latch circuit. .