JPS62164274A - Memory information reading circuit - Google Patents

Abstract

PURPOSE:To prevent erroneous detecting of reading data by checking that the level of the differential signal of a read analog signal is kept less than a prescribed negative level for a prescribed time from a period when said differential signal is kept at a level higher than the prescribed positive threshold value and also that a zero level point exists. CONSTITUTION:An analog signal 101 reproduced by a reading optical head 1 is supplied to a differentiating circuit 3 via an amplifying circuit 2. Then a differential signal 102 is supplied to comparators 4-6. A peak signal 103 is delayed by a prescribed time T1 by a delay circuit 7 and supplied to a clock input of a D type FF 10 as a signal 106. While a positive level signal 104 is delayed by a prescribed time T2 longer than the time T1 by a delay circuit 8 and inputted to an AND circuit 9 as a signal 107. The circuit 9 secures the coincidence between the signal 107 and a negative level signal 105. Then a signal 108 is supplied to the D input of the FF 10. The FF 10 secures the coincidence between both signals 106 and 108 and generated a read digital signal 109. Thus it is possible to prevent erroneous detecting due to noise.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a storage information readout circuit, and in particular, it is suitable for an optical storage device such as an optical disk device. The present invention relates to a storage information reading circuit that obtains digital signals.

〔overview〕

The present invention provides a memory information reading circuit which obtains a read digital signal as an output by detecting a peak value of a read analog signal obtained from a memory information detection means, in which the level of the differential signal obtained by differentiating the read analog signal is means for checking that the level of the differentiated signal is below a predetermined negative threshold for a predetermined period of time from the point in time when the level of the differential signal becomes below a predetermined negative threshold, and outputting a read digital signal. By providing this, erroneous output of the read digital signal due to noise when there is no signal or noise in the undershoot waveform portion of the read analog signal is prevented, and the read margin is improved.

[Conventional technology]

Information reading in an optical storage device such as an optical disk device corresponds to the presence or absence of bits (trace) formed on the same surface of the medium when the storage medium is irradiated with a laser beam focused on a very small spot. This is done by using an optical sensor to detect changes in the intensity of reflected light. The read analog signal obtained from this optical sensor contains information at a positive peak point corresponding to the center of the pitch h12 on the medium surface 1, as shown by the waveform of the read analog signal 101a in FIG. The waveform will be Therefore, the circuit is configured to obtain read data as a read digital signal each time the read circuit detects a positive peak point of the read analog signal.

The peak point detection means is generally performed by combining a differentiation circuit and a zero-cross comparison circuit to detect the zero-level cross point of the read analog signal after differentiation. However, due to the increase in high-frequency noise due to the characteristics of differentiating circuits, and because it is generally not possible to obtain a sufficient S/N ratio for this type of readout analog signal, the readout circuit uses a signal amplitude Level detection is also performed to check the peak detection output, and a method is used to obtain read data from the coincidence of the peak detection output and the level detection output.

When using the readout analog signal itself as a means of level detection, there are circuit limitations such as difficulty in wideband amplification that includes DC, even though the readout analog signal inherently contains a DC component. Therefore, AC amplification is generally performed, and as a result, the envelope of the read analog signal fluctuates due to data bumps, making level detection difficult.

Conventionally, the read analog signal 101b is second-order differentiated as shown in FIG. A method has been used in which the second-order differential signal 1)0 is compared with a predetermined threshold voltage 1).

[Problem that the invention seeks to solve]

In the above-mentioned level detection method in the conventional storage information readout circuit, the second-order differential wave of the read analog signal is used as the target for level detection, so the first-order differential signal 102b or more uses high-frequency noise for peak detection due to the differentiation circuit characteristics. , and therefore the bitless “0” in Figure 3
There was a drawback that false detection of "1" data due to noise at the data position was likely to occur.

Furthermore, as can be seen in FIG. 4, in order to use a second-order differential wave in the undershoot waveform portion 13 of the read analog signal due to the diffraction effect at the edge portion of the bit or the low-pass filter characteristics in the amplifier circuit, The drawback was that false detections due to noise were likely to occur.

An object of the present invention is to prevent false detection of read data due to noise during no signal or noise in the undershoot waveform part of the read analog signal, and to improve the read margin by eliminating the above-mentioned drawbacks. An object of the present invention is to provide an improved storage information reading circuit.

[Failure to solve the problem]

The present invention provides a memory for outputting a read digital signal, including a stored information detecting means (1) for reading out a read analog signal from an information storage medium, and a differentiating means (3) for differentiating the read analog signal and outputting a differentiated signal. In the information reading circuit, a first detection means (4) detects that the level of the differential signal crosses the zero level and outputs a peak signal;
- a second detection means (5) for detecting that the level of the recorded failure signal is equal to or higher than a predetermined positive threshold and outputs a positive level signal; a third detection means (6) for detecting that the level is below a predetermined negative threshold and outputting a negative level signal; and for delaying the peak signal by a first delay time and outputting a delayed peak signal. a first delay means (7); a second delay means (8) for delaying the positive level signal by a second delay time greater than the first delay time and outputting a delayed positive level signal; The present invention is characterized in that it includes a selection means (9, 10) for outputting a delayed positive level signal and a readout digital signal based on a condition of coincidence between the delayed peak signal and the negative level signal.

[For production]

In the present invention, the first detecting means (4) generates a peak signal when the differential signal crosses the zero level of the differential signal, which is the no-signal level, from positive to negative, and the second detecting means (5) ) generates a positive level signal when the level of the differential signal is above a predetermined positive threshold, and the third detection means (6) generates a positive level signal when the level of the differential signal is below a predetermined negative threshold. When a negative level signal is generated.

Furthermore, the first delay means (7) generates a delayed peak signal by delaying the peak signal by, for example, T1 time, and the second delay means (8) generates the positive level signal by delaying the above-mentioned positive level signal by T+ waiting time. The selection means (9, 10) generates a delayed positive level signal delayed by, for example, T2 time.
Accordingly, a read digital signal is obtained under the condition of -1- delayed positive level signal, the jW extended peak signal and -I- storage level signal.

Therefore, the present invention provides the output of the read digital signal as
For a predetermined period of time from the time when the level of the differential signal was greater than or equal to a predetermined positive threshold, the level of the differential signal is less than or equal to a predetermined negative level, and a zero level point correctly exists during that time. things are checked. As a result, erroneous detection of [1) data due to noise at the "0" data position of the read analog signal and noise due to the undershadowed waveform portion can be prevented.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In this embodiment, the analog signal 10 read from the information storage medium is
A reading optical head 1 as a storage information detecting means for reading 1.
, the read analog signal 101 is differentiated, and the differentiated signal 102 is
In the storage information reading circuit that outputs the read digital signal 109 and includes a differentiating circuit 3 as a differentiating means that outputs the differential signal 109, a peak signal 103 is output upon detecting that the level of the differential signal 102 crosses the zero level from positive to negative. a comparator circuit 4 as a first detection means for detecting the differential signal 102, and a second detection means for detecting that the level of the differential signal 102 is equal to or higher than a predetermined positive threshold voltage and outputting a positive level signal 104. and the level of the differential signal 102 is a predetermined negative threshold voltage -■.

A comparison circuit 6 as a third detection means which detects that the level is below and outputs a negative level signal 105, and a peak signal 10
3 by the first delay time T to obtain a delayed peak signal 1.
a delay circuit 7 as a first delay means that outputs 06;
a delay circuit 8 as a second delay means for delaying the positive level signal 104 by a second delay time T2 which is larger than the negative delay time T1 and outputting a delayed correct/bell signal 107; and a delayed positive level signal. 107, delayed peak signal 106, and negative level signal 105, an AND circuit 9 and a D-type flip-flop (D-type F/F) 10 are included as selection means for outputting a read digital signal 109.

In the figure, 2 is an amplification circuit for the read analog signal 101, and 1) is a delay circuit for setting the pulse width of the read digital signal 109 to T3.

The feature of the present invention is that comparison circuits 4.5 and 6, delay circuits 7 and 8, AND circuit 9 and D-type flip-flop 10 are provided in FIG.

Next, the operation of this embodiment will be explained.

FIG. 2 is an operational waveform diagram in the embodiment of FIG.
Waveforms 01 to 109 indicate operational waveform examples of each signal 101 to 109 in FIG. In FIG. 2, thin lines in the waveforms of the peak signal 103 and the delayed peak signal 106 indicate noise. Since the read analog signal 101 reproduced by the read optical head 1 is weak, it is amplified by the amplifier circuit 2 and then supplied to the differentiator circuit 3. In the differentiating circuit 3, the read analog signal 101 is differentiated with respect to time, so that its output, the differential signal 102, has a waveform in which the peak point of the read analog signal 101 is converted to a zero cross point.

This differential signal 102 is fed to one input of a comparison circuit 4.5.6. Since zero level is supplied to the other input of comparator circuit 4, its output peak signal 1
03 is "1" when the differential signal 102 crosses the zero level.
”, “0” becomes a changing logic signal. That is, the positive peak point of the read analog signal 101 containing information is detected as a polarity reversal of the peak signal 103 from "0" to "1)". On the other hand, the other input of the comparator circuit 5.6 has a predetermined positive and negative threshold voltage +VT.
and 1■□, the positive level signal 104 which is the output of the comparator circuit 5 is the differential signal 102.
becomes a logic signal that becomes "1" when the threshold voltage becomes 1-1-. The negative level signal 105 which is the output of the comparator circuit 6 has a differential signal 102 of the threshold voltage -
It becomes a logic signal that becomes "1" when it becomes 1 or less.

The peak signal 103 is delayed by a predetermined time T1 by the delay circuit 7 to become a delayed peak signal 106, which is supplied to the clock input of the D-type flip-flop 10.

In addition, the positive level signal 104 and the delay circuit 8 result in a signal of 1゛.

The signal is delayed by a larger predetermined time T2, becomes a delayed positive level signal 107, and is supplied to one input of the AND circuit 9. In the AND circuit 9, since the negative level signal 105 is supplied to the other human power, here, first, the delayed positive level signal 1
07 and the negative level signal 105 is established, and the level signal 108 is supplied to the D-type flip-flop 10.

Next, the D-type flip-flop 10 outputs this level signal 1.
08 and the delayed peak signal 106, a read digital signal 109 is generated. That is, the read digital signal 109 is converted into a delayed peak signal 106 and a delayed positive level signal 1 by an AND circuit 9 and a D-type flip-flop 10.
07 and the negative level signal 105 are matched.

The delay circuit 1) is for setting the pulse width of the readout digital signal 109 to T3, and by supplying the readout digital signal of opposite polarity to the reset input of the D-type flip-flop 10 after a delay of T3. achieved.

In the above embodiments, the positive and negative threshold voltages have the same absolute value, but are not particularly limited to being the same.

〔Effect of the invention〕

As explained above, the present invention provides a level detection condition for a readout circuit that obtains a readout digital signal by matching a peak detection condition and a level detection condition, such that the differential signal obtained by differentiating the readout analog signal has a positive threshold. By delaying the confirmation that the differential signal is equal to or greater than the value for a predetermined time and checking that the differential signal is less than or equal to the negative threshold under the delayed positive level condition, noise during no signal or readout analog signal can be eliminated. This has the effect of preventing erroneous detection of read data due to noise in the visible undershoot waveform portion and improving the read margin.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a diagram of its operating waveforms. FIG. 3 is an explanatory diagram showing the correspondence between bits on a storage medium and read analog signals. FIG. 4 is an operating waveform diagram of a conventional example. 1... Reading optical head, 2... Amplifying circuit, 3... Differentiating circuit, 4.5.6... Comparing circuit, 7.8.1)...
・Delay circuit, 9...AND circuit, 10...D-type flip-flop, 12...bit, 13...undershoot waveform section, 101.101a, 101b-...
Read analog signal, 102.1o2b-? 6 minute signal, 1
03...Peak signal, 104...Positive level signal, 1
05... Negative level signal, 106... Delayed peak signal, 107... Delayed positive level signal, 108... Level signal, 109... Read digital signal, 1) 0...
Second-order differential signal, T3, T, , T3...delay time, V
, , +Va, -V. ...threshold voltage. Patent Applicant NEC Corporation Representative Patent Attorney Naotaka Ide;j:,:,1'
jpa~,.

Claims (1)

[Claims] (1) Storage information that outputs a read digital signal, including a stored information detection means (1) that reads a read analog signal from an information storage medium, and a differentiator (3) that differentiates the read analog signal and outputs a differentiated signal. In the readout circuit, first detection means (4) detects that the level of the differential signal crosses the zero level and outputs a peak signal; and the level of the differential signal is equal to or higher than a predetermined positive threshold. A second detection means (
5), and a third detection means (
6), a first delay means (7) for delaying the peak signal by a first delay time and outputting a delayed peak signal, and delaying the positive level signal by a second delay longer than the first delay time. a second delay means (8) for outputting a delayed positive level signal with a delay of time; and a selection means for outputting the read digital signal based on a matching condition between the delayed positive level signal, the delayed peak signal, and the negative level signal. (9, 10) A storage information reading circuit characterized by comprising: (9, 10).