JPS61206971A - Memory information reading circuit - Google Patents

Abstract

PURPOSE:To improve reading margin by checking in amplitude of a differential signal between a differentiation signal obtained by differentiating a read analog signal and a delayed differentiation signal obtained by delaying the differentiation signal by a fixed time to use as the condition of level detection of a reading circuit that obtains read data by coincidence of the condition of peak detection and the condition of level detection. CONSTITUTION:A differentiating circuit 3 time differentiates a read analog signal (a) and outputs a differentiation signal (b). A delay line 4 obtains the first delayed differentiation signal (c) in which the differentiation signal (b), an inputted signal, is delayed by Td/2 and the second delayed differentiation signal (d) delayed by Td. A peak signal (g), output of a comparator circuit 5, goes to a binary logical signal '1', '0' of which is changed when the first delayed differentiation signal (c) cross the zero level. Differential between the differentiation signal (b) and the second delayed differentiation signal (d), delayed by Td therefrom, is detected by a differential amplifier circuit 6 and a differential signal (e) is obtained. Reading data (h) is prepared from the condition of coincidence of the peak signal (g) and the level signal (f) in a D-type flip-flop 8.

Description

TECHNICAL FIELD The present invention relates to a storage information reading circuit, and more particularly to a storage information reading circuit from an optical storage device such as an optical disk device.

Conventional technology To read information in an optical storage device such as an optical disk device, when a storage medium is irradiated with a laser beam focused on a very small spot, the intensity of the reflected light changes depending on the presence or absence of bits formed on the surface of the medium. This is done by using an optical sensor to detect changes in the The read analog signal obtained from this optical sensor has a bit 1, as shown in waveform (a) in the MFM (Modified FM) storage modulation method in FIG. 4, for example.
The waveform contains information at the positive peak point corresponding to the center of 1. Therefore, the readout circuit is configured to obtain readout data, which is a digital signal, by detecting the positive peak point of the above-mentioned readout analog signal.

Peak point detection means is generally performed by combining a differentiating circuit and a zero-cross comparing circuit to detect the zero level crossing point of the read analog signal after differentiation. Since the S/N of the signal itself cannot be obtained sufficiently, the readout circuit also performs level detection to check the signal amplitude in order to prevent erroneous detection of data due to noise. A method of obtaining read data from matches is used.

Conventionally, as a method for level detection, there is a method of detecting a read analog signal or a read analog signal after differentiation, and comparing the average level with a predetermined threshold value. Further, as shown in FIG. 5, the read analog signal (b) after differentiation is compared in level with two thresholds (Vl, V2), and the read analog signal (b) after differentiation is compared with the first threshold ( ■1) The zero crossing point is valid as data only if it crosses the zero level corresponding to the peak point within a certain period of time after reaching the second threshold value (■2) or more within a certain period of time. The following method is used.

In the former method described above, since it is not possible to check the signal amplitude on a bit-by-bit basis, partial signal loss due to media defects may be overlooked during verification performed when information is directly recorded, and the However, there is a drawback that reading errors occur due to erroneous detection due to noise in this missing part.

On the other hand, in the latter method, the signal amplitude is checked for each bit, which eliminates the disadvantages of the former method, but it has the disadvantage that the circuits for level comparison, timing setting, etc. become complicated, especially at high frequencies. When used as a read signal, timing settings are affected by variations in circuit elements such as delay times, resulting in variations in the effective signal amplitude check.

The present invention has been made to eliminate the drawbacks of the above-mentioned conventional methods, and its purpose is to accurately determine the level of each bit and to discriminate data from noise using a simple configuration. An object of the present invention is to provide a storage information readout circuit which is capable of improving the readout margin.

Structure of the Invention The storage information readout circuit according to the present invention is a storage information readout circuit that obtains binary digital data by detecting the peak position of a readout signal by a storage information detection means, and the storage information readout circuit is configured to obtain binary digital data by detecting the peak position of a readout signal by a storage information detection means. peak detection means for detecting a peak signal, differentiating means for obtaining a differential signal of the read signal, delay means for obtaining a delayed signal by delaying this differential signal by a predetermined time, and a difference between the differential signal and the delayed signal. and a comparison means for comparing the level of this difference signal with a predetermined threshold value, and digital data is obtained based on the condition that the level comparison result matches the peak signal. It is characterized by

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.
is a readout optical head, 2 is an amplifier circuit, 3 is a differential circuit, 4 is a delay line with an intermediate tap and has a delay time of Td, 5.7 is a comparison circuit, 6 is a differential amplifier circuit, and 8 is a D-type flip-flop. It is a circuit.

FIG. 2 is an operating waveform diagram in the embodiment shown in FIG.
Waveforms a) to (h) show examples of operating waveforms of each signal (a) to (h) in FIG.

Since the MFM read analog signal (a) reproduced by the read optical head 1 is weak, it is amplified by the amplifier circuit 2 and supplied to the differentiator circuit 3.

In the differentiating circuit 3, the read analog signal (a) is differentiated with respect to time, so that its output, the differential signal (b), has a waveform in which the peak point of the read analog signal (a) is converted to a zero cross point. The differential signal (b) is supplied to a delay line 4 having a total delay time Td, and is also supplied to one input of a differential amplifier circuit 6. . Since the delay line 4 has an output tap with a delay time of Td and an intermediate tap with a delay time of Td/2, the input signal, the differential signal (b), is delayed by Td/2 to produce a first delayed differential signal. (C) and a second delayed differential signal (d) delayed by Td can be obtained.

One input of the comparator circuit 5 receives the 1N-th differential signal (C)!
Since the zero level is supplied to the other input of fi, the output peak signal (g) changes by 1.0 when the first delayed differential signal (C) crosses the zero level2. It becomes a logical signal of the value. That is, the positive peak point of the read analog signal (a), which is the read information point, is detected as a polarity reversal from 0 to 1 of the peak signal (g) after a time period of Td/2 has elapsed.

On the other hand, since the second delayed differential signal (d) is supplied as the other input of the differential amplifier circuit 6, here the differential signal (b)
The difference between the second delayed differential signal (d) and the second delayed differential signal (d) delayed by Td is detected, and a difference signal (e) is obtained. In principle, this differential signal (e) becomes a roughly differential waveform of the differential signal (b) due to the differential effect of the delay difference, and the read analog signal (
The signal has a negative peak at a position where a time period of Td/2 has elapsed from the positive peak point in a).

Next, this difference signal (e) is supplied to one input of the comparison circuit 7, and since the other input is supplied with a predetermined threshold voltage Vt, the level signal which is the output of the comparison circuit (f) is a binary logic signal that becomes 1 when the difference signal (e) becomes equal to or less than the threshold voltage Vd.

The level signal (f) is supplied to the D input and reset input of the D type flip-flop 8.
Since the peak signal (0) is supplied to the clock input of , the read data (h) is created based on the matching condition between the peak signal (g) and the level signal (f). That is, the read data (h) has a level signal (f) of 1 at the inversion edge of the peak signal (g) corresponding to the information from 0 to 1.
Only in this case is the signal inverted from O to 1.

As can be seen from the above embodiments, the negative amplitude of the difference signal (e) is used as a level detection condition for determining whether the read peak point is data or not. The negative amplitude of this difference signal (e) corresponds to a change in the waveform near the positive peak point of the read analog signal (a), but since it is proportional to the amplitude of the read analog signal (a), it is simply a data This can be applied not only to distinguishing bits from noise, but also to determining whether or not bits have been correctly formed during verification performed immediately after recording information.

Further, although the delay time Td in the delay line 4 is not particularly defined in the embodiment, Td−T with respect to the minimum bit interval To
If it is set to o/2, the amplitude of the differential signal (e) becomes the largest, and in this case, a better S/N condition than that of the differential signal (b) can be obtained, so that erroneous detection of data due to noise can be prevented.

In the embodiment shown in FIG. 1, the differentiating circuit 3 and delay line 4 are used for peak detection and level detection in order to simplify the circuit, but as shown in FIG. It is clear that peak detection and level detection can also be made independent.

1. Polishing 11. As explained above, according to the present invention, the level detection condition of the readout circuit that obtains readout data by matching the peak detection condition and the level detection condition is the differential signal obtained by differentiating the readout analog signal and this differential signal. By checking the amplitude of the differential signal with the delayed differential signal delayed by a certain period of time, accurate level judgment for each bit and discrimination of data from noise can be achieved, which has the effect of improving the read margin. Another advantage is that the above effects can be achieved with a simple circuit configuration.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is an operational waveform diagram of each part of the circuit of Fig. 1, Fig. 3 is a circuit diagram of another embodiment of the invention, and Fig. 4 is a diagram on a storage medium. FIG. 5 is a waveform diagram for explaining the prior art. Explanation of symbols of main parts 1...Reading optical head 3.9...
...Differential circuit 4.10...Delay line

Claims (1)

[Claims] A storage information readout circuit configured to obtain binary digital data by detecting a peak position of a readout signal by a storage information detection means, the storage information readout circuit comprising: a peak detection means for detecting a peak point of the readout signal to obtain a peak signal; , a differentiating means for obtaining a differential signal of the readout signal, a delaying means for obtaining a delayed signal by delaying the differential signal by a predetermined time, and a difference detecting means for detecting a difference between the differential signal and the delayed signal to obtain a difference signal. , a comparison means for level-comparing the difference signal and a predetermined threshold value, and the digital data is obtained based on a condition that the level comparison result matches the peak signal. .