JPS62160756A - Semiconductor device - Google Patents

Abstract

PURPOSE:To implement high density in memories and the like, in a semiconductor such as a dynamic RAM, by covering a protruded part, which is formed on the semiconductor substrate with a capacitor electrode. CONSTITUTION:Photoresist 2 is made to remain at a part, which is to become an active region in the future, by a photoetching method. With the photoresist 2 as a mask, RIE treatment is performed on an Si substrate, and a protruded part 1' is formed. In place of said photoresist, an SiO2 layer can be used. Then ions are implanted, and a channel stopper 6 is formed. After the photoresist is peeled away, annealing after the ion implantation is performed. A capacitor oxide film 3 having a thickness of 100Angstrom is formed by thermal oxidation. Thereafter, a first polycrystalline layer 4 is deposited on the entire surface. Only the polycrystalline Si layer in an element isolating region is removed by photoetching. Then, a part at the protruded part 1' is buried with an SiO2 film by using a CVD method. The surface is flattened. A capacitor electrode is provided on the upper part of a capacitor in this way. Therefore a transistor can be formed directly on the capacitor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a high-density memory.

[Summary of the invention]

The present invention provides semiconductor devices such as dynamic RAM,
By making the capacitor electrode cover the convex portion formed on the semiconductor substrate, it is possible to increase the density of memories and the like.

[Conventional technology]

One memory cell (one bit) of a DRAM is composed of one pair of transistors and a capacitor, but in order to increase the capacity, this cell must be made as small as possible, to several square microns. However, when the area becomes small, it is difficult to obtain the necessary capacitance with the conventional planar capacitor structure. With the increasing density of semiconductor devices, dynamic R is a method in which a trench is formed in the substrate, the bottom of the trench is used for isolation between elements, and the sidewall of the trench is used as a capacitor.

AM cells have been proposed.

An example of a DRAM using a conventional trench capacitor will be explained with reference to FIG. A P layer is provided on the epitaxial layers P to Nl with high impurity concentration, and a trench is formed.

A capacitor oxide film 3 is formed on the inner wall of the trench.
Furthermore, a storage electrode 12 serving as one electrode of the capacitor is provided. In the P layer, there is a drain region 14,
A source region 15 is formed and forms a MOSFET together with a gate 13 made of polycrystalline St.

The drain region 14 is connected to a bit line made of the first wiring layer 11. Since the source region 15 of the transistor is connected to the storage electrode in the trench capacitor, electrons are located inside the 8i layer 3, and holes, which are the majority carriers of the p++ layer 1, are located outside the insulating layer 3. Therefore, the depletion layer does not expand within P"Jil. (Denpa Shimbun December 4, 1985) [Problems to be solved by the invention] The cell distribution density of DRAM is reduced by using trench capacitors. Even if it is increased, it is still insufficient for DRAMs of 4M or more, and it is necessary to further increase the distribution density.

In addition, even if a trench capacitor is used, in DRAMs that generate capacitance due to the expansion of the depletion layer, the spacing between cells is required to prevent the depletion layers of adjacent cells from coming into contact and causing bunch-through. must be sufficiently maintained. This is also an obstacle in increasing the density of DRAM.

[Means for solving problems]

In the present invention, the above-mentioned problem has been solved by adopting a configuration in which the convex portion formed on the semiconductor substrate is covered with a capacitor electrode.

[Effect]

Since the capacitor electrode is provided above the convex-shaped capacitor, a transistor can be formed directly above the capacitor, and a high density DRAM can be achieved.

Also, between the capacitors, CV D 5iOz
, so the isolation between elements is perfect.

〔Example〕

In order to better understand the structure of the semiconductor device of the present invention,
The present invention will be explained based on the manufacturing steps shown in FIGS. 1A to 1E.

FIG. 1A A photoresist 2 is left by photo-edging in a portion that will become an active region in the future, and using this photoresist 2 as a mask, an RIE process is performed on the Si substrate to form a convex portion 1'. At this time, a SiO□ layer may be used instead of the photoresist.

Figure 1B Channel stopper 6 after ion implantation
After forming the photoresist 2 and removing the photoresist 11, annealing is performed after ion implantation.

FIG. 1C After forming a capacitor oxide film 3 with a thickness of 100 people by thermal oxidation, a first polycrystalline layer 4 is deposited on the entire surface. After removing only the polycrystalline Si layer in the element isolation region by photoetching, the CVD method is used to fill in the spaces between the convex portions 1' with a 5iOz layer 5 to flatten the surface.

FIG. 1D After opening a window in the SiO□ layer on the convex portion 1', the second polycrystalline layer 7 is formed on the entire surface, and the first and second polycrystalline layers 7 are formed through the opening 16. Connect. The second polycrystalline layer 7 is patterned and subjected to RIE treatment.

FIG. 1E The surface of the second polycrystalline SiN is oxidized to form the gate oxide film 8 of the switching transistor, and the third polycrystalline SiJ! ! 9 will be provided. After patterning this third polycrystalline Si layer 9 to a desired gate length, RIE treatment is performed. Next, using this gate as a mask, ion implantation is performed to form source and drain regions, and then an annealing process is performed after the ion implantation.

After providing an interlayer insulating film on this, a window is opened in this insulating film. By attaching AI to the entire surface, AI
A contact is made between the second polycrystalline Si layer and the second polycrystalline Si layer. Unnecessary AI is removed by RIE processing, leaving an AI line that will become a bit line. Perform AI sintering to complete DRAM.

FIG. 1F is a diagram showing the arrangement of various parts of the semiconductor device of the present invention. The cross-sectional view shown in FIG. 1A-H is similar to that shown in FIG.
1 shows one element in a portion indicated by a dashed-dotted line A-B in FIG. The source of the switching transistor provided in the second polycrystalline Si layer 7 is connected to the capacitor electrode through the contact hole 16. On the other hand, the drain of the switching transistor is connected to the bit line 11 via a contact hole 17. The gate electrode made of the third polycrystalline Si layer 9 serves as a word line.

Note that in order to reduce the number of bit line contacts, it is also possible to connect two cells as a set.

〔Effect of the invention〕

The semiconductor device of the present invention has the following effects.

(i) Since the spaces between cells are filled with a CV DSiO□ layer, isolation between elements is perfect.

(ii) The capacitor pattern is very simple.

Therefore, it is very advantageous for manufacturing high-density DRAMs of 4M or more.

(iii)) Portions other than the wrench can also be used as capacitors.

(iv)) Make the bottom of the wrench into an inter-element isolation region,
Most of the other side walls and the upper part can be used as a capacitor, which is advantageous in terms of higher density and larger capacity of the capacitor.

(v) I? on the first polycrystal of the capacitor? There is no damage to the substrate due to the TE treatment.

(vi) Since element isolation can be performed only at the bottom of the trench, in other words, the channel stopper only needs to be provided at the bottom, the manufacturing method is simplified.

[Brief explanation of drawings]

FIG. 1 ABCDE is a diagram illustrating the semiconductor device of the present invention based on the manufacturing process. FIG. 1F is a diagram showing the arrangement of various parts of the semiconductor device of the present invention. FIG. 2 is a diagram showing a conventional DRAM. 1... Semiconductor substrate 1... Convex portion 2... Photoresist 3... Capacitor oxide film 4... First
Polycrystalline 5iJii 5...SiO□ layer 6...Channel stopper 7...Second polycrystalline Si layer 8...Gate oxide film 9
...Third polycrystalline Si layer 10...SiO□ layer 11
...AI wiring layer 12...Storage electrode 13...Gate electrode 14...Drain region 15...Source region 16...Contact between source and capacitor 17...
Bit line and drain contact 18...capacitor part

Claims (1)

[Claims] A semiconductor device in which a capacitor electrode is formed to cover a convex portion formed on a semiconductor substrate.