JPS62160487A - Character pattern data compression - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] Technical Field The present invention relates to a method for compressing character pattern data expressed as a dot matrix of M rows and N columns, and particularly relates to a method for compressing character patterns that has a high compression ratio and is easy to restore. It is something.

<Prior art> Figure 1 shows an example of the kanji ``hon'' expressed as a dot matrix of 24 rows x 24 columns.
1" and white as "0" dot information without data compression, 576 bits of data will be stored for each character. Considering this compared to 2965 JIS Level 1 Kanji characters, The data is approximately 213 bytes,
A huge amount of data will be stored.

For this reason, methods for compressing kanji pattern data using statistical trends of kanji patterns have already been proposed.

This takes advantage of the fact that the state of a pixel in a Kanji pattern has a strong correlation with the states of surrounding pixels. In other words, if the states of all the pixels around a pixel are "white", the state of that pixel is also "white", and conversely, if the surroundings are "black", the probability that that pixel is also "black" is extremely high. That is to say. In addition, the surrounding pixels for a certain pixel are determined by the probability that the pixel is "black" when the next pixel adjacent to the left, right, top, and bottom is "black", and the probability that the pixel is "black" when the pixel adjacent diagonally is "black". The probability that the pixel is "black" is much higher in the former case, and furthermore, the probability depends on the horizontally adjacent pixels rather than the vertically adjacent pixels. As one of the compression methods that utilizes the statistical tendency of kanji patterns as described above, character pattern data of M rows by N columns is divided into subpatterns of m rows by n columns, and Huffman is applied to each of the subpatterns. The encoding method is applied.

In other words, if a 24x24 dot pattern is divided into 2x2 subpatterns, each subpattern consists of 4 pixels, so there are 16 possible patterns.
Which subpattern occurs in a given subpattern depends on the state of its adjacent subpatterns.

Therefore, the sub-pattern to be encoded is set as the sub-pattern of interest, and the sub-patterns adjacent to the sub-pattern of interest are scanned from left to right using the IJ pattern in Figure 1, which has the highest degree of dependence. In this case, the subpattern on the left is used as a reference subpattern that provides conditions for the subpattern of interest, and it is determined to which of 16 patterns the state of the subpattern of interest belongs to the state of the reference subpattern. It's something to see.

Then, to the 16 patterns, appearance frequency rankings with respect to the states of the reference sub-patterns are assigned in advance in 16 steps using human codes, and the states of the noted pattern are expressed in the appearance frequency rankings using human codes. , this is 24
The X24 dot pattern is sequentially encoded. In this case, since there is no reference subpattern to the left of the first subpattern of interest on the left, a temporary subpattern is created to set the initial conditions. Encode and JI
When we investigate the 2965 characters of the S 1st level, we get the results shown in Figure 7.

As shown in Figure 7, among the 2965 kanji characters, there are 2318+5 sub-patterns with the highest frequency of occurrence, and the second highest frequency is 0 with 640g2, and those with higher frequency of occurrence have fewer bits. The total code length is 1019125 bits, and the compression rate is <problems with the conventional technology>. Although a high compression rate can be obtained, this encoding method
Since one of the 16 code words is assigned to one sub-pattern, the code given to each sub-pattern is a code with no regularity in length. For example, in FIG. 7, if we pay attention to ranks 10 to 16, the code length is 7.7.
7.8.9°10.10. This makes it irregular.

Therefore, with this compression method, it is difficult to restore character pattern data, and a very complicated decoding device is required.

<Objective of the Invention> The present invention aims to eliminate the drawbacks of the conventional character pattern data compression methods described above, and particularly provides a compression method that is easy to restore.

That is, a dot pattern of M rows and N columns is divided into subpatterns of m rows and n columns, and the appearance of a subpattern of interest to be encoded among the subpatterns with respect to one reference subpattern adjacent in the left and right direction. In this variable-length encoding, a code of 1 pit is assigned to the first rank of appearance frequency, and the second and subsequent ranks are assigned a rank of 2k, where k is an integer. and (2k+1
) is assigned a length of (k+2) bits, and a bit indicating the end of the code and a bit distinguishing between 2k and (2k-H) are assigned to the second bit, thereby giving regularity to the code length, This makes it easy to restore character pattern data.

<Embodiment> The character pattern data compression method of the present invention divides a character pattern expressed in a 24×24 matrix pattern as shown in FIG. , variable-length encoding is performed on each sub-pattern based on the frequency of appearance with respect to the reference pattern to the left of the sub-pattern.

In FIG. 2, since the subpatterns SPY, 5P25+, etc. at the left end of the matrix have no reference pattern on the left, a reference pattern sPo is hypothetically set for each subpattern, and this pattern meets the condition of "blank" or "roooo". It is set.

Therefore, the subpatterns in FIG. 2 are encoded by sequentially scanning from the left side of the upper row to the right, and the frequency of appearance of the subpattern SPI is encoded based on the reference pattern SPo.
The sub-pattern SP2 is encoded one after another under the condition of the reference pattern SPI, and the sub-pattern SP3 is encoded one after another under the condition of the reference pattern SP2. The sub-pattern 25 is a reference pattern S that is temporarily set as the sub-patterns Sr1 and 1M.
Po is encoded as a condition, and thereafter, the same method is used up to subpattern 5P144 (lower right subpattern).

By the way, regarding the encoding of the frequency of appearance, since the sub-pattern is configured in 4 rows x 1 column and is composed of 4 pixels, 16 patterns can be obtained.

Then, these 16 patterns are arranged in descending order of frequency of appearance, and variable length coding is performed starting from the one with the highest ranking, as shown in Figure @3.

That is, they are arranged in descending order of appearance frequency, and the first rank is assigned the code "On," and the second and subsequent ranks are assigned (k+2) bit lengths to ranks 2k and (2k+1), respectively, where k is an integer. Then, the last bit is assigned “0” indicating the end of the code, and the ranks 2k and (2k+1
) “O” or “l” (“l” is the rank (2k+
1) is assigned to the second bit.

As mentioned above, this encoding is shown in Figure 3, and the code lengths are 3.3.4.4 to 8, 8.9 for the second and subsequent ranks.
．． It has a regularity of 9.10.

Using such encoding, variable-length encoding is performed on the submatrix shown in Figure 2 according to the frequency of appearance with the condition of the submatrix on the left, and this is examined for 2965 JIS Level 1 Kanji characters. The results shown in FIG. 6 are obtained.

As is clear from FIG. 6, the compression rate in the case of encoding according to the present invention is very high, similar to the American Huffman code.

Next, considering decoding by the encoding of the present invention, one embodiment of this decoding circuit is shown in FIG.

In FIG. 4, l is a basic clock generation circuit, 2 is an octal counter, 3 is an address counter, 4 is a first ROM that stores compressed character data, that is, round character data compressed by the above encoding, and 5 is the This is an 8-bit shift register into which the compressed character data read from the first ROM 4 is input, and outputs the compressed character data one pit at a time to the control device 7 based on the clock signal from the basic clock generating circuit 1. 6 is a start bit counter, and when compressed data of a desired character is taken out from the first ROM 4 to the shift register 5 by the address counter 3,
This is for detecting the start bit position at which bit in the address position indicated by the address counter 3, compressed data of a desired character starts.

Reference numeral 7 denotes the above-mentioned control device, which sends out a ranking counter 8 and a second ROM 2k signal, which will be described later, based on compressed data sent from the shift register 5 in response to a start instruction from the start bit counter 6.

The ranking counter 8 is for detecting the appearance frequency ranking of compressed data, and is initially preset to ``r+t+'', and counts up by ``l'' every time a clock signal is output from the control device 7 to the line L1. When the control device 7 detects "0'" in the first bit and the third and subsequent bits of the compressed data, the contents of the counter 8 are output to the second ROM 9 in response to a load instruction signal outputted on line L2k. be.

The second ROM 9 receives the reference pattern data and the signal of the appearance frequency ranking for the reference pattern data, and outputs the corresponding restoration pattern (fcl dot patterns selected from 16 patterns) in 4 pitches. The latch circuit 12k sends out the lowest bit A to the address input of the 29th ROM 9. l is reline L from control device 7
8 and the second bit data of the compressed data is output (however, if the compressed data is 1 pit, "1" is output).
" data is asserted), and the contents of the rank counter 8 are introduced into bits A1-A3, and these A.

-A3 bits form the appearance frequency ranking signal. Furthermore, restored data of the previous sub-pattern, that is, reference pattern data, is input from the latch 12 to bits A4 to A7, and therefore, the second ROM receives the reference pattern data and the appearance frequency order signal for this. 0 10 is a column counter and 11 is a row counter, which accepts and outputs the corresponding restoration pattern;
These counters are 10.11 in a 24X24 matrix!
This is to detect whether or not restored data for characters has been obtained.

The operation of FIG. 4 is shown in the flowchart of FIG. 5, and the decoding operation will be explained below.

Now, suppose there is a character that you want to restore, first the CPU
The address counter 3 and start bit counter 6 are enabled by the instruction, and the data at the start address and start bit position of the compressed data is determined by the character code as CP.
The data is transferred from U to address counter 3 and start bit counter 6.

Then, the column counter IO is set to “24” and the row counter 11 is set to “24”.
"6" is preset. Furthermore, the ranking counter 8 is also “
+11”.

Thereafter, a start signal is transferred from the CPU to the basic clock generation circuit 1, which generates a basic tarok signal and also clears the shift register 5. A basic clock signal is applied from the basic clock generation circuit 1 to an octal counter 2, a shift register 5, a start bit counter 6, and a control device 7. The octal counter 2 updates the address counter 3 every 8 counts and resets the shift register 5.

As a result, 8-bit compressed data is first introduced into the shift register 5 from the ROM 4 of Ml based on the address value preset in the address counter 8, and the control device is input one bit at a time by the clock signal output from the basic tarlock generation circuit l. Transferred to 17. Here, all of the 8-bit compressed data introduced into the 1-address data or shift register 5 is not necessarily the data of the sub-pattern of the character to be restored now (see compression code in Figure 3).
Therefore, until the control device 7 receives the signal output from the start bit counter 6, it operates to ignore the data as belonging to a subpattern of another character.

The start bit counter 6 outputs a signal to the control device 7 when the preset start bit value and the count value of the introduced clock signal match.

τ). . A, 37. . -7, device 7,8□-5,71 Accepts the signal from counter 6, first shifts register 5
When the 1-bit data sent from the line L2k is "0", the control device 7 detects the first data "0" and outputs the line L2k load signal. Also, at this time, since it is the first time, a "1" signal is output to line L of the control device 7.

Therefore, the input address A of the second ROM 9. ~A3 receives a “1” signal from line L3 and “ from rank counter 8.
The "111" signal is input and the "1111" signal is introduced.

In other words, the signal indicating the appearance frequency ranking is "1111", and the second ROM 9 determines that this is the first appearance frequency ranking.

Here, input address A of ROM9 of M2. - The relationship between the input signal of A3 and the order of appearance frequency is shown in the following table. 0 Since it is the first reference pattern data for the input addresses A4 to A7 of the second ROM 9, "ooo o"
is input, therefore, the output of the second ROM 9 is the first in appearance frequency ranking for the reference pattern data "oooo".
A dot pattern of 1.0 is output and latched by the latch circuit 12k. The dot pattern of this latch output is output as restored data and is also input to input addresses A4 to A7 of the second ROM 9 as reference subpattern data for the next subpattern.

Then, the column counter 10 is counted down by "l" by the load signal outputted from the line L2k of the control device 17.

Next, a case will be explained in which, for example, compressed data rIIOJ, which has the third place in the appearance frequency ranking in FIG. Therefore, at this time, the line L2k load signal is not output, and the next bit is subsequently accepted. The second bit is "1", and this second bit signal "l" is output as is to line L3.

In other words, as mentioned above, the control device 7 outputs the second bit signal as it is to line L3, but only when the first bit is "0", there is no second bit, so the initial signal on line L3 is "l" is fixedly output as the state.

Subsequently, when the third bit "O" is input, the control device 7 causes the rank counter 8 to count up "!", detects "0", and outputs the line L2k load signal. As a result, the input address A of the second ROM 9. Then, "1" is input from line L3, and the content "000" of the rank counter 8 is input to the input addresses A1 to A3, and Ao-A8 becomes "1000".

As shown in the table above, this is determined to be the third place in the appearance frequency ranking, and at this time, addresses A4 to A7 of the second ROM9
The data of the reference sub-pattern is inputted to the dot pattern, and the dot pattern with the eighth highest frequency of appearance for this reference sub-pattern is selected and output. This output is latched by the latch circuit 12k in the same manner as above, and is output as restored data and as the next reference sub-pattern.

The decoding process is performed as described above until the column counter 10 reaches "0", and when the column counter 10 reaches "O", scanning of one row is completed and the row counter 11 is counted down by "1". The latch circuit 12 is reset. Since this reset of the latch circuit 12 restores the first (leftmost) sub-pattern of the second row, the reference pattern is the temporary reference pattern shown in FIG.
This is because "ooo".

In this way, when the row counter I+ reaches "1o", the pattern of one character is restored, and the row counter 11 stops the operation of the basic clock generation circuit l.

With the decoding circuit as described above, the compressed pattern according to the present invention can be easily restored to character pattern data, and this decoding circuit can also be easily configured.

Effect> As described above, in the present invention, character pattern data expressed using a dot matrix with M rows and N columns is divided into submatrices with m rows and n columns, each of which is formed into a sub-pattern. A first ROM that stores the variable length code for the character pattern while compressing characters by variable length encoding in order of appearance frequency for the submatrix using the pattern of the adjacent submatrix as a reference pattern. control circuit means for receiving the variable length codes sequentially read out from the control circuit means, detecting the variable length codes for each subpattern, and outputting appearance frequency ranking data for each subpattern; and appearance frequency ranking data from the control circuit means. and a second ROM which receives the dot data of the previously output sub-pattern (reference pattern) and outputs a dot pattern corresponding to the order of appearance frequency with respect to the input reference pattern. Well, the above part! As a variable-length code stored in the ROM, a 1-bit code is assigned to the first subpattern in the order of appearance frequency, and a 1-bit code is assigned to the subpattern whose appearance frequency is in second place or later, where k is an integer, and the order is 2k. A method for compressing character pattern data in which a (k+2) bit length is assigned to (2k+1), a code indicating the end of the bit length is assigned to the last bit, and a bit is assigned to the second bit to distinguish between ranks 2k and (2k+1). It has the characteristics that a very high compression ratio can be obtained, and decoding is also easy, so that the decoding circuit can be easily constructed.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a kanji dot matrix pattern to which the character pattern data compression method of the present invention is applied, WJ
2 is a diagram showing an example of dividing the dot matrix in FIG. A block diagram showing an example of a pattern data decoding circuit, Fig. i5 is a flowchart showing the circuit operation of Fig. 4, and Fig. 6 shows an example of the bit length of the entire JIS level 1 character compressed by the present invention. FIG. 7 is a diagram showing an example of the bit length of the entire t character compressed by the conventional Huffman code. 1: Basic clock generation circuit, 3 Near address counter, 4
: first ROM, 5: shift register, 6: start bit counter, 7: control device, 8: rank counter, 9: second ROM. 10: Column counter, ll: Row counter, 12: Latch circuit. Agent Patent attorney Aihiko Fukushi (and 2 others) Figure 7
Figure 2 Figure 3

Claims (1)

[Claims] 1. Character pattern data expressed using a dot matrix of M rows and XN columns is divided into submatrices of m rows and n columns to form subpatterns, and subpatterns are adjacent to each submatrix. Characters are compressed by variable length encoding using the pattern of the submatrix as a reference pattern in order of appearance frequency for the subpattern.
control circuit means for receiving variable length codes sequentially read out from the OM, detecting variable length codes for each sub-pattern, and outputting appearance frequency ranking data for each sub-pattern; and appearance frequency ranking data from the control circuit means. The decoding device is equipped with a second ROM into which the data and the dot data of the previously output sub-pattern (reference pattern) are input, and which outputs a dot pattern corresponding to the appearance frequency order with respect to the input reference pattern. As the variable-length code stored in the first ROM, a 1-bit code is assigned to the subpattern whose frequency of appearance ranks first, and k is an integer when the frequency of appearance ranks second and higher. As such, a (k+2) bit length is assigned to ranks 2k and (2k+1), and a code indicating the end of the bit length is assigned to the last bit, and a bit to distinguish between ranks 2k and (2k+1) is assigned to the second bit. A character pattern data compression method characterized by: