JPS62159519A - Method and apparatus for error correction - Google Patents

Method and apparatus for error correction

Info

Publication number
JPS62159519A
JPS62159519A JP52686A JP52686A JPS62159519A JP S62159519 A JPS62159519 A JP S62159519A JP 52686 A JP52686 A JP 52686A JP 52686 A JP52686 A JP 52686A JP S62159519 A JPS62159519 A JP S62159519A
Authority
JP
Japan
Prior art keywords
decoder
error correction
error
decoding
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP52686A
Other languages
Japanese (ja)
Inventor
Nobukazu Doi
信数 土居
Moriji Izumida
守司 泉田
Seiichi Mita
誠一 三田
Yoshizumi Eto
江藤 良純
Fuyuki Inui
乾 冬樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP52686A priority Critical patent/JPS62159519A/en
Publication of JPS62159519A publication Critical patent/JPS62159519A/en
Pending legal-status Critical Current

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  • Error Detection And Correction (AREA)

Abstract

PURPOSE:To prevent an error from being overlooked by controlling an area to be corrected not by correction but by replacement depending on the occurrence state of the error. CONSTITUTION:A reproduced digital signal inputted from an input terminal 1 is subjected to 1st stage decoding by a decoder 2 in the row direction at first. Then the 2nd stage of decoding is applied by using decoders 3-5 taking error correction word number in the column direction as 4, 3, 2 based on the result of decoding and the decoding data is stored respectively in memories 6-8. A counter 9 calculates number of columns not corrected by the decoder 4 in the column direction at each, e.g., unit of product sign. Then a selector 10 selects any of the memories 6-8 by using a count C and a decoded data is outputted from an output terminal 11.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は誤り訂正方法及びその装置に係り、誤訂正確率
を低減したままで訂正能力を増大でき、コンパクトディ
スクやデジタルVTRなどに好適な誤り訂正方法及びそ
の装置に関する。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an error correction method and device thereof, which can increase the correction capability while reducing the probability of error correction, and is suitable for compact discs, digital VTRs, etc. The present invention relates to a method and an apparatus thereof.

〔発明の背景〕[Background of the invention]

近年、誤り訂正符号はコンピュータ用記憶装置から家庭
用オーディオ機器に至るまで広く用いられるようになっ
てきた。第3図は記録又は送信すべきディジタルデータ
30に対し、誤り訂正用パリティ31.32を2次元的
に付加した積符号と呼ばれる誤り訂正符号の構成を示し
たものである。
In recent years, error correction codes have become widely used in everything from computer storage devices to home audio equipment. FIG. 3 shows the structure of an error correction code called a product code in which error correction parities 31 and 32 are two-dimensionally added to digital data 30 to be recorded or transmitted.

積符号に関しては、例えば常用等の「符号理論」昭晃堂
発行第73ページに詳しく説明されている。
Product codes are explained in detail in, for example, the 73rd page of "Coding Theory" published by Shokodo.

第3図の]マスは複数ビットのデータからなり、以後こ
れをワードと呼ぶ。このように符号化した積符号を矢印
に示す順序で記録又は送信する。
The square in FIG. 3 consists of multiple bits of data, and is hereinafter referred to as a word. The product codes encoded in this way are recorded or transmitted in the order shown by the arrows.

以下、積符号の復号手順を示す。まず、各行ごとに誤り
訂正用パリティ31を用いて誤りを訂正する。訂正能力
を上回る誤りが発生した場合は、その行に含まれる全て
のワードを不確かとし、各ワードに不確かさを示すフラ
グを付加する。つぎに、各列ごとにフラグと誤り訂正用
パリティ32を用い誤りを訂正する(イレージヤ訂正と
いう)。
The decoding procedure of the product code will be described below. First, errors are corrected using the error correction parity 31 for each row. If an error that exceeds the correction ability occurs, all words included in that line are made uncertain, and a flag indicating uncertainty is added to each word. Next, errors are corrected for each column using a flag and error correction parity 32 (referred to as erasure correction).

訂正可能な場合は誤りを訂正すると共に、その列のワー
ドのフラグを除去する。訂正能力を上回る場合はその列
の全てのワードにフラグを付加する。
If correctable, the error is corrected and the flag for the word in that column is removed. If the correction capacity is exceeded, a flag is added to all words in that column.

最後にフラグのないワードはそのまま出力し、フラグの
付いたワードは例えば1フイールド前の相関の高いワー
ドで置き換えることで誤りを修整した後出力する。
Finally, words without flags are output as they are, and words with flags are output after correcting errors by replacing them with, for example, a highly correlated word from one field before.

上記誤り訂正手順を詳しく述べた例として、例えば特開
昭57−10557号公報、特開昭57−10558号
公報、特開昭57−10559号公報、特開昭57−1
0560号公報、特開昭57−10561号公報等があ
る。
Examples of the above error correction procedure described in detail include, for example, JP-A-57-10557, JP-A-57-10558, JP-A-57-10559, and JP-A-57-1.
0560, JP-A-57-10561, etc.

一般に画(音)質の劣化は、正しくない訂正をする場合
と訂正せず相関の高い信号で置換する場合に起こる。ま
た、これらは二律背反関係にあり、単純に片方の劣化を
少なくすれば同時にもう片方の劣化が多くなってしまい
、両立の劣化を共に少なくすることは容易ではない。し
たがって、上記誤り訂正方法では、正しくない訂正によ
る劣化と置換による劣化が共に許容レベル以下に低減さ
れておらず、ディジタルVTRやコンパクト・ディスク
など高側(音)質の要求される機器に対しては依然問題
が残されていた。
In general, deterioration in image (sound) quality occurs when incorrect correction is made or when a highly correlated signal is substituted without correction. Furthermore, these are in an antinomic relationship, and simply reducing the deterioration of one will simultaneously increase the deterioration of the other, so it is not easy to reduce both of the deteriorations. Therefore, in the above error correction method, both the deterioration due to incorrect correction and the deterioration due to replacement are not reduced to below the allowable level, and it is difficult to reduce the deterioration due to incorrect correction and the deterioration due to replacement to below the allowable level. There still remained problems.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、誤りの発生状態に応じて誤りを訂正す
る個数を制御し、誤りの見逃しや不必要な置き換えによ
る修整をなくした誤り訂正方法及びその装置提供するこ
とにある。
An object of the present invention is to provide an error correction method and apparatus that controls the number of errors to be corrected depending on the error occurrence state, and eliminates missed errors and corrections due to unnecessary replacement.

〔発明の概要〕[Summary of the invention]

第3図の積符号において、誤りの見逃しは各行でとに行
う復号で訂正能力を上回る数ワード以上の誤りが発生し
たにもかかわらず、例えば1ワード以下の軽微な誤りが
発生した(以後誤りの見逃しと呼ぶ)とするとき起こる
In the product code shown in Figure 3, missed errors are caused by decoding performed on each row, which causes a slight error of one word or less (hereinafter referred to as error This happens when you miss something (called an oversight).

このような誤りの見逃しは、数100〜数1000ビツ
トに及ぶ長く連続したバースト誤りが発生したときに限
る。また、行方向の復号で誤りを見逃した場合、列方向
の復号は誤りを見逃さない場合に比べ訂正能力を上回る
誤りが発生するとしたり又は複数ワード以上の誤りが発
生したとなる確率が高くなる。したがって、積符号の列
方向の復号で訂正できなかったり、又は複数ワード以上
の誤りが発生したとなる列の数を計数することで、行方
向の復号で誤りの見逃しがあったが否かが判る。
Such errors can only be overlooked when long, continuous burst errors of several hundred to several thousand bits occur. In addition, if an error is missed by decoding in the row direction, there is a higher probability that an error exceeding the correction ability will occur or an error of multiple words or more will occur in column direction decoding than when no error is missed. . Therefore, by counting the number of columns that cannot be corrected by decoding the product code in the column direction or in which an error of multiple words or more has occurred, it is possible to determine whether errors were missed in the decoding in the row direction. I understand.

よって、計数値により列方向で訂正する誤りワード数を
変えることで、誤りの見逃しや不必要な置き換えににる
修整を少なくすることができ、それに伴なう画(音)質
の劣化を少なくできる。具体的には、計数値が少ない時
には訂正可能とする誤りワード数を多くシ、計数値が多
くなるに従い順次訂正ワード数を少なくする。
Therefore, by changing the number of error words to be corrected in the column direction based on the count value, it is possible to reduce corrections caused by overlooking errors or unnecessary replacement, and to reduce the accompanying deterioration in image (sound) quality. can. Specifically, when the count value is small, the number of error words that can be corrected is increased, and as the count value increases, the number of correctable words is sequentially decreased.

〔発明の実施例〕[Embodiments of the invention]

第3図に示す積符号を、1ワードを8ビツトとする拡大
体0F(2δ)上のリード・ソロモン符号により、行方
向で32ワードの情報に対し4ワードのパリティ部を付
加し、列方向では28ワードの情報ワードに対し4ワー
ドのパリティ部を付加することで構成した場合を考える
。この場合、行方向の復号は2ワード以下の誤りが訂正
できる。
The product code shown in Figure 3 is a Reed-Solomon code on an extended field 0F(2δ) where one word is 8 bits, and a 4-word parity part is added to 32 words of information in the row direction, and a 4-word parity part is added in the column direction. Let us now consider a case in which a 4-word parity section is added to a 28-word information word. In this case, decoding in the row direction can correct errors of 2 words or less.

また、列方向の復号は行方向の復号結果を利用すること
で4ワード以下の誤りが訂正できる。しかし、実際は正
しくない訂正による誤りの見逃しを防止するため、例え
ば行方向の復号は訂正数を1ワード以下に抑え、列方向
の復号でも訂正数を3ワード以下にしている。
Further, in column direction decoding, errors of 4 words or less can be corrected by using the row direction decoding results. However, in practice, in order to prevent errors from being overlooked due to incorrect corrections, the number of corrections is kept to one word or less in row direction decoding, and three words or less in column direction decoding, for example.

本発明では、行方向の復号で訂正する誤りワード数は従
来と同じか又は多くする。列方向の復号は2段階に分け
て行う。第1段では誤り訂正能力に余裕を持つ例えば3
ワード以下の誤りを訂正し、訂正できなくなる列の数を
例えば1個の積符号を構成する28個の列ごとに計数す
る。第2段では、この計数値に基づき訂正する誤りワー
ド数を変え改めて誤りを訂正する。すなわち、計数値が
大きい場合は行方向の復号で誤りを見逃した確率が高い
ため、訂正ワード数を少なくすることで誤り検出能力を
高くし、誤りの1.逃しを少なくする。計数値が少ない
場合は行方向の復号で誤りを見逃した確率が低いため、
訂正ワード数を多くすることで誤り訂正能力を高くし、
訂正できない誤りを少なくする。具体的には、計数値を
Cと表すとき。
In the present invention, the number of error words to be corrected by decoding in the row direction is the same as or larger than the conventional method. Decoding in the column direction is performed in two stages. In the first stage, for example, 3
Errors smaller than a word are corrected, and the number of columns that cannot be corrected is counted for each of, for example, 28 columns constituting one product code. In the second stage, the number of error words to be corrected is changed based on this count value and errors are corrected anew. In other words, if the count value is large, there is a high probability that an error will be missed during decoding in the row direction, so by reducing the number of correction words, the error detection ability is increased and the error 1. Reduce misses. If the count value is small, the probability of missing an error in row direction decoding is low;
Increase the error correction ability by increasing the number of correction words,
Reduce uncorrectable errors. Specifically, when the count value is expressed as C.

第4図に示すように誤り訂正ワード数を定める。The number of error correction words is determined as shown in FIG.

第1図に本発明の実施例を示す。入力端子1から入力す
る再生ディジタル信号は、まず行方向の復号器2で第1
段の復号をする。つぎに、この復号結果に基づき列方向
の誤り訂正ワード数を4゜3.2とする復号器3,4.
5で第2段の復号をし、復号データをそれぞれメモリ6
.7.8に記憶する。カウンタ9は、例えば積符号単位
ごとに列方向の復号器4で訂正できなくなる列の個数を
計数する。そして、計数値Cにより第5図に示すように
セレクタ10でメモリ6.7.8のいずれかを選択し、
復号データを出力端子11から出力する。
FIG. 1 shows an embodiment of the present invention. The reproduced digital signal input from the input terminal 1 is first processed by the first decoder 2 in the row direction.
Decode the steps. Next, based on this decoding result, decoders 3, 4 .
5 performs the second stage decoding, and stores the decoded data in memory 6.
.. 7. Store in 8. The counter 9 counts the number of columns that cannot be corrected by the decoder 4 in the column direction, for example, for each product code unit. Then, as shown in FIG. 5, the selector 10 selects one of the memories 6, 7, and 8 according to the count value C, and
The decoded data is output from the output terminal 11.

第2図に本発明の他の実施例を示す。入力端子13から
入力する再生ディジタル信号は、まず行方向の復号器1
4で第1段の復号をする。つぎに、この復号データに基
づき列方向の復号器15で訂正ワード数を3とした第2
段の復号をする。計数器16は例えば積符号単位ごとに
列方向の復号器15で訂正不能となる回数を計数する。
FIG. 2 shows another embodiment of the invention. The reproduced digital signal input from the input terminal 13 is first input to the decoder 1 in the row direction.
4 performs the first stage decoding. Next, based on this decoded data, the column-direction decoder 15 performs a second correction with a correction word count of 3.
Decode the steps. The counter 16 counts the number of times that the decoder 15 in the column direction becomes uncorrectable, for example, for each product code unit.

そして、計数値により先はどと同様に列方向の復号器1
5で訂正する誤りワード数を設定し、改めて復号し、復
号データを出力端子17より出力する。
Then, depending on the count value, the decoder 1 in the column direction is
5 sets the number of error words to be corrected, decodes again, and outputs the decoded data from the output terminal 17.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、訂正せず置き換えにより修整する領域
を誤りの発生状態に応じて制御するため、置き換える領
域を小さくかつ誤りの見逃しをなくすことができる。
According to the present invention, since the area to be corrected by replacement without correction is controlled according to the error occurrence state, the area to be replaced can be made small and errors can be prevented from being overlooked.

【図面の簡単な説明】 第1図は本発明の一実施例を示す図、第2図は1.13
・・・入力端子、11.17・・・出力端子、2゜14
・・・行方向の復号器、3,4,5.15・・・列方向
の復号器、9.16・・・計数器、10・・・セレクタ
。 30・・・記録又は送信データ、31.32・・・誤り
訂正用パリティ。
[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 shows an embodiment of the present invention, Fig. 2 shows 1.13
...Input terminal, 11.17...Output terminal, 2゜14
... row direction decoder, 3, 4, 5.15 ... column direction decoder, 9.16 ... counter, 10 ... selector. 30...recording or transmission data, 31.32...parity for error correction.

Claims (1)

【特許請求の範囲】 1、誤り訂正符号の復号において、一定期間ごとに誤り
検出する回数を計数し、計数値により誤り訂正動作を制
御することを特徴とする誤り訂正方法。 2、特許請求の範囲第1項において、第1段の誤り訂正
及び検出する1個の復号器と、第2段の誤り訂正及び検
出する誤り訂正数の異なる複数個の復号器と、第2段の
復号器による誤り訂正データを記憶する回路と、第2段
の特定の復号器が誤り検出する回数を一定期間ごとに計
数する回路とを有し、前記計数値に応じて記憶回路に記
憶した複数組の誤り訂正データの中から1つを出力する
ことを特徴とする誤り訂正方法。 3、特許請求の範囲第2項において、第2段の復号器が
1つの復号器から成り、第1回目の復号はあらかじめ定
めた誤り訂正数で行い、第2回目の復号は計数値に応じ
同一復号器で誤り訂正数を変えて行うことを特徴とする
誤り訂正方法。 4、行方向の復号器と列方向の復号器と計数器とを有し
、あらかじめ定めた周期ごとに行方向の復号器が訂正不
能となる回数を計数し、計数値に応じて列方向の復号器
の訂正動作を制御することを特徴とする誤り訂正装置。 5、特許請求の範囲第4項において、訂正可能とする誤
りワード数の異なる複数個の列方向の復号器と、復号結
果を記憶するメモリを有し、列方向の復号器の復号結果
の中から計数値により1つを選択し出力することを特徴
とする誤り訂正装置。
[Scope of Claims] 1. An error correction method characterized by counting the number of times errors are detected every fixed period in decoding an error correction code, and controlling the error correction operation based on the counted value. 2. In claim 1, a first stage error correction and detection decoder, a second stage error correction and a plurality of decoders different in the number of error corrections to be detected, and a second stage error correction and detection decoder are provided. It has a circuit for storing error correction data by the decoder in the second stage, and a circuit for counting the number of times a specific decoder in the second stage detects an error every fixed period, and stores it in the storage circuit according to the counted value. An error correction method characterized in that one of a plurality of sets of error correction data is output. 3. In claim 2, the second stage decoder consists of one decoder, the first decoding is performed with a predetermined number of error corrections, and the second decoding is performed according to the count value. An error correction method characterized in that the number of error corrections is changed using the same decoder. 4. It has a row-direction decoder, a column-direction decoder, and a counter, and counts the number of times the row-direction decoder cannot make corrections at each predetermined period, and according to the counted value, the column-direction decoder An error correction device characterized by controlling a correction operation of a decoder. 5. In claim 4, a plurality of column-direction decoders each having a different number of correctable error words and a memory for storing decoding results are provided, and the decoding results of the column-direction decoders are An error correction device characterized in that an error correction device selects and outputs one of the following based on a count value.
JP52686A 1986-01-08 1986-01-08 Method and apparatus for error correction Pending JPS62159519A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52686A JPS62159519A (en) 1986-01-08 1986-01-08 Method and apparatus for error correction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52686A JPS62159519A (en) 1986-01-08 1986-01-08 Method and apparatus for error correction

Publications (1)

Publication Number Publication Date
JPS62159519A true JPS62159519A (en) 1987-07-15

Family

ID=11476212

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52686A Pending JPS62159519A (en) 1986-01-08 1986-01-08 Method and apparatus for error correction

Country Status (1)

Country Link
JP (1) JPS62159519A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995001008A1 (en) * 1993-06-21 1995-01-05 Oki Electric Industry Co., Ltd. Bit error counting method and counter
US5838697A (en) * 1995-12-15 1998-11-17 Oki Electric Industry Co., Ltd. Bit error counting method and counting technical field

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995001008A1 (en) * 1993-06-21 1995-01-05 Oki Electric Industry Co., Ltd. Bit error counting method and counter
US5838697A (en) * 1995-12-15 1998-11-17 Oki Electric Industry Co., Ltd. Bit error counting method and counting technical field

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