JPS6215890B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device, and particularly to a digital logic circuit suitable for monolithic integration.

As digital logic integrated circuits become LSIs, the number of internal nodes has increased dramatically, and testing methods for the entire LSI have become extremely complex, especially when these nodes include storage elements (state flip-flops, etc.). As is well known. An effective method for this purpose is to arrange the flip-flops at key points in the logic circuit and divide them into several groups, so that each flip-flop group can be used in a test operation mode that is different from the normal operation mode. A method of reading or rewriting the state of any flip-flop at any time by operating it independently as a shift register and outputting its clock input, data input/output, etc. to the outside (so-called scan pass method).
There is a known method to simplify testing by converting general sequential logic into combinatorial logic. This method is certainly extremely effective because it simplifies the LSI testing method, but the drawback is that the number of test input/output terminals increases significantly. This would not be noticeable if the large-scale logic circuit was constructed in the conventional manner, in which the basic unit was a printed circuit board with a large number of connector terminals, which was equipped with a low-integration scale integrated circuit. However, as the degree of integration of integrated circuits increases, there is no margin for the number of terminals, and this is extremely disadvantageous.

An object of the present invention is to provide an integrated circuit device that can perform multiple functions such as inspection without increasing the number of terminals.

Another object of the present invention is to provide an integrated circuit device that can allocate the maximum number of input and output terminals in the normal operation mode, which is the intended use.

An integrated circuit device, in particular a monolithic integrated circuit device, according to the invention has a plurality of flip-flops and a logic section, and the flip-flops are formed such that each flip-flop is connected to the logic section and connected to each other in series. The device is characterized in that the terminal for inputting data to the logic section and the terminal for inputting shift-in data to the flip-flop are made common, and switching of data input is controlled by a control signal and a clock signal. .

In the present invention, even if there are physically n input (output) terminals, if a separate function is assigned to each terminal depending on the logic state of one separate control terminal, for example, 1, 0, etc. We will focus on the fact that it functions as 2n terminals. Of course, consideration must be given to the allocation so that among the 2n functions, the first n and the last n are not used at the same time. This argument is easily m
This can be extended to the case of book control input. The present invention also applies to normal logic voltage ranges (for example, −0.5 ^V in TTL).
~ ^5.5.V ) If you use the so-called third value (for example, connect the inverter input terminals that operate at +8 ^V in parallel with the normal TTL input terminals) and use this as a mode control input, you will need to further improve the terminal efficiency. Focus on what you can improve on.

According to the present invention, the present invention has a plurality of input terminals, a plurality of output terminals, and at least one control terminal (mode control input terminal), and at least some of the input terminals and output terminals perform different functions in different operation modes. A digital integrated circuit controlled by the mode control input terminal is obtained. Furthermore, at least some of the input (output) terminals physically double as control terminals, function as input (output) terminals in one operating mode in the normal logic voltage range, and Alternatively, it is also possible to obtain a digital integrated circuit that functions as a control terminal by prohibiting one operation mode and activating another operation mode at the same time in a low constant voltage value range (hereinafter referred to as the third value). . Furthermore, such a digital integrated circuit includes at least one test operation mode in addition to the normal operation mode, and the latter is characterized in that the flip-flop is treated as a shift register and can be used for logic debugging or fault diagnosis. shall be. In other words, each flip-flop operates as a normal flip-flop in response to one or more clock inputs in the normal operation mode, and inputs and outputs data to and from the logic section, and in the test operation mode, shifts the input data to data. It functions as a shift register under timing control by a clock. Similarly, as a logic part, a set of one or more programmable AND logics ("AND array") or a set of OR logics ("OR array"), or an OR driven by one or more AND arrays.
In digital integrated circuits containing so-called PLA (programmable logic arrays),
The above AND array or
For OR arrays, AND term (OR
selectively activate a part of the following (1), (2), or (1).
Refers to both (2): (1) All ANDs except the selected AND (OR) term
(OR) term is inactivated so that the entire logic operates only with the selected AND (OR) term (controllable) (2) A separate state is provided for only the selected AND (OR) term. a selection circuit consisting of or including a shift register having parallel outputs such that the data is transmitted (observable) to a data output terminal, and inputs of the selection circuit in the test operation mode, that is, all activated inputs; It is also possible to obtain a (monolithic) digital integrated circuit in which at least some of the shift operation clock input, shift-in data, and data output have common terminals with inputs (outputs) in other operating modes.

Next, a first embodiment of the present invention will be described with reference to FIG. In this embodiment, some or all of a series of flip-flops are connected in series so that they can operate as a shift register. Of course, each of the flip-flops F/F1 and F/F2 is also connected to the logic section 30 and operated in cooperation with the logic section 30. A logic section 30 including combinational logic has inputs I ₁ , I ₂ , I _{3 connected to input terminals I 11 , I 12 , I 21 and outputs connected} to output terminals O ₁₁ , O ₁₂ respectively.
It has an output O ₃ connected to output terminal O ₂₁ via O ₁ , O ₂ and an AND gate A ₅ and an OR gate R. In addition, the logic section 30 and the flip-flop F/
It is connected to F1 by a write output _N11 and a read input _N12 , and is similarly connected to flip-flop F/F2 by a write output _N21 and a read input _N22 . In normal operation mode, these flip-flop F/Fs
1, F/F2 is connected to logic section 3 by input/output N ₁₁ to N ₂₂
0, and operates to define the state of the logic section 30.

Here, one input of these flip-flops F/F1 and F/F2 is connected to the clock input terminal _I22 , and the output _CLK1 of the AND gate _A2 whose other input is connected to the enable signal terminal C is used as the flip-flop. It is designed so that it can be provided as a clock ( _CLK1 ) for parallel operation for each bit of the flop. Further, the output CLK ₂ of an AND gate which receives the output of the inverter 11 connected to the enable terminal C and the clock from the clock terminal I ₂₂ can be given as a clock signal for the shift operation. When this clock CLK ₂ is applied corresponding to the enable high level, the AND gate A ₃ opens and the data applied to the input terminal I ₂₁ is applied to the flip-flop F/F 1 as shift-in data I ₄ . It will be done. The intermediate shift output _M4 of this flip-flop is input to F/F2, and is led out to the output terminal _O21 via an AND gate _A6 and an OR gate R to which an enable signal is input as shift out data _O4 . .
The enable terminal is now at a low level, and at this time, the clock CLK2 for shifting F/F1 and F/F2 is input to the terminal _I22 , and the input terminal
If shift data is given to _I21 , the gate
_A5 and _A4 are opened, and the gate _A6 of the output section is also opened, so that the two flip-flops F/F1,
F/F2 operates as a shift register. In this embodiment, as input/output terminals, appropriate input/outputs I ₃ and O ₃ of each system are used, and as clock CLK2 terminals, clock CLK1 for parallel operation of each bit of the flip-flop is used. The terminals are also used as input/output terminals, and the number of terminals can be reduced by switching them using the mode control input C.

Next, a second embodiment of the present invention will be described with reference to FIG. In this example, a so-called PLA (Programmable Logic Array) having an AND-OR array, which is the most common type of combinational logic, will be considered, and as a suitable example of converting this into a sequential logic, a part of the output of the OR array will be ANDed. Consider the case of feedback through a flip-flop to an array input.

Input terminals I ₁ to I ₁₆ and outputs Q ₁ to _{Q 8} of the flip-flop section 5 are input to the input buffer 1.
The output is input to the AND array section 2.
This AND array section has AND term outputs A ₁ to _{A 128} , and these AND term outputs A ₁ to A ₁₂₈ are input to the OR array section 3, and a part of the output of the OR array section is input to the flip-flop section 5. , and other outputs are outputted to output terminals O ₁ to O ₈ via an output buffer 4. Further, each of the output terms A ₁ to A ₁₂₈ of the AND array section 2 described above can be selected by the selection output of the shift register section 6. Any intersection point in the AND array and OR array can be programmed as indicated by a black circle. The black circles at the intersections are actually realized by elements such as transistors or diodes.

Data input DIA is given to the shift register section 6 from the terminal DI, and the output of the shift register section 6 is
DOA is led out to the output terminal DO via AND gate _A13 and OR gate _R20 . Here, the terminals DI and DO are also used as data input and output terminals of the flip-flop section 5. Block 6 is provided with a block enable ADE and a clock CLK3. The enable input terminal EN is input to the inverter 51 and the AND gate _{A11 .}
The other input is the output ADE of the inverter 51, and the output is sent to block 4 as its enable.
It is done so that it can be given as CE. ADE is connected to an AND gate _A10 , one input of which is connected to the main clock terminal CLK, so that the output of the gate _A10 can be applied to block 4 as a latch clock CLK0. On the other hand, the output of inverter 52 is output from block 6.
It is applied as a clock enable ADE and also to an AND gate _A12 whose one input is connected to the clock terminal CLK. The output of gate 12 is adapted to be applied to block 6 as clock CLK3. Here, the inverter 51 sets the third level to ADE in response to the enable input CE to block 4, and depending on whether the enable input terminal EN is at the normal level or the third level, the inverter 51 selects the normal operation mode or the AND term selection circuit of block 6. Switch between activated modes. In previous mode
Since ADE is at a low level and CLK3 is cut off, block 6 is inactive and block 4 is enabled, and in the rear mode, all shift register sections 6 are enabled. In this way, the block enable ADE allows the output latch clock to be
CLK0 and block 6 shift clock CLK3
Switching is performed. Thus, in the logic integrated circuit configured as shown in FIG. 2, the state of the flip-flop section 5 can be controlled and controlled during testing and debugging.
And array 2 is a problem along with observability.
and each term of OR array 3, especially each AND term (A ₁ ~
A ₁₂₈ ) controllability and observability. However, the former can be realized by the well-known shift register connection as described above, and the latter requires a mode in which the AND term selection circuit is operated by block 6. In this case, 128
It becomes possible to cause the bit shift register unit 6 to select any (plural) terms from each AND term.

As described above, the present invention appropriately utilizes the independent or third-level mode control input EN to allow multiple input/output signal terminals to be shared depending on whether or not the input/output signals are used in each operation mode. By doing so, the number of terminals in a monolithic logic integrated circuit can be reduced over a wide range and the number of terminals can be effectively utilized, so the effects of the present invention are enormous.

It goes without saying that the present invention is not limited to the embodiments described above, but can be widely applied to integrated circuits including flip-flops.

[Brief explanation of the drawing]

FIGS. 1 and 2 are block diagrams showing the configurations of integrated circuits according to first and second embodiments of the present invention, respectively. 30...Logic section, 1...Input buffer, 2...And array, 3...OR array, 4...Output buffer, 5
...flip/flop section, 6...shift register section.

Claims (1)

[Claims] 1. An input terminal for inputting a signal, a logic section connected to the input terminal, an output terminal for taking out the output of the logic section, a plurality of flip-flops, a clock signal input terminal, a control signal input terminal, A signal line connecting the plurality of flip-flops in series, a signal line connecting the flip-flops and the logic section, and a gate circuit connecting the series-connected flip-flops and the input terminal. , when the control signal is in the first state, the gate circuit is closed and the logic section and the flip-flop are connected.
The clock signal is applied to transfer signals between the flip-flop and the flip-flop, and when the control signal is in the second state, the gate circuit is opened and the flip-flop connected in series is operated as a shift register. An integrated circuit device characterized in that it gives the following.