JPS62157952A - Margin testing system for electronic equipment - Google Patents

Abstract

PURPOSE:To decrease the labor of an operator, to shorten a testing time and to prevent an artificial error by executing automatically a margin test in accordance with one margin pattern prepared and designated beforehand. CONSTITUTION:In a service processor 10, the device is equipped with an interface part 17, etc., of a processing device 11, a memory device 12, an electronic device which is a testing object. The set of a margin pattern composed of the assembling of the margin value to be set at respective parts of the electronic device which is the testing object is prepared beforehand, and this is accommodated at the memory device 12 as a list of the margin pattern. When the margin test is started, the set of the margin pattern accommodated in the memory device 12 is displayed at a displaying device 13, and in accordance with one margin pattern designated to the operator, the margin test is executed automatically. Thus, the labor of the operator is decreased, the testing time is shortened and the artificial error can be removed.

Description

DETAILED DESCRIPTION OF THE INVENTION One Industrial Field of Application of the Invention The present invention relates to a margin testing method for electronic devices.

Conventional technology Electric devices such as electronic meters are operated by intentionally changing the power supply type W, clock speed, etc. by a predetermined percentage from the standard value for various L1 purposes such as preventive maintenance and finding intermittent failures. Margin tests are being conducted to confirm normality/abnormality.

In this type of margin test, normally, margin values are sequentially set for each component of an electronic device and an IF permanent abnormality test is performed.

Problems to be Solved by the Invention Generally, electronic devices to be tested have different margin values depending on the function of each component. It is necessary to specify the margin test for each component to be tested one by one, which not only takes time and effort to set the margin value, but also requires the use of a car during the interruption of the operation of the power-off device during the test. There is.

Furthermore, since the margin values for each component are manually set, there is also the problem that errors in memory and errors in manual key operations are likely to occur.

Means for Solving the Problems A margin test method of the present invention that solves the problems of the prior art uses a set of margin patterns consisting of combinations of margin values to be set for each part of an electronic device to be tested. is created in advance and stored in the 4g device, and at the start of the margin test, a set of margin patterns stored in the storage device is displayed on the display device, and one margin specified by the operator is displayed.・It is configured to reduce operator effort, shorten test time, and eliminate human error by automatically executing margin tests according to patterns.

Hereinafter, the operation of the present invention will be explained in detail together with examples.

Embodiment FIG. 1 is a block diagram showing the configuration of a histopath controller 10 for carrying out a margin test method according to an embodiment of the present invention, together with an electronic device 1 to be tested.

In the service processor 10, 11 is a processing device, 12 is a storage device, 13 is a display section, 14 is a CRT;
5 is a keyboard, 16 is a keyboard interface section, and 17 is an interface section with the electronic device 6 to be tested.

There are generally multiple types of electronic devices to be tested, I, 2...m, each of which is composed of a plurality of parts 1a, ]b...1n, as represented by electronic device 1. has been done.

A set of margin patterns consisting of combinations of margin values to be set for each part of the electronic device to be tested is created in advance, and this is stored in the storage device 1 as a list of margin patterns.
It is stored in 2.

FIG. 2 is an example of a list of margin patterns stored in the storage device 12. Each pattern includes a margin pattern number, an identifier indicating whether it is a voltage margin test or a clock margin test, and margin values arranged in the order of component parts a, b, c...n in the electronic device. ff & has been made.

The margin pattern with pattern number (00) defines the contents of a clock margin test in which the clock speed of each component part a, b, . . . n is made 10% higher than the standard value, and the power supply voltage is not changed.

The margin pattern with pattern number [01] increases the voltage of component part a by 5% above the rated value, and increases the voltage of component part C and e by 5%.
The content of the voltage margin test is specified to reduce the power supply voltage by 5%. Note that the component part d to which the margin value "0" is set is not subject to the margin test, and thus operates at the standard voltage value.

The margin pattern with margin pattern number 02 specifies the content of the voltage margin test in which component parts a, c, and 6 are not subject to testing, and the power supply voltage of components 2 and d is increased by 10% and 5%, respectively. There is. One or more margin patterns are created for each electronic device to be tested. These margin patterns may be shared between two or more electronic devices under test.

The operator of this bisprocessor 10 is
A margin test is started in the service processor 10 by inputting a command to display a list of the name of the electronic device to be tested and a list of margin patterns from the service processor 5 . Upon receiving this command, the processing device 11 starts a margin test according to the procedure shown in the flowcharts of FIGS. 3 and 4.

In the first step 31, the processing device 11 reads out the list of margin patterns stored in the storage device 12 and transfers it to the display unit 13, thereby displaying it on the CRT 14.

When the pattern number is input from the keyboard 15 in the next step 32, the processing device 11 proceeds to step 33.
Then, the margin pattern with the input pattern number is received from the display unit 13 and held in the built-in register. The processing device 11 reads the margin value for the first component under test in the next step 34, and in step 3
In step 4, it is determined whether the set margin value is "0".

Treatment Tl! ! If the set margin value is not (0-1), the device 11 determines whether it is a voltage margin test or a clock margin test in the next step 36, and if it is a voltage margin test, it proceeds to step 37.

In step 37, the processing device 11 lowers the power supply voltage of the first component of the electronic device under test by the margin value via the electronic device interface section 17, and lowers the power supply voltage of the first component of the electronic device under test by the margin value. Standard values will be maintained.

In the case of a clock margin test, the processing device 11 proceeds from step 36 to step 38. The processing device 11 is
In step 38, the clock speed of the first component of the electronic device to be tested is increased or decreased by the margin value via the electronic device interface section 17, and the standard values are maintained for the other components.

When the processing device 11 determines in step 35 that the margin value is 10'', that is, that the first component is not subject to the machine test, the processing device 11 proceeds to step 39 and performs the next step in step 35. The margin value for sentence 4 in the constituent part is read and the process returns to step 35.

The processing device 11 proceeds from step 37 in FIG. 3 to step 40 in FIG.
Then, by collecting abnormality flags and the like in the component under test via the electronic device interface section 17, it is determined whether or not an abnormality has occurred.

When the processing device 11 determines in step 41 that no abnormality has occurred, the processing device 11 proceeds to step 42 and displays the CRT + 4-. An identifier for notifying IF status is displayed at a predetermined location of 1-. on the other hand,
When the processing device 11 detects in step 41 that an abnormality has occurred, it indicates the occurrence of an abnormality at a predetermined location of CR'F14+- via the display section 13 in step 43. ill! Displays the identifier that is known to the user.

These normal/abnormal identifiers are displayed as a square symbol directly below the margin value display area of the component under test.

In the next step 44, the identifier device 11 completes the margin test of the component under test by returning the voltage or clock speed of the component under test to the standard value via the electronic device interface section 17.

In step 45, the processing device 11 determines whether or not the margin test for the final component has been completed. If not, the processing device 11 returns to step 39, reads the margin test for the next component, and executes the process in step 45. Return to 35.

When the processing device 11 determines in step 45 that the margin test for the final component has been completed, it ends the test for one margin pattern.

1. In the above example, we have given an example of a general case in which the clock speed is tested for each component in the same way as for the voltage value, but for electronic devices where the clock speed cannot be changed for each component, The clock margin test may be performed on a portion or multiple constituent portions belonging to the same clock system.

In addition, we have illustrated the general case where there are multiple electronic devices to be tested and one of them is specified at the start of the test, but if the electronic device to be tested is
:l: Service Processor 1 If the electronic device to be tested is specified by the connection to the interface section of the setter, it is not necessary to specify the electronic device to be tested when starting the test.

As described in detail, the margin test method of the present invention creates a set of margin patterns in advance and stores them in the recording device, and when starting the margin test, displays the set of margin patterns on the display device. The margin test is automatically executed according to one margin pattern specified by the operator, which reduces the operator's effort and test time, and eliminates the possibility of human error. The effect of disappearing is produced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a service processor to which a margin test method according to an embodiment of the present invention is applied together with an electronic device to be tested. A conceptual diagram illustrating a list of margin patterns displayed on the CRT 14, and FIGS. 3 and 4 are flowcharts showing the procedure of an automatic margin test by the processing device 11 of FIG. 1. 10... Service processor, 11... Processing device, 12
...Storage device, 13...Display unit, 14...CRT, 15
・・Keyboard, 19・・Keyboard interface,
17...Electronic device interface section to be tested, 1-
m...Electronic device to be tested.

Claims (1)

[Claims] An electronic device that sequentially sets the operating voltage or clock speed of a plurality of parts constituting the electronic device to be over or under a standard value, and then tests whether the operation of the plurality of parts is normal or abnormal. In the margin test method, a set of margin patterns consisting of combinations of margin values to be set for each part of the electronic device to be tested is created in advance and stored in a storage device.
At the start of the margin test, a set of margin patterns stored in the storage device is displayed on the display device, and a margin test is performed on each component of the electronic device according to one margin pattern specified by the operator. A margin test method for electronic devices characterized by performing the following.