JPS62156816A - Patterning method - Google Patents

Abstract

PURPOSE:To contrive improvement in the efficiency of an integrated circuit by a method wherein the boundary, to be used for split drawing of an integrated circuit pattern, is selected and registered in advance as the proposed boundary for patterning field, and the size of the patterning field is variably set in accordance with said proposed boundary, and a patterning operation is performed. CONSTITUTION:The proposed position of the patterning field boundary to be set in the fundamental part of a repetitive pattern is selected using the graphic operation function in the system, and the determined proposed position of the patterning field boundary is indicated by a one-dot chain line 21. The setting of the patterning field is performed within the range of a data drawing-up program, to be used for an electron beam exposure device, in such a manner that the following two conditions are satisfied. They are the size of patterning field is set at the value of integral number times and one of the patterning field boundaries is set at the position of the patterning field boundary. A resist process is proceeded by the prepared data for the electron beam exposure device and the electron beam exposure device, and a semiconductor integrated circuit memory is formed. The patterning field provided as above-mentioned is indicated in the diagrams (a) and (b).

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of writing integrated circuit patterns using a charged particle beam.

[Technical background of the invention and its problems]

First, a conventional technique using a drawing method using charged particles will be explained. Charged particles are ejected from a source.

The trajectory is varied using a polarizer and imaged at the desired location on the wafer or mask using a magnetic or electrostatic lens.

At this time, the size of the area (this is called the drawing field) in which the charged particles can be deflected by the deflector is important.

There are limitations that come from the electron optics and electrical subsystems. Its size is smaller than the size of the semiconductor integrated circuit pattern. Therefore, in order to form one semiconductor integrated circuit pattern, the pattern must be divided into several parts. Therefore, in order to form semiconductor integrated circuit patterns using charged particles, it is necessary to connect the writing fields by mechanically moving the stage on which the wafer (or mask) is fixed. However, errors occur in the connection of the drawing fields, and pattern formation accuracy deteriorates. this is.

This is one of the biggest causes of deterioration in drawing accuracy that occurs when the above pattern forming method is used. The amount of variation in pattern dimensions caused by this is approximately 0.1 μm.

Up until now, charged particle lithography devices have often been used to create masks for optical reduction projection exposure. It didn't matter. However, with the miniaturization of elements, charged particle lithography equipment has a 1:1 ratio for X# exposure.
It is being applied to the creation of masks and the direct drawing of semiconductor integrated circuit patterns onto wafers, and in this case, the above-mentioned pattern dimensional errors are no longer within an acceptable range. In the pattern formation of a #-conductor integrated circuit memory, if the drawing field boundary is located in the channel part of the FgT that constitutes the memory cell, variations in the channel length of the PET will occur, and the current-voltage of the FET will vary. Variations in characteristics occur, causing deterioration in the performance of semiconductor physical memory.

Conventionally, in pattern formation using a charged particle drawing device,
No consideration was given to the method of setting the border position of the drawing field.

The problems with the prior art will be explained in detail with reference to FIGS. 2 and 3. FIG. 2 is a schematic diagram of a semiconductor integrated Fit circuit (for example, a semiconductor memory) having a reversible portion. FIG. 3 shows what the boundaries of the drawing field look like when the drawing field size is fixed and drawing is performed using a continuous stage movement type drawing apparatus.

The drawing field boundaries are indicated by straight lines in the figure. As seen in FIG. 3, since there is a mismatch between the size of the drawing field and the repetition pitch, the basic parts of the pattern repeats are cut off at various locations by the drawing field boundaries. In semiconductor integrated circuit memory, l
A collection of several memories that make up a bit is the basic part of the above repetition, and if the conventional technology is applied as is, the border of the drawing field will be the Fg that makes up the memory.
A case may occur in which the signal passes through the channel portion of T.

[Purpose of the invention]

The present invention improves the drawbacks of the conventional pattern forming methods described above, and an object of the present invention is to provide a pattern drawing method that improves the performance of integrated circuits.

[Summary of the invention]

According to the present invention, candidate positions for setting the drawing field boundaries are first selected and registered in the integrated circuit pattern.

When selecting this candidate position, appropriate criteria are set, such as selecting a position other than the gate of the FET and a position other than the structural capacitor. Next, when drawing the pattern,
The drawing field size is variably set according to the registered drawing field boundary candidate position, and pattern formation is performed.

For a portion where a pattern of the same shape exists with only one boring force, the above procedure can be more easily executed as follows. When determining the drawing field boundary candidate position.

■The size of the drawing field set in the repeating part is limited to an integral multiple of the pitch of the repeating pattern.

(2) In addition, at least one of the drawing field boundaries is set as the drawing field boundary candidate in (2) above.

The pattern formation of the repeating portion of drawing field boundary candidates in (2) above is performed while making the drawing field variable and satisfying the above two conditions (2) and (2).

The drawing field set in this way is shown in Figure 1 (a
) and shown in FIG. 1(b). These figures correspond to the model of a semiconductor integrated circuit memory shown in FIG.

This is an application of the present invention. Figure 1 (a) shows the drawing field set when using a step-and-+7-bit type drawing device, and Figure 1 (b) shows the case when using a stage continuous movement type drawing device. The drawing field set to is shown. The boundaries of the one-track field are shown by solid lines.

[Effects of the Invention] According to the present invention, the drawing field boundary automatically passes only through places where drawing precision is required. Therefore, the performance of the produced accumulator @ device is improved, and the manufacturing yield is also greatly improved.

[Embodiments of the invention]

A method for drawing a semiconductor integrated circuit memory pattern will be described below as an embodiment of the present invention. The gate length of FF3T included in one peripheral circuit section in a semiconductor integrated circuit memory is:
Compared to the gate length of the FET included in the memory section, the length is 30% -6 Therefore, the peripheral circuit section and the memory cell section do not require any drawing precision. Therefore, in this embodiment, the present invention was applied only to the memory cell portion.

As the drawing device, for example, an electron beam irradiation device R20 as shown in FIG. 81!4 is used. This electron beam irradiation device 2
0 is X-Y for fixing the object 10 to be drawn.

It has a stage 11. The X-Y stage 11 uses a drive mechanism 13 to move the object 1o to be drawn in its vertical and horizontal directions (
Hereinafter, they will be referred to as the Y direction and the X direction. ) at a predetermined speed. An electron gun 13 is provided above the XY stage 11 so as to face the surface of the object 10 to be drawn. Between the electron gun 13 and the XY stage 11 is a condenser lens 149 that focuses the electrons emitted from the electron gun 13 and irradiates the object 1o with a particle beam (ON).

Blanking electrode 35 that controls irradiation release (OFF)
.

Deflection 'wt poles 16 for scanning electrons are sequentially provided. Blanking 'gvL Kan 15, deflection electrode 16. The X-Y stage 11 is connected to a computer (not shown), and their operations are controlled according to pattern data input to the computer.

When exposing an integrated circuit pattern to a resist on a wafer, the stage 11 to which the wafer or mask is fixed is continuously moved, and in synchronization with the movement, the direction of stage movement (X direction and The electron beam is scanned in the orthogonal direction (Y direction).

However, along with this movement, the blanking electrode is controlled according to the input pattern data, and a desired pattern is exposed on the resist. In this way, one writing field on the wafer is 3! After the light.

The stage moves in the Y direction by the width of the previously drawn drawing field. By repeating these five operations, all desired patterns are exposed over the entire resist region on the wafer.

When carrying out the above-mentioned pattern writing, a function was added to the above-mentioned writing apparatus to make the size of the drawing surface field variable, but this was done by providing a non-drawing section within the scanning section of the electron beam. . To set the non-drawing section,
This is done by providing a region where electron beam irradiation is canceled in a part of the scanning section using the blanking pole 15 according to the instructions of the pattern data.In this way, the writing field size variable function is applied to the electron beam exposure apparatus. At the same time, input data for implementing the present invention was created.

The f'l: formation of this input data was performed as follows. The drawing field boundary candidate positions to be set in the basic portion of the repeating pattern were selected using a graphic arithmetic machine within the CAD system. FIG. 5 shows the basic part of the reusable pattern in the semiconductor integrated circuit memory created by the pattern drawing described above for 800 layers. The drawing field boundary candidate positions determined within the CAD system are shown in FIG. 5 by dashed lines.

In this example, the drawing field settings are as follows.

Two conditions, viz. ■Drawing field size An integral multiple of the refill pitch.

(2) Set one of the drawing field boundaries to the above-mentioned drawing field boundary position. This is done in the data creation program for the nucleon beam exposure apparatus so that the setting is set to 44.

A resist process is carried out using the thus-prepared data for the particle beam exposure apparatus and the above-mentioned particle beam exposure apparatus, and a semiconductor integrated circuit memory is produced.

There is a primary difference between the semiconductor integrated circuit memory fabricated by implementing the present invention and the semiconductor integrated circuit memory fabricated by the conventional method. In other words, bit defects (r
(including defects in time characteristics) is approximately 80% higher in the former than in the latter.
% reduction.

The cause of bit defects is not only the dimensional error occurring on the drawing field boundary, but also many other factors.

However, bit defects with the above-mentioned dimensional error of 1.0 times occur systematically, and have a fatal effect on the manufacture of semiconductor integrated circuit memories. therefore.

The fact that approximately 80% of such t-bit defects were repaired in the actual column clearly shows the effectiveness of the present invention.

[Other embodiments of the invention]

In the above-mentioned friend array, an actual example of the present invention was described using a raster scan type electron beam exposure apparatus with a continuous stage movement type. However, the method of the present invention is not limited to the above-described embodiment. For example, the present invention can be applied to a case where a step-and-repeat method for moving the sample stage is used and a single-beam exposure device using a vector scan method is used. The present invention can be applied to any pattern forming method that involves moving a sample when forming a pattern on a material (for example, a wafer or a mask).

Also, in the example described above, input data for the drawing device was created so that the invention could be implemented, and this was done on a computer separate from the drawing device.

However, the present invention is 5j! What are the detailed methods for applying this?

The arrangement is not limited to this column, and a human may select the drawing field boundary candidate position to be set in the repeating unit of the pattern.

Set the drawing field size to 11 to 11 on the drawing device.
This may be performed by a computer that controls the drawing device, or may be performed by providing a dedicated circuit within the electrical subsystem of the drawing device.

[Brief explanation of drawings]

FIG. 1 shows a drawing field set when the present invention is applied, (a) is a step-and-repeat method drawing device, (b) is a schematic diagram of a stage continuous movement method drawing device, and FIG. Figure 2 is a schematic diagram of an integrated circuit with repeated parts. Figure 3 is a schematic diagram of the drawing field set in the following cases using a drawing device with continuous stage movement and applying the conventional drawing method. 5 is a schematic diagram showing the configuration of an electron beam exposure apparatus used in an embodiment of the present invention, and FIG. be. A, B, C... 1 m portion without recesses... Basic unit of repeats, 10... Object to be drawn, 11... X
-Y stage, 13...electron gun, 14...magnetic lens. 15... Blanking electrode % 16... Deflection area 4.
20... Electron beam irradiation device, 21... Boundary of repeated portion, 22... Drawing field boundary candidate position. Agent Patent Attorney Nori Chika '11 Same as right
Kikuo Takehana Figure 1 Figure 2 Figure 3
Figure 4 Figure 5

Claims (1)

[Claims] A method for drawing an integrated circuit pattern on a sample using a charged particle beam, comprising the steps of: selecting and registering a boundary for dividing and drawing the integrated circuit pattern as a candidate for a drawing field boundary in advance; A pattern drawing method characterized by comprising the steps of: variably setting the size of a drawing field according to the registered boundary candidate and drawing a pattern.