JPS62154753A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To eliminate cross talk between blocks on one chip and to obtain an IC structure, which is operated at a high frequency and has high performance,by forming the width of an isolating region, by which the blocks are isolated, so that the width is far larger than the width of an isolating region, by which elements are isolated. CONSTITUTION:On one semiconductor chip, a block A, which comprises an element group forming one circuit, and another block B comprising an element groups forming another circuit are located. In this semiconductor integrated circuit device, a width D of an isolating region, by which the blocks A and B are electrically isolated, is made far larger than a width (d) of an isolating region, by which elements in the blocks A and B are isolated. For example, the D is about D=50-100mum, which is ten and several times the width d=3-5mum. At this time, an element isolating groove 4 and a wide groove 6 between the blocks are formed by the same etching processes. An element isolating (p) layer 5 and a block isolating (p) layer 7 utilizing a P-N junction are provided by the same diffusion process.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique for preventing crosstalk (mutual communication) between blocks in a semiconductor integrated circuit device.

[Background technology]

In semiconductor integrated circuit devices such as ICs and LSIs, when two or more different IOAs and Bs are electrically coupled, conventionally, each IC is formed on a separate semiconductor chip as shown in FIG. When electrically connecting external terminals (pads) by wire bonding, etc., parasitic resistance R
', and parasitic capacitance C', it is inevitable that gain will be lost at the coupling part.

Therefore, as shown in FIG. 9, the inventor of the present invention has studied an IC having a one-chip type structure in which two or more circuit blocks A and B are formed separately on one semiconductor chip. In such a one-chip type semiconductor device, the problem of gain loss at the junction between blocks is small, but it has been found that electrical mutual communication between different ICs (hereinafter referred to as crosstalk) becomes a problem. .

Usually, isolation regions are provided between elements and between blocks to electrically isolate the elements, and these isolation regions usually have a pn junction isolation structure or an isolation structure using an insulator by selective oxidation. Separate structures (isoplanar structures) that use these in combination are employed. (-Refer to page 111 of the July 1982 issue of Electronic Materials published by Kogyo Kenkyukai.) Figure 10 shows yet another technique studied by the present inventors, in which two integrated circuit blocks A and B are mounted on one semiconductor chip.
FIG. 3 is a partial cross-sectional view of a case where isolation regions using pn junctions and grooves are formed between transistors in each block.

However, if the ICs in the two blocks A and B separated by the separation region are used with completely different waveforms and different frequencies, for example, one block A forms a branch circuit that passes high-frequency current, and the other block B Now, it will be considered that when a sawtooth wave generation circuit is formed, crosstalk between blocks often occurs, such as a high frequency waveform from block A being mixed into the sawtooth wave of block B through the inside of the substrate on which the separation structure is formed. The result was clear.

That is, as shown in the equivalent circuit diagram in a part of the same figure, the transistors of block A and transistors of block B are coupled by capacitances C,,C, and substrate resistances n5sR's4, but in this case, C8 □ and Rin, □.

Since C82 and I'sz constitute a bypass filter, if the frequency of block A is high, the signal will be transmitted to block B.

Alternatively, even if the frequencies between blocks A and B are the same, if the phases are different, the signal will move from person to B and from B to A, and this effect will occur on the output of the transistor.

If the losstalk is extremely large, the board may be destroyed.

One way to prevent the above-mentioned inter-block crosstalk is to connect the Si substrate 1 between blocks A and 8 to the ground potential (GND), or to ) was also considered.

However, even with the above structure, when the frequency used in one block becomes higher than 10 MHv, it has been found that the above method cannot sufficiently deal with the above problem. This was done to overcome the

One object of the present invention is to provide a high-performance IC structure that eliminates crosstalk between blocks on one chip and can operate at high frequencies.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, one 3i semiconductor chip has one integrated circuit block and another integrated circuit block, and an isolation region using a pn junction and a groove is provided on the surface of the S+ substrate between these blocks, and the width of this isolation region is is formed much wider than the width of the isolation region between elements within the block. Alternatively, by connecting the Si substrate in the isolation region to the ground potential (GND), the impedance between blocks is increased, crosstalk between blocks is eliminated, and high frequency operation is possible, thereby achieving the above object.

[Embodiment 1] FIGS. 1 to 3 show an embodiment of the present invention. Among them, FIG. 1 shows a semiconductor in which two circuit blocks A and B are formed on one semiconductor chip. Overall plan view of the device,
FIG. 2 is a section view taken along line 1--1 in FIG. 1.

1 is a semiconductor substrate (p-type Si substrate), 2 is an epitaxial n3a layer, 3 is an n10 buried layer, 4 is an isolation trench between elements in blocks A and B, and 5 is an isolation trench 4 between elements.
A p-layer for nine-junction isolation is provided between the substrate and the substrate immediately below. 6
is a bottom groove for separating two blocks A and B. 7 is a p-layer for junction separation provided between the bottom groove 6 and the substrate 1.

As shown in the figure, the width of the isolation regions of blocks A and B is much larger than the width d of the isolation region between elements in each block. For example, D is about 10 times larger than 623-5 μm, that is, D=about 50-100 μm. The inter-element isolation trench 4 and the inter-block wide area 6 are formed by the same etching process.

The pms for isolation between elements and the p layer 7 for isolation between blocks are provided by the same diffusion process.

A part of the element isolation groove 4 extends to the collector side of one transistor, facilitating connection between the collector extraction n soil layer 8 and the n+ buried layer 3.

The base p-diffusion layer of the 9inprl transistor, and 10 the emitter n-diffusion layer.

Although not shown, the surfaces of the elements in each block are covered with an insulating film such as a Si#l film, and AI electrodes and Al wiring are connected through contact windows formed in this insulating film.

FIG. 3 is an equivalent circuit diagram of the electrical connection state of the inter-block isolation regions in FIG. 2.

npn in block AK) Collector (n0 buried layer) 3a of transistor QA is junction valley'! kC81 board impedance R'sat R541'271-Csz
, to Prolife-B' through npn,) 1
It is electrically coupled to the collector (n buried layer) 3b of the transistor QB. (Fig. 2), width of block separation area]),
By making it much larger than d, the impedance R'ss R34 becomes extremely large.

Further, by forming the bottom groove 6 in the inter-block isolation region, the longitudinal impedances Rs□ and R82 of the substrate are reduced by the depth of the groove (for example, about 0.8 μm). on the other hand,
The substrate resistance between blocks A and B, resistance R'ss l R84, increases, and the substrate resistance Rss also increases, and the parallel resistance value increases, but the impedance between the circuits increases, reducing the occurrence of crosstalk. K becomes.

[Embodiment 2] FIGS. 4 and 5 show another embodiment of the present invention, in which FIG.
5 is a plan view of the semiconductor device in which C blocks A and H are formed, and FIG. 5 is a sectional view taken along line V-V' in FIG. 4.

In FIGS. 4 and 5, reference numeral 11 is a metal film such as AI, which is formed directly on the semiconductor surface in the entrance 6 between wide blocks and on the peripheral area of each processor, and is formed through wiring, etc. It is connected to the ground potential (GND), or alternatively, to the power supply potential (Vcc). This metal coating 11 is formed simultaneously when forming the element electrodes of each block.

In FIG. 5, the same reference numbers are used for components common to FIGS. 1 and 2 of the first embodiment described above.

The metal coating formed in the bottom groove may be formed in a plurality of columns 12 instead of a single column as shown in FIG. 6, and these may be connected to the ground potential.

In a part of FIG. 5, an equivalent circuit of an electrically connected state of the inter-block isolation region is shown. The resistor in the figure shows a state of low impedance in the vertical direction of the board.

In this second embodiment, a wide #I
It is said to be #6. Furthermore, the ground potential G within this wide n6
A metal coating 11 connected to ND (or a semiconductor region connected to high potential VCC, not shown) is provided to stabilize the potential of the semiconductor substrate and prevent thyristors. Due to the wide isolation region and the bottom groove 6, the lateral impedance of the semiconductor substrate directly below it R'sa・R83′・R's4・R84/・
By raising R'ss, R'ss', and R'ss, it is possible to prevent crosstalk and oscillation.

This metal coating 11 also serves other functions. That is, in an IC sealed with an epoxy resin, an electric field may be generated between transistors QA and QB via the resin, and this may cause cyclotalk. This metal coating 11 is provided to prevent this electric field. Furthermore, this metal coating 11 reduces signals transmitted through parasitic capacitance and parasitic resistance (substrate resistance) to ground potential (high potential).
can be released to a fixed potential.

In this way, since crosstalk is less likely to occur between the two blocks, it becomes possible to manufacture an IC that operates at a high frequency, and it is expected that an IC with even higher performance will be realized.

In the future, the frequency bands of ICs will tend to increase to several hundred megabytes or more, and the present invention can be applied to such cases.

[Embodiment 3] FIG. 7 shows another embodiment of the present invention, and is a cross-sectional view in which a thick insulating film is formed in the isolation region between IC blocks in one semiconductor chip.

In the figure, %13.14 is a thick semiconductor (Si) oxide film, a so-called isoplanar oxide film.

This oxide film is formed by etching a wide isolation region between blocks using a Si, N4 film, etc. formed on the substrate as a mask, forming a bottom groove, and selecting it using the same mask made of Si, N4. It is formed by oxidation. An isolation p layer 5.7 is formed between the oxide film and the substrate by diffusing impurity boron implanted in advance from the bottom surface of the bottom groove.

Of these, the oxide film 14 and the 9th layer 7 in the inter-block isolation region
is formed in the same process as the oxide film 13 for element isolation and the second layer 5 in each block, and the width of the former is several times to ten times larger than the width d of the latter.

In each block, elements such as npn (npn) transistors are formed in each island region separated by an oxide film for element isolation and a p layer. Each component of these elements is shown in Examples 1 and 2 described above and in FIG. Components common to those in FIG. 5 use the same designation symbols.

According to this invention, by making the width of the inter-block isolation region sufficiently wide and forming an isoplanar oxide film in a wide area formed in this region, the intra-block isolation region The lateral impedance of the board 53 #R514 is set to be large, and on the other hand,
Block A due to small longitudinal impedance R31*R52.

The occurrence of crosstalk between circuits B can be significantly reduced.

In this invention, the formation of the bottom groove, p layer, and isoplanar oxide film of the inter-block isolation region can be performed by directly using the formation process of the element isolation groove, p layer, and oxide film in each block. This can be easily achieved without adding any new processes.

This invention has the advantage that the space on the oxide film in the interblock isolation region can be used for forming wiring, resistors, capacitors, and the like.

As above, the invention made by the present invention has been specifically explained based on the examples, but the present invention is not limited to the above-mentioned examples, and various changes can be made without departing from the gist thereof.

For example, the same effect can be achieved by forming the M coating provided on the surface of the inter-block separation region so as to completely surround one block (8), as shown in FIG.

〔Effect of the invention〕

Representative effects obtained by the invention disclosed in this application will be described.

(1) In an IC having at least two circuit blocks that process different operating frequencies or different waveforms, the isolation width between the circuit blocks is made larger than the isolation width between elements formed within each circuit block. By increasing the impedance between circuit blocks, crosstalk can be prevented, and circuit blocks that process different operating frequencies and different waveforms can be formed on the same semiconductor substrate.

(2) From (1) above, gain loss between circuit blocks can be reduced.

(3) In addition to (1) above, by forming a metal film connected to a fixed potential in the isolation region between circuit blocks, it is possible to more effectively prevent thyristors, crosstalk, etc. .

[Application field]

The present invention can be applied to all semiconductor devices having IC circuit blocks using a plurality of different waveforms and different frequencies on one substrate.

The present invention is particularly effective when applied to a semiconductor device having a circuit that partially operates at a high frequency.

The present invention is particularly advantageous when applied to a semiconductor device consisting of a plurality of blocks having isolation grooves 9 and isolation isoplanar oxide films between elements.

[Brief explanation of drawings]

FIG. 1 is an overall plan view of a semiconductor device showing an embodiment of the present invention. FIG. 2 is a sectional view taken along line nn' in FIG. 1. FIG. 3 is an equivalent circuit diagram showing the electrical state of the inter-block isolation region in FIG. 2. FIG. 4 is an overall plan view of a semiconductor device showing another embodiment of the present invention. FIG. 5 is a sectional view taken along the line v-v' in FIG. 4. FIG. 6 is a partial sectional view showing a modification of FIG. 5. FIG. FIG. 7 is a sectional view of a main part of a semiconductor device showing another embodiment of the present invention. FIG. 8 is a block diagram showing an example of combining two different circuit blocks formed on separate chips. FIG. 9 is a plan view (block diagram) showing an example in which two different circuit blocks formed on the same chip are combined. FIG. 10 is a sectional view showing an example of a conventional isolation region between two circuit blocks formed on the same chip. FIG. 11 is a plan view of a semiconductor device showing one of the conventional techniques for preventing crosstalk between blocks. FIG. 12 is a plan view of a semiconductor device showing an example of application of the present invention. Agent: Patent Attorney Katsuo Ogawa 7-＼、('、
1"'! Figure 3 Figure 8 Figure 11 Figure 12

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device in which one block consisting of a group of elements forming two circuits and another block consisting of a group of elements forming another circuit coexist on one semiconductor chip, , the width of the isolation region that electrically isolates the blocks is
A semiconductor integrated circuit device characterized in that the width is much larger than the width of an isolation region that isolates elements in each block. 2. The semiconductor integrated circuit device according to claim 1, wherein the inter-block isolation region and the inter-element isolation region are isolation regions using pn junctions. 3. A semiconductor integrated circuit device in which one block consisting of a group of elements forming one circuit and another block consisting of a group of elements forming another circuit coexist on one semiconductor chip. Isolation regions using pn junctions and grooves are formed to electrically isolate between other blocks and between elements within each block, and the width of the isolation region that isolates blocks is the same as the isolation region that isolates elements. A semiconductor integrated circuit device characterized by being formed much larger than the width of a region. 4. A semiconductor integrated circuit device in which one block consisting of a group of elements forming one circuit and another block consisting of a group of elements forming another circuit coexist on one semiconductor chip. Isolation regions using pn junctions and grooves are formed between other blocks and between elements in each block to electrically isolate them, and above each groove is a fixed potential. A metal film connected to a ground potential or a semiconductor region connected to a high potential is formed,
A semiconductor integrated circuit device characterized in that the width of the inter-block isolation region is formed to be much larger than the width of the inter-element isolation region.