JPS62154131A - Buffer memory device - Google Patents

Abstract

PURPOSE:To shorten the data reading time to an FIFO buffer by outputting selectively the data supplied to a separate register or the data stored in a buffer based on the number of writing signals and data stored in the buffer. CONSTITUTION:An input 11 is delayed by a clock by a register 20 and then inputted to a buffer 10. The outputs of the register 20 and the buffer 10 are inputted to a multiplexer 16 and an output 13 is outputted after selection. The contents of a writing pointer WP set within a control circuit 14 are delayed by a clock by a register 21 and sent to the buffer 10. Then the signal (a) is inputted to the multiplexer 16 from a unit number detecting circuit via an OR circuit 22. The output of a multiplexer 12 is selected in case >=2 pieces of data are stored in the buffer 10. While the output of the register 20 is selected if <=1 pieces of data is stored in the buffer 10. Furthermore the writing signal WE is inputted to the circuit 22 via a register 23 and an inverter 24.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field of the invention] The present invention is based on the first in fi
The present invention relates to a buffer memory device that can speed up the reading time from a buffer (st out).

[Technical background of the invention and its problems] Conventionally, for example, a 4-level FIFO buffer is
), it consists of a four-stage shift register, and the data is Ml, r2J.

When r3J and r4J were input, they were output in the order in which they were input.

Next, the detailed configuration of a conventional buffer memory device will be explained with reference to FIG. In Figure 4, 10 is 4
This is a FIFO buffer 7 memory composed of registers 101-104. Input signals 11 are respectively input to this buffer memory 10 .

The outputs of the registers 101 to 104 are each input to a multiplexer 12.
The data selected by is output as output data 13. By the way, 14 is a control circuit that controls writing to and reading from the buffer memory 10, and this control circuit 14 receives a write signal W.
E and read signal RE are input. This control circuit 1
4 is a write pointer WP that specifies which register to write to among the registers 101 to 104 when the write signal WE is input, and a write pointer WP that specifies which register to read from when the read signal RE is input. There are read pointers RP to
Each time E or read signal @RE is input, it is incremented and operated cyclically. Note that the signal from this read pointer causes the multiplexer 12 to
is operated. Further, the control circuit 14 is provided with a number detection circuit for detecting how many of the registers in the buffer store data. This number detection circuit is constituted by, for example, a 2-bit counter, and when the write signal WE is input, the counter is incremented by +1, and when the read signal RE is input, the counter is incremented by -1. In this way, the counter counts the number of data items stored in the registers in the buffer. Here, such a buffer 10 has RAM
If you want to store the real address read from (random access memory) and read the real address at the lowest level, place the lowest level near the RAM.
RAM access time can be shortened. However, due to space issues, there are cases where the RAM and buffer are located on separate boards. In such cases,
Since the propagation time of signals between boards and the timing of clock skew must be taken into account, there is a drawback that the RAM access time becomes long.

[Object of the Invention] The present invention has been made in view of the above points, and its object is to solve the problem of F I F O (first in first o
ut) An object of the present invention is to provide a buffer memory device that can speed up the reading time to the buffer.

[Summary of the invention! ! ] A buffer composed of a plurality of registers, a write pointer WP that specifies the write register that is incremented by the input write signal @W to the buffer, and a read that specifies the read register that is incremented by the read signal R. A control circuit having a pointer RP and means for detecting the national religion of the data stored in the buffer is provided, the control circuit delays the output of the write pointer WP and outputs it to the buffer, and is provided on the input side of the buffer. The data input to the spaced apart register or the data stored in the buffer is selectively output based on the write signal W and the number of data in the buffer.

[Embodiment J of the Invention An embodiment of the present invention will be described below with reference to the drawings. First, in the present application, the bottom level of the buffer is separated from each other as shown in FIG. 3(B).

That is, as shown in FIG. 3(B), for example, real address information output from the RAM is input to the spacing register 20. The output of the m register 20 is input to the buffer 10 and also to the multiplexer 16. Then, the multiplexer 16 selects one of the outputs of the spacing register 20 or the buffer 10, and outputs the output 13.

Next, a buffer memory device according to an embodiment of the present invention will be described with reference to FIG. 4 in Figure 1
Names that are the same as those in the figures are given the same numbers. First, input 1
1 is written into the register 20 in synchronization with the O-check signal CLK. That is, the input 11 is input to the buffer 10 after being delayed by one clock in the register 20. The output 201 of the register 20 and the buffer 11
The outputs of 0 are each input to a multiplexer 16, and are selected by this multiplexer 16 to output 13.
is output. Write pointer W in the superior control W circuit 14
The contents of P are read into the register 21 in synchronization with the clock signal CLK. In other words, the above write pointer WP
The contents are delayed by one clock in the register 21 and sent to the buffer 10. And this multiplexer 16
The signal a from the control circuit 14 is input via the OR circuit 22 . That is, the signal from the number detection circuit is used as the signal a. In other words, this signal a indicates that the number of data stored in the buffer 10 is "2".
When the number of data stored in the buffer 10 is greater than or equal to 1, the level becomes ``1''. In such a state, the output of the multiplexer 12 is selected as the output of the multiplexer 16. “1J(l
If li1 or less, the level is °°0'', in which case the output of the register 20 is selected as the output of the multiplexer 16. Roughly speaking, the write signal WE is synchronized with the clock signal @CLK. The output of the register 23 is then inputted to the OR circuit 22 via the inverter 24.

Next, how the buffer memory device according to the present application is used will be explained with reference to FIG.

As shown in the figure, the register 20 at the lowest level of the buffer is provided on the board A11l, and the registers at other levels are provided on the board B side.

For example, one field of a virtual address stored in the register 31 is sent to the RAM 32, converted to a real address, and stored in the register 20. The control information of the real address stored in this register 20 is sent to the random logic 33, and a predetermined condition, for example, logic as to whether the real address is in a writable area or not, is determined. The output of this random logic 33 is sent directly to the multiplexer 16 and the buffer 1
Sent to 0.

Next, the operation of an embodiment of the present invention configured as described above will be explained. First, in a state where no data is stored in the buffer 10, the data r is
A case where AJ is input will be explained. In this case 6
Since no data is stored in buffer 10,
Signal a is at the "O" level. By the way, the above data r
AJ is read into the register 20 in synchronization with the clock signal CLK. Here, as the write signal WE, “1′°
When the level signal is applied, the register 101 is designated by the write pointer WP of the control circuit 14, but the designation is delayed by one clock via the register 21 and then supplied to the buffer rlO. Therefore, data rAJ is written to the register 101. By the way, even if the write signal WE reaches a level of 1°, the signal is delayed by one clock via the register 23 and is inverted and input to the OR circuit 22, so that the output of the OR circuit 22 is is '''0°0° level. Therefore, multiplexer 16
The output on the register 20 side is selected by this. Therefore, the data rA stored in the register 20 as output 13
J is output. That is, when the number of data to be stored in the buffer 10 is "1", the input data is always stored in the register 20 and also in the register 101. Therefore, the data written to buffer 10 is "1"
In this case, the data is written to registers 101 and 20, and the data written to register 20 is read out as output data 13.

By the way, after the data rAJ is written into the register 101, the write signal WE becomes 0°0° level and the data 0 is written into the register 23 in synchronization with the clock signal CLK. As a result, the multiplexer 16 selects the output of the buffer ?1o. In this state, when reading the data rAJ written in the buffer 1o, the read signal @RE becomes the level signal @RE. This causes the read pointer RP in the control circuit 14 to
is incremented, register 101 is specified,
The data rAl is output via the multiplexer 16.

Next, a case where two data rAJ and r8J are inserted in a state where no data is stored in the buffer 10 will be described. First, the operation in which the first data rAJ is stored in the registers 101 and 20 is exactly the same as in the above case. Next, the self-imposed message @WE is sent to the control circuit 14.
As a result, the write pointer WP in the control circuit 14 is updated, and data rBJ is written to the register +02 in synchronization with the clock signal @CLK. In this way, when two pieces of data are written into the buffer 10, the signal a becomes the ``1°'' level. Therefore, multiplexer 16 selects the output of buffer 10.

Next, after the two pieces of data have been written into the buffer 10 as described above, when reading the data, a read signal RE is output to the control circuit 14.

As a result, the read pointer RP in the control circuit 14 is incremented. As a result, the data rAJ stored in the register 101 is selected by the multiplexer 12 and outputted via the multiplexer 16.

Next, when the read signal RE is outputted to the control circuit 14 again, the read pointer RP in the control circuit 14 is incremented. As a result, the data rBJ stored in the register 102 is selected by the multiplexer 12,
It is output via multiplexer 16.

According to the above embodiment, the random logic 33 can be added between the register 20 and the buffer 10, which are provided separately on the boards A and 8. Furthermore, if the input of the random logic is m, the number of outputs is 0 (n<
By m), it is possible to reduce the hardware amount of the buffer memory device.

[Effects of invention]

As described in detail above, according to the present invention, FIFO (fir
It is possible to provide a buffer memory device that can speed up the read time to a buffer (first in first out).

[Brief explanation of drawings]

FIG. 1 is a diagram showing a buffer memory device according to an embodiment of the present invention, FIG. 2 is a diagram showing an example using the same buffer memory device, and FIG. 3 (A) explains the function of a conventional FIFO buffer. Figure 3<8) is the FIF related to this application.
FIG. 4 is a diagram explaining the O buffer, and is a diagram showing the conventional FIFO buffer in detail. 10... Buffer, 12.16... Multiplexer, 14... Control circuit, 20.21.23... Register. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 Input Figure 3 Input Figure 3

Claims (3)

[Claims] (1) A buffer composed of multiple registers, a write pointer that specifies the write register that is incremented by the input write signal W to the buffer, and a read that specifies the read register that is incremented by the read signal R. a control means having a pointer and means for detecting the number of data stored in the buffer; a delay means for delaying the output of the write pointer and outputting it to the buffer; and a control means provided on the input side of the buffer. a separate register, a selection means for selectively outputting data from the separate register and data from the buffer, and selection of the selection means by the write signal W and a signal indicating the number of data stored in the buffer. 1. A buffer memory device comprising: means for creating a signal. (2) The circuit means outputs a selection signal for selecting the output of the buffer to the selection means when there are two or more pieces of data stored in the buffer. The buffer memory device according to scope 1. (3) the circuit means selects and outputs the data in the spaced register when the write signal W is output when the number of data in the buffer is "1" or less;
The above patent claim is characterized in that when the number of data in the buffer is "1" or less, after the write signal W is output, a selection signal for selecting the output of the buffer is output to the selection means. The buffer memory device according to item 1.