JPS6215151B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timing circuit, and its object is to provide an electronic timing circuit that prevents noise, bouncing, and chatter from switches and prevents logical malfunctions. It is on offer.

FIG. 1 shows the overall circuit of one embodiment of the present invention,
A frequency divider circuit 1 inputs an oscillation signal from a crystal oscillator clock from an input terminal 3 and divides the frequency to obtain a hammering period pulse signal, and a frequency divider circuit 1 which inputs an output from a predetermined frequency division stage of the frequency divider circuit 1 and divides the frequency. The oscillation section is composed of a frequency dividing circuit 2 for creating an audio clock signal using a mixing gate _OR1 . Frequency dividing circuit 2 is a counter
The divided output of B ₁ is used as the first audio frequency signal f ₁ output, the divided output of counter B ₂ is used as the second audio frequency signal f ₂ , and one audio frequency signal f ₁ is used as the -input of mixing gate OR _1. At the same time, the other audio frequency signal _f2 is directly input to the other input of the mixing gate _OR1 , and the OR gate output of the mixing gate _OR1 is taken out as an audio clock signal. 5 in the figure detects when the power switch (not shown) is turned on and outputs a pulse signal with a pulse width determined by the time constant of capacitor CX and resistor RX and the threshold level of inverter IN. It is a power-on detection section that
The initial output of the flip-flop FF ₁ is determined to be "1" by the pulse signal of the power-on detection section 5, and the counter C ₁ of the hour and number of strokes setting circuit 11 (described later) is set to "1".
Reset. Reference numeral 6 denotes an hourly signal generating circuit which operates when an hourly signal is input from the crystal clock.This hourly signal generating circuit 6 turns on the hourly signal switch _SW1 , which is a push button switch, at the same time as the hourly signal is input. A pulse signal is output to the second bit in the 3-bit shift register 6A. 7 is a time setting circuit, and when switch SW ₂ consisting of a push button switch is turned on, 2 is set in a 3-bit shift register 7A.
At the bit, a pulse signal is outputted to set the output of the flip-flop _FF1 to the "1" level. Shift register 6A of hourly signal generation circuit 6
The shift register 7A of the time setting circuit 7 is used to prevent malfunctions due to chattering or bouncing when the switch _SW1 or switch _SW2 is turned on. That is, for example, the time setting circuit 7
When the switch SW ₂ is turned on and off, as shown in Figure 2a, bouncing with a bouncing width Ba occurs when it is on, and bouncing with a bouncing width Bb when it is off.
bouncing occurs. Here, if the pulse width of the clock _P1 of the shift register 7A is T as shown in FIG.
Therefore, the bouncing widths Ba and Bb do not span two pulse widths. Therefore, in the shift register 7A, even if bouncing is detected by the clock, only one bit is output, and two bits remain "0", making it possible to prevent bouncing. By the way, the bouncing that occurs when the power is turned on is caused by the time constant τ ₁ of the power-on detection section 5 = RX・CX, the time constant τ ₂ of the hour signal generation circuit 6 = RY・CY, and the time constant τ ₃ of the time adjustment generation circuit 7. = τ ₁ for RZ・CZ
>> By setting τ ₂ and τ ₃ , even if the output pulse signals of the hour signal generation circuit 6 and the time adjustment generation circuit 7 are generated, the pulse signal of the power-on detection section 5 will eventually cause the flip-flop FF ₁ to be activated. The output can be set to the initial state of "1" level. FIG. 3 is a time chart of the signals of various parts when the switch SW ₂ of the time adjustment generation circuit 7 is turned on and off. In the figure, a shows the on/off state of the switch SW ₂ , and b shows the signal of the shift register 7A. Indicates input. Also, c in the same figure shows the clock _P1 of the shift register 7A, and d and e in the same figure show the clock P1 of the shift register 7A.
The Q ₁ output and Q ₂ output are shown respectively. Also, f, g in the same figure
1 and 2 respectively show the _1st and _2nd inputs of NOR circuit NOR ₁ and NOR circuit NOR ₂ , h in the figure shows the NOR circuit
The output α of NOR ₁ is shown, and i in the figure shows the output α of NOR circuit NOR _2.
The _figure j shows the output β of the NOR circuit NOR ₂ . 8 is a skip signal generation circuit;
Further, 9 is a stop signal generation circuit, and the switches of these skip signal generation circuit 8 and stop signal generation circuit 9 are constituted by the c terminal and d terminal of the rotary switch RS, and when the rotary switch RS is switched to a predetermined terminal, generate a signal. The rotary switch RS separately has an a terminal and a b terminal, where the a terminal constitutes a switch for the continuous tapping sound generating circuit 10 used for adjusting the volume, etc., and the b terminal constitutes a switch for the time setting circuit 7. It is connected in series to SW ₂ , and when the time is set, it is possible to set the time by inputting it to this terminal. Reference numeral 11 denotes an hour striking number setting circuit, which inputs and counts the output signal (beating period pulse signal) from the frequency dividing circuit 1, and calculates the striking period pulse signal for time setting or the striking period for hourly hours. A predetermined number of pulse signal attenuation circuits 1
Set the output to 2. 13 is only the hitting sound at the end of the hit,
This is a delay circuit for processing the percussion period pulse signal in order to delay the percussion interval by half a beat from the previous percussion interval, and 14 amplifies the output signal of the attenuation circuit 12 and causes the speaker 15 to emit the percussion sound. This is an amplification section for

Next, the operation of a circuit according to an embodiment of the present invention will be explained.
Now, when the power switch (not shown) is turned on,
As shown in FIG. 4a, a pulse signal is generated from the power-on detection section ₅ , and as shown in FIG. Reset ₁ . Next, when the rotary switch RS is switched to the b terminal and the switch SW ₂ of the time adjustment circuit 7 is turned on, the pulse signal shown in Figure 4c is output from the time adjustment circuit 7, and the flip-flop FF ₁ outputs the "0" level. Invert. flip flop
When FF ₁ is inverted to “0” level, the data is transferred to shift register 1A of frequency divider circuit 1 and output to NOR circuit.
A pulse signal is output from NOR ₃ as shown in FIG. 4e to reset the frequency dividing stages FF ₁₄ to FF ₂₀ . Then, a moment later (in milliseconds) until the Q ₁₅ output of the frequency dividing stage FF ₁₅ reaches the "1" level, a hammering periodic pulse signal, which is the frequency divided output, is output from the NAND circuit NAND ₁ as shown in Figure 4 f. Furthermore, the NOR circuit of the delay circuit 13
The signal is outputted to the attenuation circuit 12 via NOR ₄ and NOR ₅ , which turns on and off the transfer gates TG ₂ and TG ₃ , and causes the speaker 15 of the amplification section 14 to sound. At this time, the audio clock signal from the frequency dividing circuit 2 is modulated by turning on and off the transfer gates TG ₂ and TG ₃ using the above-mentioned striking period pulse signal, and becomes a striking signal having a predetermined tone. Now, the above NAND circuit
The hitting sound period pulse signal outputted from NAND ₁ is simultaneously input to the hour-hitting number setting circuit 11. That is, at the time when the above-mentioned switch _SW2 is turned on, the counter _C1 is reset, and the hitting sound period pulse signal is inputted as shown in FIG. 4i. At this time, the output pulse of the NOR circuit NOR ₁ (Fig. 4c) sets the output of the flip-flop FF ₂₁ to the "0" level as shown in Fig. 4h, so that the hammering period pulse signal reaches the preset counter.
At the same time, the complement of _the data in counter _C1 is input to the preset counter.
Parallel set to each bit of _C2 . When the time setting is completed and the switch _SW2 is turned off, one pulse signal is outputted from the NOR circuit _NOR2 as shown in FIG. 4d, and the output of each bit of the counter _C1 is advanced by one. This is to set the counter C ₁ in order to strike the next time after the hour signal is received and the time is set. For example, when the time is set at 4 o'clock, the counter C ₁ is set. When five pulse signals are input, the flip-flop _FF1 is simultaneously inverted and its output is set to the "1" level.
Therefore, the output of the NAND circuit NAND ₁ exists, but
The output of the NOR circuit NOR ₄ , that is, the output of the percussion periodic pulse signal to the outside is stopped. FIG. 4g shows the output of the NAND circuit NAND ₂ . 4j to m show the _Q1 output, _Q2 output, _Q4 output, and _Q8 output of the counter _C1 .

Now, in this state, the hour signal is input and the NOR circuit NOR ₆ of the hour signal generation circuit 6 outputs a pulse signal as shown in Figure 5a, which inverts the flip-flop FF ₁ and sets its output to the "0" level. Then, as in the above-mentioned time setting, a pulse signal with a striking period is generated. At the same time, the flip-flop FF ₂₁ is inverted and the output is set to the "1" level, so that the striking period pulse is not input to the counter _C1 , but is input to the preset counter _C2 as shown in Figure 5b. The number of strokes setting circuit 11 is controlled. Now, as mentioned above, when the time is set, the complement of the data on the counter _C1 is set in parallel to each bit of the preset counter _C2 . There are five pieces of data for _1, ie, [0101], and therefore, in the preset counter _C2 , the complement number [1010] is set in parallel to each bit. Therefore, at the moment the flip-flop FF ₂₁ outputs the "1" level, the input C of the preset counter _C2 becomes the "1" level, and the Q of the counter _C2 becomes the "1" level.
Send one pulse to the output and count. Therefore, in order to count one hit sound period pulse signal before inputting it to the preset counter _C2 , each
The count contents of [1010] of Q ₈ , Q ₄ , Q ₂ , _and Q 1 become [1011], and after that, the count contents change to [1100] every time one hammering period pulse signal is input.
The preset counter _C2 functions as a subtraction circuit. Figure 5 c to f are preset counters.
Each bit Q ₁ , Q ₂ , Q ₄ , Q ₈ output of C ₂ is shown. That is, subtracting 5 from the initially set number (for example, 5's complement) becomes 0. For example, when striking 5 o'clock on the hour, if you want to distinguish the 5 hour sounds, or the "final sound" from other striking sounds, you need to use the 4 sounds before the "final sound". By using the eye bit output [1111] to detect the fifth note, it is possible to change the striking interval and decay time.
This [1111] is detected by the NAND circuit NAND ₃
When there is no bit output from the preset counter _C2 at [1111], an output is generated to the delay circuit ₁₃ as shown in FIG. 4. Stops the hammering periodic pulse signal outputted through ₄ . On the other hand, delay circuit 1
The NAND circuit NAND ₂ of No. 3 delays the "end-of-strike sound" by half a beat with respect to the interval between the previous strokes, at the same time as the NAND circuit NAND ₁ outputs the percussion period pulse signal. This circuit outputs a similar striking sound periodic pulse signal, and the hour striking number setting circuit 1
When the output shown in Figure 5g is generated in the NAND circuit NAND ₂ of 1, the output of the NAND circuit NAND ₂ is transferred to the flip-flop through the NOR circuit NOR ₃ as shown in Figure 5h.
2-bit counter C ₃ consisting of FF ₂₂ and FF ₂₃
This will be entered into. This counter _C3 switches the percussion period pulse signal from the NAND circuit NAND ₁ to the NAND circuit NAND ₂ , and at the same time, if this percussion period pulse signal is used for the percussion sound, the percussion sound will be output half a beat earlier. The tapping period pulse signal from this NAND circuit NAND ₂ is counted as shown in Figure 5 i and j, and the 2nd bit output, that is, a signal delayed by 1 bit from the preceding tapping period pulse signal is obtained. The output of this striking period pulse signal is input to the preset counter _C2 of the hour striking number setting circuit 11 via the NOR circuit _NOR5 , and the bit output is changed from [1111] to [0000]. shall be.
A signal is therefore generated from the NOR circuit NOR ₉ and input to the register 12A. The output of the register 12A generates an output in the NOR circuit _NOR7 as _shown in _FIG . By turning off the transfer gate TG ₁ , the resistor Rg is disconnected from the attenuation loop. That is, the attenuation circuit 12 includes a capacitor CO, a resistor Rh, and a resistor.
The attenuation loop is constructed from the parallel circuit with Rg, but when the resistor Rg is disconnected, its attenuation time constant becomes τ=CO·Rh, which increases the attenuation time. Therefore, the "end-of-stroke sound" detected by each bit output [1111] that is the counter content of the preset counter _C2 has a longer reverberation than the previous time-strike sound. At this time, at the same time as the hitting sound is output, a hitting sound stop signal is output by the Qg ₃ output of the register 12A, and the output state of the flip-flop FF ₁ is set to "1" level, and the NAND circuit
By closing the NOR circuits NOR ₄ and NOR ₈ , the output of the hammering periodic pulse signals from NAND ₁ and NAND ₂ to each part is stopped. At the same time, the above Qg ₃ output is output to the counter C ₁ , and the contents of the counter are set to the number of strokes at the next hour. At this time, the flip-flop FF ₂₁ is inverted and set to the "0" level, and the gate 16 is opened so that the contents of the counter _C1 are set in parallel to the preset counter _C2 . In this way, it stands by for the next hourly signal. Figure 5 k shows the output of the NOR circuit NOR ₉ , and Figure 5 l, m, and n represent the registers 12A each Qg ₁ , Qg ₂ ,
Qg ₃ outputs are shown, and the time scales of these m to o are expanding. Further, Fig. 5 p shows the striking sound when the time is set on the hour. In FIG. 1, P ₂ and P ₃ indicate clocks, respectively.

Conventionally, this type of electronic timing circuit, as shown in Figures 6 and 7, generates a noise pulse called bouncing when the capacitors CY and CZ connected to switch SW ₁ and switch SW ₂ are charged when the power is turned on. This pulse may cause the shift register 6A,
7A, there is a possibility that a pulse signal will be generated from the power-on detection section 5, the hour signal generation circuit 6, and the time adjustment circuit 7, and the switch SW ₁ and switch SW ₂ are also input in the same way. Chattering may also occur when the pulse signal is output from the power-on detection section 5, the hour signal generation circuit 6, and the time adjustment circuit 7 via the shift registers 6A and 7A. Consequently, these pulse signals have the disadvantage of causing logic malfunctions.

The present invention has been provided in view of the above-mentioned drawbacks.
A shift register of 2 bits or more is used as the signal generating means of the switch means for generating signals such as a time setting signal and an hourly signal, and the output of the hammering periodic pulse signal is performed by generating the second bit or more of the bit output of the shift register. In addition to using a gate circuit that inverts the output of the flip-flop to be controlled,
Means for setting the width of the clock of the shift register to be larger than the width of bouncing that occurs when the switch means is turned on and off; and power-on detection means for detecting power-on and generating a pulse signal for determining the initial state of the flip-flop. and means for setting the generation period of the pulse signal generated by the power-on detection means to be longer than the bouncing width that occurs when the switch is turned on, thereby eliminating chattering bouncing that occurs when the switch means is turned on and off. This has the effect of eliminating the cause of malfunction in terms of logic operation, and also detects power-on and switches on the time constant of the pulse signal that determines the initial state of the flip-flop that controls the output of the hammering periodic pulse signal. Since the width is set to be longer than the bouncing width that sometimes occurs, even if a noise pulse occurs due to bouncing, the initial state of the flip-flop can be set to the above pulse signal, and there will be no effect on the circuit. It has the effect of not giving.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG.
3, 4, and 5 are time charts for explaining the operation of the same as above, and FIGS. 6 and 7 are circuit diagrams of conventional examples, respectively, where 6A and 7A are shift registers, FF ₁ is a flip-flop, and P ₁ is the clock and T is the period.

Claims (1)

[Claims] 1. A sounding means for inputting an audio clock signal modulated by a striking period pulse signal as a striking signal and emitting a number of striking sounds corresponding to the number of striking period pulse signals; In an electronic time striking circuit having a time striking logic means for counting pulse signals to control the number of hour strikes to the current hour number and presetting the number of hour strikes corresponding to the next hour number, the time setting signal and the hour striking circuit are provided. The signal generating means of the switch means for generating signals such as signals includes a shift register of 2 bits or more, and an output of a flip-flop that controls the output of the percussion periodic pulse signal by generating the second or higher bit output of the shift register. In addition to using a gate circuit for inverting the clock, means for setting the width of the clock of the shift register to be larger than the width of bouncing that occurs when the switching means is turned on and off, and determining the initial state of the flip-flop by detecting power-on. An electronic timing circuit comprising: power-on detection means for generating a pulse signal; and means for setting the generation period of the pulse signal generated by the power-on detection means to be longer than the bouncing width generated when a switch is turned on. .