JPS62150599A - Memory circuit - Google Patents

Abstract

PURPOSE:To attain programming even after the assembling as a product by providing a control function required for programming only to one or plural terminals. CONSTITUTION:In applying a high voltage to a terminal DIN so as to turn on an ENH MOS transistors (IR) Q4, when an address signal A' is at a 'LOW' level, an ENH MOS TR Q5 is turned off, the level of a node N3 goes to a 'High' level and an ENH MOS TR Q6 is turned on. On the other hand, when the address signal A'i goes to a high level, the ENH MOS TR Q5 is turned on, the level of the node N3 goes to a 'LOW' level and the ENH MOS TR Q6 is turned off. When no programming is required, a voltage not turning on the ENH MOS TR Q4 has only to be given to the DIN terminal. That is, the DIN terminal has a control function required for programming. Thus, the programming is attained even after the memory circuit is assembled as a product.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory circuit in which all defects occurring during manufacturing can be repaired.

[Technical background of the invention]

Semiconductor memories have been increasing in capacity in recent years, but as the number of elements housed within a chip and the chip area have increased,
It is becoming increasingly difficult to obtain good products without defects. Therefore, all spare memory cells in addition to regular memory cells are used in advance in the chip, and if there is a defective regular memory cell (hereinafter referred to as a defective memory cell), the memory cell of the defective memory cell There is now a need for a semiconductor memory having a redundant configuration in which all chips including the defective memory cell can be repaired by replacing the defective memory cell.

First, a method for repairing a defective memory cell in a semiconductor memory having a redundant structure will be explained with reference to FIG. In FIG. 1, a semiconductor memory having a redundant configuration is a normal memory cell group 1. Spare memory cell group 2. 3. A defective address registration circuit in which the address of a defective memory cell is electrically programmed. and a comparison circuit 4 for comparing an external input address and the address of a defective memory cell. First, a functional test is performed on the normal memory cell group 1, and the address of a defective memory cell therein is identified. The address of the defective memory cell is then programmed into a defective address registration circuit having a programmable resistance element, such as a resistance element made of fusible polycrystalline silicon (hereinafter referred to as polysilicon), located within the same chip. The address of the defective memory cell is programmed depending on whether the polysilicon fuse is blown or not.

The operation of the semiconductor memory subjected to the relief treatment tLa- in this manner is as follows. In other words, the external input address and the address programmed in the defective address registration circuit are input to the comparison circuit, and if they do not match, the normal memory cell corresponding to the external input address is selected, and if they match, the normal memory cell is selected. A defective memory cell in the memory cell group is not selected, and a spare memory cell corresponding to the address is selected.

[Prior Art] The above is a method for repairing a defective memory cell in a semiconductor memory having a redundant configuration and its operation. Here, a conventional example of a defective address registration circuit to which the present invention relates will be explained using FIG. . In Figure 2, Ql is a terminal VI) I) which is necessary only when programming the drain, and a degradation type MOS with the gate and source as the gold node N0.
Q2 is a transistor (hereinafter referred to as a DEP type MOS transistor) with its drain connected to node N1. Enhancement type MO8 transistor (hereinafter referred to as ENH type MO8 transistor) whose source is the ground potential power supply GND, and the gate is input with a signal A/i (hereinafter referred to as address signal) generated in response to an external input address. Ashih Qa connects the drain to node N2. Connect the gate to node N1
．． It is an ENH type MO8) transistor whose source is the power supply GND, Pl is a polysilicon fuse connected between the power supply Vcc and node N2, and R1 is a terminal VpI) which becomes unused after programming is completed. It is a high resistance to prevent node N1 from floating when h R
2 is a high resistance for preventing the node N2 from becoming floating when the polysilicon fuse is blown.

A method of electrically programming the defective address registration circuit will be explained. First, the terminal vp is required only when programming.
When a voltage is applied to p, the address signal A/i becomes '''
LOW” when ENH type MO8) transistor (hH off L
, node NIU-High "7!: ft') E
N H type MO8) transistor Qxld is turned on and the power supply V
A current flows through the polysilicon fuse and melts it.

-When address signal A〆i is ``High'' ENH type M
O8 transistor Q2 is turned on and node N1 is @LOW”
Therefore, the ENH type MO8) transistor Qa fl is turned off. The polysilicon fuse P1 is not blown out because only a small current flows due to the high resistance R2 of the polysilicon fuse PI vcB.

In this way, the policy uses Pln address signal A' i
iE 'LOW' (Fuses when D"L,"
Since FIiptrl is not blown out, the address corresponding to the defective memory cell is programmed.

The terminal vpp is a terminal used only when programming the address of a defective memory cell mechanically, and is not used during subsequent wafer testing or post-assembly product testing. Therefore, in order to repair all defective chips, it is impossible to electrically program the defective memory cells after they are assembled as a product, and it is common to program the addresses of defective memory cells during wafer testing.

However, even if defective chips are repaired by programming during wafer testing, the number of defective memory cells often increases after assembly, and it is no longer possible to repair such products.

Furthermore, it is necessary to add a pad for the program-dedicated terminal VT)p on the chip, leading to an increase in the chip area.

[Purpose of the invention]

An object of the present invention is to improve such conventional drawbacks and to provide a memory circuit that can be programmed even after being assembled as a product without adding all terminals dedicated to programming in order to electrically program the address of a defective memory cell. It is about providing.

[Features of the invention]

The memory circuit according to the present invention has an address terminal, a data input terminal, a chip selection terminal, and a write control terminal, and includes a defective address registration circuit in which the address of a defective memory cell is electrically programmed, It is characterized in that the terminal has control functions required only during programming.

Alternatively, in the memory circuit according to the present invention, a defective address registration circuit consisting of the terminal and a group of ENH-type MO8 transistors having a first threshold voltage, It is characterized in that it has a high second threshold voltage and is connected via a second ENH type MO8 transistor whose gate and drain are common.

[Embodiments of the invention]

Next, an embodiment of the present invention will be described in detail using FIG. 3.

In the $3 figure, DIN is a data input terminal and also has a control function necessary only during programming.
5 is a data input buffer connected to the terminal DIN, and 6 is a defective address registration circuit. The defective address registration circuit 6 connects the drain to the node NSo and the address signal A'ii.
The first threshold (1st threshold) with the gate input and the source as the III source GND is the voltage VTtt-4 ENH type MO8
) Ranjith' Qs.

Connect the drain to node N4. Connect the gate to node N3. Threshold voltage vTt when the source is the power supply GND? Motsu ENH
Type MO8) transistor Q a + power supply Vcc and node N4
A high resistance R3 is connected between the node N3 and the power supply GND, and a high resistance R4 is connected between the node N4 and the power supply GND.

In addition, Q4 is set to a second threshold voltage ' which is sufficiently high compared to the first threshold voltage vTl.
The gate and drain of the S transistor are connected to the terminal DIN, and the source is connected to the node N3.

The operation shown in FIG. 3 will be explained. First, the case of programming the address of a defective memory cell will be described.

A high voltage is applied to the terminal DIN so that the ENH type MO8) run star Q4 is turned on. At that time, address signal A' i
Ka@LOW' TEL) f'LBAENHWMO8) Langister QI! is turned off, the fifth node N3 becomes ``High'', and the ENH type MO8) transistor Q6 is turned on.

Therefore, a current sufficient to blow out the polysilicon fuse flows from the power supply Vcc, and the polysilicon fuse is blown out. - 10,000 address signal A'i is “High” and n(l
-I'ENH type MOS transistor Qs is turned on, node N3 becomes "LOW", and ENH type MO8) transistor Q
sH off. Therefore, since only a small current flows through the polysilicon fuse through the high resistance Rak, the polysilicon fuse does not melt.

Also, when there is no need to program, connect ENH to the 1DIN terminal.
It is sufficient to apply a voltage that does not turn on the type MOS transistor Q4. In other words, the DIN terminal also has a control function necessary for the program. -For normal memory operation, a voltage within the allowable memory operation range is applied to the terminal DIN, so the ENH type MO8) transistor Q4G"C with a sufficiently high threshold voltage will not turn on. , the node N3 remains at -LOW''. Therefore, program information is not destroyed during normal memory operation.

In other words, the terminal DIN has the function of supplying the high voltage necessary for programming during programming.
In production, it functions as one terminal of the original memory.

〔Effect of the invention〕

Although the memory circuit of the present invention has been described above by taking the data input terminal as an example, it goes without saying that the memory circuit of the present invention can also be applied to other terminals within the memory circuit.

If the present invention is used, there is no need to add a dedicated program control terminal or power supply terminal for electrical programming, so the chip area does not increase. Furthermore, since it can be programmed even after it has been assembled as a commercial product, a higher yield can be obtained than when programming is done during wafer testing, which is very effective.

[Brief explanation of drawings]

FIG. 1 is a partial circuit diagram of a memory circuit in which a defective memory cell can be repaired. 1... Regular memory cell group, 2... Spare memory cell group, 3... Defective address registration circuit, 4... Comparison circuit second factor. 1 is a diagram showing a conventional defective address registration circuit. FIG. 3 shows a partial circuit 1 of the memory circuit of the present invention. 5...DIN buffer buffer...Failure address registration circuit s Qt...Depression type MOS transistor, Q2. Qa, Q4.
Qs, Qs...Enhancement type MO8)
Ransistor h "Is P2... Polysilicon fuse, R11, R2, R3, R14... Resistor, vpp... Program power supply terminal h Vccr
-G-ND...Electric, N1. N2. N3+N
4...Node. Not 2 yen 5 mouths

Claims (2)

[Claims] (1) In a memory circuit having an address terminal, a data input terminal, a chip selection terminal, a write control terminal, and a defective address registration circuit in which the address of a defective memory cell is electrically programmed, the one or more A memory circuit characterized in that its terminals have a control function necessary only during programming. (2) A defective address registration circuit composed of the terminal and a first enhancement type MOS transistor group having a first threshold voltage has a second threshold voltage higher than the first threshold voltage. 2. The memory circuit according to claim 1, wherein the memory circuit is connected via a second enhancement type MOS transistor having a common gate and drain.