JPS62149098A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent reduction of allowance of operation caused by fluctuation of power source, grounding level and substrate potential by making a writing system, especially a data in buffer operatable state after termination of operation of a sense amplifier and generation of sufficient differential potential in a pair of bit lines. CONSTITUTION:In a memory provided with a clock generator for controlling a row system, a generator that receives synchronizing signals from a column system and synchronizing signals and row address strobe signals from the column system and generates controlling clock of write enable system, the write system clock generator 5 is activated on receiving a signal S2 generated after forming sufficient differential potential between bit lines after termination of amplification of signals by a sense amplifier 10 out of signals of the column system clock generator 1. Thereby, more stable writing operation can be made without narrowing operational allowance of a data in buffer 6 due to fluctuation of power source, grounding level and substrate potential caused by discharging of many bit lines at the time of operation of the sense amplifier.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a write enable system control device for semiconductor storage devices, particularly semiconductor memories.

(2) Background of the Prior Art Conventionally, when writing to a semiconductor memory, a row or word line is selected, and then a column or bit line is selected.
In this way, a memory cell located at the intersection of these has been selected and writing has been performed to that cell. Figure 1 shows an overview of the circuit for cell selection and writing, where RAS is a row address strobe, and 1 is a RAS-related control such as address capture, decoder charge-up, and word line selection. , a generator that generates a clock for activating the sense amplifier, etc. 2 is R, A S
The system address buffer receives the row addresses Ao-Ai and sends these and their inverted signals to the row decoder ROWDEC.
Give to ODER. CAS is a column address strobe, 3 is a CAS clock generator, 4 is CA
In the S-based address buffer, column address Ao =
A i is received and sent to the column decoder COLUMN.
Give to DECODER.

The side lines of RAS and CAS indicate inversions of the RAS and CAS, and these are signals input from the outside.

As shown in FIG. 2, the first input is the RAS signal, and when this goes to LOW level, it becomes possible to take in the row address. Then, i.e. after time 'RCD, CAS
The signal becomes LOW and the column address can be read. WE is write enable (the meaning of the side lines is the same as before)
The LOW level of this signal, that is, the write cycle designation starts soon after the CAS flag becomes LOW level after the row address capture is completed. tW6□2,10, is RA
tWCll MIN is the period from when S becomes LOW until the end of the write cycle designation, and tWCll MIN is the period when CAS is 1. This is the period from when it becomes OW until the end of the designation that it is a write cycle. DIN is the write data and %tDH is the DIN acquisition period.

(3) Problems with the prior art In memory operation, the falling edge υ of the RAS signal and CAS signal is determined by the time required to ensure that each row and column address is captured in a MOS memory that performs address multiplexing. It needs to be off target. That is, if we give tRA (time) to fetch the row address, then change the address bus signal from the row address signal to the column address signal, and let δ be the time required for this switching, then CA
The S signal is similar to the RAS signal.'1 tRCD, Vll
It is necessary to delay by tRAII+δ.Then, the write cycle is specified and the write operation starts when the CAS signal becomes LOW level.
Since the RITE system starts, if this delay time is γ, then the RAS signal is tRCDmln+γ=tR
It starts with a delay of AH+δ+γ. As shown in FIG. 1, this means that the WRITE system clock generator 5
A signal S1 from a RAS-based clock generator 1,
Receive column address strobe CAS, Sl and CAS
This is because the cyclic clock generator is operated by the AND of and WE. At this time, the generation of rice fields is tR
CD IIIAX (RAS that can hold tARMIN)
(maximum value of CAS delay).

However, as semiconductor memories have recently become larger in capacity and faster, internal inductance and resistance components have become a hindrance to stable operation.

In other words, when a large current suddenly flows due to the inductance component associated with the structure, the power supply, ground level, and substrate potential fluctuate, reducing the operating margin and potentially causing malfunction.

In particular, in dynamic memory, a large number of bit lines discharge during sensing operation, and the resulting fluctuations in the power supply, ground level, and substrate potential cannot be ignored in circuit design. In a domain buffer that determines a TTL level input from the outside, for example, fluctuations in the ground level directly reduce the input determination margin. In the conventional write enable system, 'RCD min
Since it only starts after +γ time, by moving %tRcD, the activation of the data-in buffer will conflict with the operation of the sense amplifier, narrowing the operating margin of the data-in buffer. However, there was a problem in that the stability of the write operation was impaired.

(4) Purpose of the Invention The present invention aims to improve the above points and enable even more stable write operations.

(5) Structure of the Invention The structure of the present invention consists of a clock generator that receives 1 m of low-level 2 strobe signals and generates clocks for controlling row systems such as the row address buffer and sense amplifier, and column addresses for the 7-column address buffer, sense amplifier, etc. A clock generator that receives a strobe signal and a timing signal from the row system and generates a clock for controlling a column system such as a column address buffer, and the column address, etc., and a clock generator that receives a timing signal from the row system and a column address strobe signal, Data in buffer t:
In a semiconductor memory equipped with a clock generator that generates a control clock for which write enable system and the data main buffer, a signal from the low system is used as a signal for activating the write enable system after the data-in-back among the write enable systems. A timing signal of 1 is input, and the signal is generated after the signal has been amplified by the sense amplifier and a sufficient potential difference is generated between the bit lines. Let me explain this.

(6) Embodiment of the invention FIG. 3 shows an embodiment of the invention. The same parts as in FIG. 1 are given the same reference numerals, and 7 is a row decoder 8.
The di micro-column decoder is a word line booster circuit, and 10 is a timing signal from a sense amplifier 52iK low system.

The write system clock generator 5 is activated in response to the signal S2, which is generated among the signals of the row system clock generator 1, after the signal has been amplified by the sense amplifier and a sufficient potential difference has been generated between the bit lines. This is a feature of the present invention. Note that, compared with FIG. 4, a word line booster circuit and a sense amplifier are added, but these are the same as in the conventional circuit.

To explain the operation of the block diagram of the present invention shown in FIG.
Timing signal S of RAS system Wolf clock generator 1
, is input to the CA, S system clock generator 3,
The point that the CAS depth operates after the RAS system is activated is the same as in Figure 1, but the data in buffer 6 of the write system
Among the timing signals from the low system, the control circuit 11 receives a signal 81 which is generated after the signal has been amplified by the sense amplifier and a sufficient potential difference is generated between the bit lines. In this way, a write operation can be performed without narrowing the operating margin of the data-in buffer due to traceback caused by discharge of a large number of bit lines during operation of the sense amplifier, or fluctuations in the ground level or the substrate.

(7) Effects of the Invention As explained above, according to the present invention, the write system, especially the data-in buffer, becomes operational after the sense amplifier has finished operating and a sufficient potential difference has been generated between the bit line pair. This has the advantage of suppressing the reduction in operating margin due to fluctuations in the power supply, ground level, and substrate potential.

4 fffj J$ Explanation of the Drawings FIG. 1 is a block diagram showing a conventional example, FIG. 2 is a time chart for explaining operation, and FIG. 3 is a block diagram showing an embodiment of the present invention.

In the drawing, FtAS is a row address strobe, and 1 is RAS.
System clock generator, 2 is row address buffer C
ASid column address strobe, 4 is column address buffer, 3 is CAS system Kuko clock generator S
1 timing signal, WE is write enable A. -Ai is an address distance, 5 is a write enable system clock generator, 6 is a data in buffer WI, the first activation signal S2 of the write enable system is a timing signal, and 11 is a data in buffer system control circuit.

Pa) Agent Patent Attorney Susumu Uchihara　＼Month 7　Figure [−″−2 fan z diagram 6uRA□″□b-→

Claims (1)

[Claims] The present invention provides a clock generator that receives a row address strobe signal and generates a clock for controlling a load address buffer, a sense amplifier, and other row systems, and a clock generator that receives a row address strobe signal and generates a clock for controlling a load address buffer, sense amplifier, etc. A clock generator that receives timing signals and generates control clocks for column systems such as column address buffers, and the column address buffers, etc., and a clock generator that receives timing signals and column address strobe signals from row systems and generates control clocks for data-in buffers, etc. In a semiconductor memory equipped with a clock generator that generates an enable system control clock and the data in buffer, the write enable system after the timing data in buffer from the row system is used as a signal to activate the write enable system. A semiconductor memory characterized in that the signal is generated after the amplification of the signal by the sense amplifier is completed and a sufficient difference in potential is generated between the bit line pair.