JPS62145917A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a large current output without increasing the occupied area of an output stage by adopting the constitution that a gate-source voltage of an open drain type output P-MOSFET of a complementary MOSFET integrated circuit is increased by other power voltage. CONSTITUTION:In applying an L level to a point 1 being an input terminal of an output stage from the complementary MOSFET integrated circuit, a high dielectric strength P-MOSFET 2 is conductive and a high dielectric strength P-MOSFET 5 is nonconductive, and an output terminal 6 is pulled down to the 3rd power supply potential fed to an external power terminal 8 lower than a ground potential by a resistor 7. In applying an H level to the point 1, the high dielectric strength P-MOSFET 2 is nonconductive and the high dielectric strength P-MOSFET 5 is conductive and a current flows from the 1st power supply 9 to the output terminal 6. Since the 3rd power potential lower than the ground potential is fed to the external power terminal 8 in this way, the said current is increased. Further, components having the same function as resistors 3, 7 may be used in place of them.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a complementary semiconductor integrated circuit consisting of a p-channel field effect transistor and an n-channel field effect transistor, and particularly relates to a high breakdown voltage in the output stage thereof. The present invention relates to a semiconductor integrated circuit having an open-drain output transistor using a p-channel field effect transistor.

[Conventional technology]

FIG. 4 is a circuit configuration diagram of an output stage section showing a conventional semiconductor integrated circuit. In the figure, 6 is an external output terminal, and 7 is a resistor connected between the external output terminal 6 and the external power supply terminal 8, respectively. In addition, the drain of 5 is the external output terminal 6
A high-voltage p-channel field effect transistor (hereinafter referred to as MO) is used as an open-drain output transistor whose gate is connected to the contact 4 and whose source is connected to the first power supply 9.
8FET). 2 is a p-channel MO8FET whose drain is connected to the contact 4, the source is connected to the first power supply 9, and the gate is connected to the contact 1, and 10 is a p-channel MO8FET whose drain is connected to the contact 4.
These are n-channel MO8FETs whose source is connected to the second power supply 11 and whose gate is connected to the contact 1.
Channel MO8FET2, n-channel MO8FET1G
constitutes an inverter as a logic gate before the output transistor. Note that the first and second power supplies 9, 1
1 applies similar potentials to the sources of p-channel and n-channel MO8FETs constituting the complementary MO8 circuit in addition to the logic gate.

Next, the operation of the above circuit will be explained. Here, the contact 1 is normally applied with a high level potential (hereinafter referred to as H level) of the first power source 9 or a potential of the second power source 11 (hereinafter referred to as L level). When contact 1 is at L level, p-channel MO8
FET 2 is conductive, n-channel MO8FETIO
is in a non-conductive state, and contact 4 becomes H level. At this time, there is no difference between the gate voltage and source voltage of the high voltage p-channel MO8FET 5, and the p-channel MO8FET 5 is not in a non-conducting state. It is pulled down to the potential of a third power supply (not shown) which is more negative than the potential of No. 11.

When contact 1 is at H level, p-channel MO8FET2
is non-conductive, n-channel MO8FETIO is not conductive, and contact 4 is at L level. At this time, the high voltage p-channel MO8FET 5 is not conductive, and a current flows from the first power supply 9 toward the output terminal 6. This current IDS is
The voltage of the first power supply 9 is VDD.

The voltage of the second power supply 11 is VS S, and the voltage of the third power supply applied to the power supply terminal 8 is VL)sP channel MO8FE'l'5
Let vth be the threshold voltage of
)(vDn-VOCUT)-VDD votr'r
) ) m 11 @ a e (represented by 11. However, W and L are each p-channel MO8FE
Since the channel width and channel length of T5 are K, if it is necessary to flow a large amount of current, the channel width W of the oven-drain output transistor must be increased, and therefore the area occupied by that output transistor is υ
However, there were problems such as high manufacturing costs.

This invention was made to solve the above-mentioned problems, and it is possible to increase the current that can flow through the open-drain output transistor using a high-voltage p-channel MO8FET, and to reduce the manufacturing cost by reducing the area occupied by this output transistor. The objective is to obtain a semiconductor integrated circuit that can be made inexpensive.

[Means for solving problems]

A semiconductor integrated circuit according to the present invention includes an open-drain output transistor formed of a high-voltage p-channel MO8FET and a front-stage logic gate to which the output is connected to the gate thereof, and a first logic gate to which the source of the p-channel MO8FET is connected. In a complementary semiconductor integrated circuit having a second power source connected to the source of an n-channel MO8FET, the logic gate has the same polarity and high breakdown voltage as the output transistor, and the source is connected to the output transistor. Consisting of a driving transistor whose drain is connected to the gate of the output transistor at the same potential as the source, and a resistor or a first load element having an equivalent function whose one end is connected to the drain of the driving transistor. One end of a second load element having the same function as the first load element is connected to the drain of the output transistor, and an output terminal is connected to the drain of the output transistor, and the first and second load elements are connected to each other. The other ends of the two load elements are commonly connected to a power supply terminal, and this power supply terminal is connected to a third power supply that supplies a lower voltage than the second power supply applied to the source of the n-channel MO3FET. It is.

[Effect]

In the semiconductor integrated circuit according to the present invention, the current driving capability of the output transistor can be increased by increasing the voltage between the gate and source of the open drain type output transistor formed of a high voltage p-channel MO8FET.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit configuration diagram of an output stage section showing a semiconductor integrated circuit according to an embodiment of the present invention. In the figure, 6 is an external output terminal, and T is this external output terminal 6 and external power supply terminal 8.
5 is a high breakdown voltage p as an open drain type output transistor whose drain is connected to the external output terminal 6, its gate is connected to the contact 4, and its source is connected to the first power supply 9. Channel MO8FET.

Further, 2 is a high voltage p-channel MO8FET whose drain is connected to contact 4, source is connected to first power supply 9, and gate is connected to contact 1, and 3 is this high voltage p-channel MO8F.
A resistor is connected between the ET2 and the external power supply terminal 8, and the external power supply terminal 8 is connected to the second power supply 11 (the fourth
(See figure) A negative potential (Vp) that is lower than the ground potential (Vss) applied to the source of the n-channel MO8
) to a third external power source (not shown). That is, the difference between the embodiment shown in FIG. 1 and the conventional example shown in FIG. 4 is that the high breakdown voltage p-channel MO8
The p-channel MO3FE has the same polarity as FE'r5, has a source connected to the first power supply 9, and a drain connected to the p-channel MO3FE through the contact 4.
High-voltage p-channel MO8FET2 as a driving transistor connected to the gate of T5, and this MO
A first resistor 3, one end of which is connected to the drain of the SFET 2, constitutes a logic gate in front of the output transistor.

Then, one end of the second resistor 7 is connected to the drain of the high voltage p-channel MO8FET 5, and the external output terminal 6 is connected to the drain, and the first and second resistors 3,
By connecting the other ends of 7 to an external power supply terminal 8, a voltage (Vp) lower than that of the second power supply 11 is applied to the power supply terminal 8 from the third external power supply, thereby forming an open drain. This is to drive a type of high breakdown voltage p-channel MO8FET5.

Note that the high-voltage p-channel MO8FET 2.5 has a breakdown voltage higher than that between the source and drain of the MOS FET that constitutes the complementary MO8 circuit or the integrated circuit in the 9CMO8 semiconductor chip. All circuit elements except the external output terminal 6 and the external power supply terminal 8 shown in FIG. 1 are integrated inside the semiconductor chip.

Next, the operation of the above embodiment circuit will be explained. Here, contact 1
Usually, the high level potential of the first power supply 9 (hereinafter referred to as H level) or the source potential of the n-channel MO8FET of the CMO8 logic circuit inside the semiconductor (hereinafter referred to as L level or ground potential) is applied. When contact 1 is at L level, high voltage p-channel MO8FET2 is not conductive, and contact 4 is at H level. At this time, the potential difference between the gate voltage and source voltage of the high voltage p-channel MO8FET5 (hereinafter referred to as VGS) is zero, and the high voltage p-channel MO8FE
T5 is in a non-conducting state, and the output terminal 6 is pulled down by the resistor 7 to the potential of the third power supply which is more negative than the ground potential applied to the external power supply terminal 8. In addition, when contact 1 is at H level, high voltage p-channel MO8FET2 is not in a non-conducting state, and contact 4 is at the third power supply potential V which is negative from the ground potential applied to external power supply terminal 8 by resistor 3.
It is pulled down to p. This allows υhigh voltage p-channel M
The O8FET 5 becomes conductive, and current flows out from the first power source 9 toward the output terminal 6. Current flowing at this time ID
S has a gate potential VIN and a potential VD of the first power supply 9.
D ground potential VssXp If the threshold voltage of channel MO8FET5 is vth and the output terminal voltage is vOUT, then
VDD-VOUT (When VDD-VIN-Vth-
7 (VDD-YouT)) 6...Fist* (21
It is expressed as However, W and L are each p-channel MO
In the channel width and channel length of 8FET 5, K is the conductance constant. Therefore, as is clear from the above equation (2), the larger IVDD-VINI, the more l I
Since DS l increases, VI
In the case where N=vp, the power is applied to the external power supply terminal 8. 1 Iosl increases by the potential difference between the ground potential and the third power supply which is more negative than the ground potential.

In the above embodiment, a resistor 3.7 was used as the load element, but p-channel MO8FETs 12 and 13.7 whose gates were connected to the external power supply terminal 8 as shown in FIG. Alternatively, as shown in Figure 3, connect the gates to each contact 4. Depletion type p-channel MO8FET connected to the drain side 14
According to the present invention, the voltage between the gate and source of the open drain type output transistor formed by the high voltage p-channel MO8FET is set to the third power source. Since the output transistor is configured to be increased by voltage, a large current can flow, and the area occupied by the output transistor can be reduced, resulting in excellent effects such as low cost.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to one embodiment of the invention, FIGS. 2 and 3 are circuit diagrams showing other embodiments of the invention, and FIG. 4 is an example of a conventional semiconductor integrated circuit. FIG. 2,5 II m 11 m high voltage p-channel MO8
FET. 3.7...Resistance, 6...Output terminal, 8...
External power supply terminal, 12.13...p channel MO8F
ET, 14.15-...Φ depression type p-channel MO8FET0

Claims (1)

[Claims] A first power source and an n-channel, which are equipped with an open-drain output transistor formed of a high-voltage p-channel field effect transistor and a previous-stage logic gate to which the output is connected to the gate thereof, and to which the source of the p-channel field-effect transistor is connected. In a complementary semiconductor integrated circuit having a second power supply connected to a source of a field effect transistor, the logic gate has the same polarity as the output transistor and has a high breakdown voltage, and the source has the same potential as the source of the output transistor. a driving transistor whose drain is connected to the gate of the output transistor, respectively;
A resistor having one end connected to the drain of the driving transistor or a first load element having an equivalent function, and a second load element having the same function as the first load element connected to the drain of the output transistor. one end of the load element is connected, an output terminal is connected to the drain of the output transistor, the other ends of each of the first and second load elements are commonly connected to an external power supply terminal, and the power supply terminal is connected to A semiconductor integrated circuit, characterized in that the semiconductor integrated circuit is connected to a third power source that supplies a voltage lower than the second power source applied to the source of the n-channel field effect transistor.