JPS6214582A - Vertical emphasis circuit - Google Patents

Vertical emphasis circuit

Info

Publication number
JPS6214582A
JPS6214582A JP15224785A JP15224785A JPS6214582A JP S6214582 A JPS6214582 A JP S6214582A JP 15224785 A JP15224785 A JP 15224785A JP 15224785 A JP15224785 A JP 15224785A JP S6214582 A JPS6214582 A JP S6214582A
Authority
JP
Japan
Prior art keywords
circuit
emphasis
luminance signal
signal
video signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15224785A
Other languages
Japanese (ja)
Inventor
Kazuyoshi Kotani
小谷 一孔
Kuniaki Miura
三浦 邦昭
Atsushi Yoshioka
厚 吉岡
Michio Masuda
増田 美智雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15224785A priority Critical patent/JPS6214582A/en
Publication of JPS6214582A publication Critical patent/JPS6214582A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the noise to prevent color fogging and blur by controlling the feedback quantity in accordance with the difference between the luminance signal of one horizontal period H before and the present luminance signal and correlations between signals of horizontal scanning periods adjacent to each other to perform preemphasis and deemphasis in the vertical direction. CONSTITUTION:If an input signal e1 is the luminance signal, the element of the constant of an attenuator in a fundamental circuit is included in a constant gamma of a level adjusting circuit 6, and an adder 7 is provided to perform operation, and a correlation detecting circuit consisting of a delay line 8, an attenuator 9, and a non-linear circuit 10 is formed, and the attenuation quantity of an attenuator 2 and the constant gammaof the circuit 6 are controlled by correlations obtained by said detecting circuit. The feedback quantity is controlled by the difference between the luminance signal of 1H before and the present luminance signal and correlations between signals of horizontal scanning periods adjacent to each other. Thus, the asymptotic characteristic of the outline part is converged more quickly to reduce the degradation of the response characteristic such as waveform dullness of rise and blur fall. The noise is reduced considerably by preemphasis and deemphasis effects in parts other than the outline part.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は磁気記録再生装置(例えばVTR等)における
映像信号の垂直方向のエンファシス回路に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a vertical emphasis circuit for a video signal in a magnetic recording/reproducing device (for example, a VTR, etc.).

〔発明の背景〕[Background of the invention]

VTRのS/N改善手段の一つとして画面の垂直方向の
プリエンファシス、ディエンファシスがある。これは、
例えば特公昭55−19551に記載されている1H遅
延線(jHは1水平期間、NTSCの場合63.5μB
)を用いたフィ    □−ドバック形の映像信号の垂
直方向の輪郭強調回路を発展させる事によって実現可能
である。
One of the means for improving the S/N of a VTR is pre-emphasis and de-emphasis in the vertical direction of the screen. this is,
For example, the 1H delay line (jH is 1 horizontal period, 63.5 μB in the case of NTSC) described in Japanese Patent Publication No. 55-19551.
) can be realized by developing a vertical contour enhancement circuit for a feedback type video signal.

しかし、回路の簡略化等の為に、プリエンファシスだけ
、あるいはディエンファシスだけを行なう場合、エンフ
ァシス量を大きくすると垂直方向の輪郭部分にほけを生
じる。特にカラー信号の場合、色にじみを生じ画質が劣
化する問題があった。
However, when performing only pre-emphasis or only de-emphasis to simplify the circuit, increasing the amount of emphasis causes blurring in the vertical contour. Particularly in the case of color signals, there is a problem in that color bleeding occurs and image quality deteriorates.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記した従来技術の欠点を補って、ノ
イズを大幅に抑圧し、併せて垂直方向のぼけあるいは色
にじみの発生を軽減した垂直方向エンファシス回路を提
供する事にある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a vertical emphasis circuit which can compensate for the above-mentioned drawbacks of the prior art, significantly suppress noise, and reduce the occurrence of vertical blur or color fringing.

〔発明の概要〕[Summary of the invention]

本発明は、垂直方向の輪郭強調回路を発展させ、垂直方
向のプリエンファシス、ディエンファシスを施すもので
ある。
The present invention develops a vertical contour enhancement circuit and performs vertical pre-emphasis and de-emphasis.

〔発明の実施例〕[Embodiments of the invention]

以下本発明をその実施例にもとすいて説明するが、本発
明の説明の前にフィードパ9り形の輪郭強調回路の原理
を説明する。
The present invention will be described below with reference to its embodiments, but before explaining the present invention, the principle of a feedper type contour emphasizing circuit will be explained.

第2図は、従来の1H遅延線を用いたフィードバック形
の映像信号の垂直方向の輪郭強調回路の一例である。こ
の回路の動作原理を説明すると、入力映像信号e1は1
H遅延線1、減衰率α倍(α〈1)の減衰器2、及び加
算器3で構成されるポジティブフィードバックルーズに
加えられる。この回路の出力映像信号りは1H遅延線1
の入力信号e2から、その出力信号e3を減衰率1倍(
βく1)の減衰器4を経た信号を減算器5により減算す
ることで得られる。各部の信号は1H遅延線1の遅延時
間をτとして、e 2 =、  a 、石ワて、1弓1
1Qx  ・・・曲間・ ■a3 = exp(−Sr
 ) ・e t      −=−■Sはラプラス変換
演算子 となり、回路総合の伝達関数G (S)は、で与えられ
る。ステップ人力e3に対する応答6t lは、第3図
に示すように時間τを経過する毎に瀘衰し、(1−β)
/(1−α)に漸近する。α〉βの場合、垂直方向の輪
郭強調回路となシ、α〈βの場合、その逆特性を有する
回路となる。
FIG. 2 is an example of a feedback type video signal vertical contour enhancement circuit using a conventional 1H delay line. To explain the operating principle of this circuit, the input video signal e1 is 1
The positive feedback loop is added to a positive feedback loop composed of an H delay line 1, an attenuator 2 with an attenuation factor α times (α<1), and an adder 3. The output video signal of this circuit is 1H delay line 1
From the input signal e2 of the output signal e3, the attenuation rate is 1 times (
It is obtained by subtracting the signal that has passed through the attenuator 4 of 1) using the subtracter 5. The signals of each part are as follows, where the delay time of 1H delay line 1 is τ, e 2 =, a , stone wire, 1 bow 1
1Qx...Between songs ■a3 = exp(-Sr
) ・e t −=−■S is a Laplace transform operator, and the transfer function G (S) of the overall circuit is given by. The response 6tl to the step human force e3 decays as time τ elapses, as shown in FIG. 3, and becomes (1-β)
/(1-α). When α>β, there is no vertical contour enhancement circuit, and when α<β, the circuit has the opposite characteristics.

本発明は上記のフィードバック形輪郭強調回路を基本に
等価変形し、更にフィードバック量を1H前の輝度信号
と現在の輝度信号の差分、即ち、となシ合う水平走査期
間の信号の相関性によって制御することにより、輪郭部
でのエンファシス特性を変化させ、垂直方向の輪郭のぼ
け、あるいは色にじみを軽減した垂直方向エンファシス
回路を実現することができる。
The present invention is based on an equivalent modification of the above-mentioned feedback type contour enhancement circuit, and further controls the amount of feedback based on the difference between the luminance signal 1H before and the current luminance signal, that is, the correlation between the signals in the horizontal scanning period that coincide with each other. By doing so, it is possible to realize a vertical emphasis circuit in which the emphasis characteristic at the contour portion is changed and blurring of the vertical contour or color blurring is reduced.

以下本発明の垂直エンファシス回路を実施例により説明
する。
The vertical emphasis circuit of the present invention will be explained below using examples.

第1図は、本発明の第1の実施例としての垂直方向エン
ファシス回路の基本構成を示したもので、入力信号e1
が輝度信号の場合である。第2図の基本形との相違点は
、減衰器4の定数βの要素をレベル調整回路6の定数γ
に含めたことと、加算器7を設けて演算を施したこと及
び遅延&18、減衰器9、非線形回路10から成る相関
検出回路を構成し、該相関検出回路より得られた相関量
に応じて減衰器2の減衰量とレベル調整回路6の定敬γ
を制御する構成にした事である。これによって後述のよ
うに、エンファシス定数が具体的に与え易くなシ、併せ
て輪郭部分でのディエンファシス量を小さくして輪郭に
生じるプリエンファシス時の過大ナオーハーシュートや
ディエンファシス時のほけを軽減出来る等の特長が生じ
る。
FIG. 1 shows the basic configuration of a vertical emphasis circuit as a first embodiment of the present invention.
is the case of the luminance signal. The difference from the basic form in FIG. 2 is that the constant β of the attenuator 4 is replaced by the constant γ of the level adjustment circuit 6.
In addition, an adder 7 is provided to perform calculations, and a correlation detection circuit consisting of a delay &18, an attenuator 9, and a nonlinear circuit 10 is configured, and according to the amount of correlation obtained from the correlation detection circuit. Attenuation amount of attenuator 2 and fixed value γ of level adjustment circuit 6
The structure was designed to control the This makes it easier to specify the emphasis constant as described later, and also reduces the amount of de-emphasis in the contour area to reduce excessive naoher shoot during pre-emphasis and blurring during de-emphasis that occur on the contour. Features such as being able to do so occur.

入力e1に対し、62+eBは前述した■、■式で与え
られ、その結果e4は となる。レベル調整回路6のゲインをrとすると伝達関
数G (S)は、 1−α と表わされる。0式においてr=1=7とすれば、■式
の示す特性と一致し、この回路が等価プリエンファシス
特性Gp(S)は となる。両特性間には Gp(S)・ Gd(’S) = 1・・・・・・・・
・・・・・・・・・・・・・・・・・・・・・・・・・
・・・■なる関係があるため、両回路の整合条件を完全
に満足させることができる。エンファシス係数に1.K
z及びエンファシス素Xは、上記整合条件関係式より独
立2変数で成立ち、両エンファシス係数、あるいはそれ
らの一方とエンファシス量を定めることにより、回路特
性を決定できる。
For the input e1, 62+eB is given by the above-mentioned equations (1) and (2), and as a result, e4 becomes. When the gain of the level adjustment circuit 6 is r, the transfer function G (S) is expressed as 1-α. If r=1=7 in equation 0, the characteristics match the characteristics shown by equation (2), and the equivalent pre-emphasis characteristic Gp(S) of this circuit is as follows. Between both characteristics, Gp(S)・Gd('S) = 1...
・・・・・・・・・・・・・・・・・・・・・・・・
Because of the relationship . . . , it is possible to completely satisfy the matching conditions for both circuits. 1 for emphasis coefficient. K
z and the emphasis element X are established as two independent variables according to the above matching condition relational expression, and the circuit characteristics can be determined by determining both the emphasis coefficients or one of them and the amount of emphasis.

ここで、 下限としてfH毎に最大となる特性を有する。here, It has a characteristic that the lower limit is maximum for each fH.

輝度信号の垂直周波数スペクトル成分は、水平スペクト
ルnfH(nは整数、fHは水平周波数)を中心として
存在し、第4図の特性からプリエンファシス1Gp(7
ω)1によりその垂直周波数スペクトル成分が強調され
、ディエンファシス1Gd(/ω)1により抑圧される
ことがわかる。第5図にブリエフファシス、第6図にデ
ィエンファシスのステップ応答を示す。輝度信号をプリ
エンファシスしてテープ 等に記録し、再生時にディエ
ンファシスすることにより、垂直周波数スペクトル成分
は原信号と一致し、再生系で混入したノイズはディエン
ファシスにより抑圧されるのでS/Nが改善される。改
善効果は低周波から高周波まで信号全帯域にわたる。
The vertical frequency spectrum component of the luminance signal exists centered on the horizontal spectrum nfH (n is an integer, fH is the horizontal frequency), and from the characteristics shown in Figure 4, the pre-emphasis is 1Gp (7
It can be seen that the vertical frequency spectrum component is emphasized by ω)1 and suppressed by de-emphasis 1Gd(/ω)1. FIG. 5 shows the step response of briefphasis, and FIG. 6 shows the step response of de-emphasis. By pre-emphasizing the luminance signal and recording it on tape, etc., and de-emphasizing it during playback, the vertical frequency spectral components match the original signal, and noise mixed in the playback system is suppressed by de-emphasis, resulting in a low S/N ratio. Improved. The improvement effect spans the entire signal band from low frequencies to high frequencies.

次に輪郭部における応答特性について述べる第5図、第
6図に示すようにステップ状の信号を入力すると、プリ
エンファシスでは信号の立ち上がりでオーバーシュート
を生じ徐々に信号レベルに漸近する特性になシ、デイエ
ンファシ    ]スでは立ち上が9がゆるやかで徐々
に信号レベルに漸近する特性になる。立ち下がシ部分で
は第7図、第8図の様に入力信号が0になってもエンフ
ァシス出力は、徐々に0に漸近する特性になる。本発明
では輪郭を遅延線8、減衰器9、非線形回路10からな
る相関検出回路により検出し減衰器2の減衰量とレベル
調整回路6を制御しに0あるいはに2およびXの値を小
さくする事によって輪郭部の漸近特性の収束速度を速め
、立ち上がりの波形なまりや立ち下がシのにじみ等の応
答特性の劣化を軽減する。これは輪郭部分のみ尾動作し
輪郭部以外は上記したエンファシス特性によるノイズ抑
圧効果が保たれる。また、減衰器2、レベル調整回路6
の一方のみを制御する構成も可能であシ、この場合上記
した応答特性改善効果は小さくなる。
Next, when we input a step-like signal as shown in Figures 5 and 6, which describe the response characteristics at the contour, the pre-emphasis creates an overshoot at the rise of the signal and gradually approaches the signal level. , de-emphasis] has a characteristic that the rise 9 is gradual and gradually approaches the signal level. In the falling portion, as shown in FIGS. 7 and 8, even if the input signal becomes 0, the emphasis output has a characteristic that gradually approaches 0. In the present invention, the contour is detected by a correlation detection circuit consisting of a delay line 8, an attenuator 9, and a nonlinear circuit 10, and the attenuation amount of the attenuator 2 and the level adjustment circuit 6 are controlled to reduce the values of 0 or 2 and X. This speeds up the convergence speed of the asymptotic characteristics of the contour and reduces deterioration in response characteristics such as waveform blunting at the rising edge and blurring at the falling edge. In this case, only the contour portion is affected, and the noise suppression effect due to the above-mentioned emphasis characteristic is maintained in areas other than the contour portion. Also, an attenuator 2, a level adjustment circuit 6
A configuration in which only one of the two is controlled is also possible, and in this case, the above-mentioned response characteristic improvement effect becomes small.

この垂直方向エンファシス回路を色度信号に適用する回
路につめて述べる。NTSC方式の場合、色度信号は輝
度信号に対し周波数227.5fル(fHは水平周波数
)の色副搬送波により、1/2fH周波数オフセットの
状態で多重されて、水平スベクトル(n+7 )fH(
nは整数)を中心として垂直周波数スペクトル成分が存
在する。従ってその垂直方向エン7アシスは第1図の構
成回路が(n+−)fHを中心とするスペクトル成分に
対し原理どおりの動作をするよう色副搬送波の位相を補
正してやる必要がある。すなわち、10.5 H遅延線1に227.5fHの遅延補正を付加するか1
H遅延線1の出力位相を反転させる。あるいは加算器3
を減算器に、減算器5を加算器に変えればよA0第9図
はNTSC方式の色度信号の垂直方向エンファシス回路
の例である。この例は加算器3を減算器に、減算器5を
加算器としたものである。これによるプリエンファシス
特性Gp (S )は、 ディエンファシス特性Gtics)h となシ、第10図にこれらの周波数特性1Gp(7ω)
 I 、 1Gd(7ω)l ヲ示ス。IGp(j”)
 l ハIo式中のQを上限としてfH毎に最大となる
特性を有し、1Gd(,2ω)Iは1/Qを下限として
fH毎に最小となる特性を有している。
This vertical emphasis circuit will be described in detail as a circuit that applies it to chromaticity signals. In the case of the NTSC system, the chromaticity signal is multiplexed with the luminance signal by a chrominance subcarrier with a frequency of 227.5 fH (fH is the horizontal frequency) with a 1/2 fH frequency offset, resulting in a horizontal vector (n+7) fH (
There are vertical frequency spectral components centered around the frequency (n is an integer). Therefore, in the vertical direction assist, it is necessary to correct the phase of the color subcarrier so that the component circuit shown in FIG. 1 operates according to the principle for the spectral component centered at (n+-)fH. In other words, whether 227.5fH delay correction is added to 10.5H delay line 1 or
The output phase of H delay line 1 is inverted. Or adder 3
9 is an example of a vertical emphasis circuit for NTSC chromaticity signals. In this example, adder 3 is used as a subtracter, and subtracter 5 is used as an adder. The pre-emphasis characteristic Gp (S) resulting from this is the de-emphasis characteristic Gtics)h, and these frequency characteristics 1Gp (7ω) are shown in Figure 10.
I, 1Gd(7ω)l is shown. IGp(j”)
1Gd(,2ω)I has the characteristic that it becomes the maximum for each fH with Q in the Io formula as the upper limit, and 1Gd(,2ω)I has the characteristic that it becomes the minimum for each fH with 1/Q as the lower limit.

色信号の垂直周波数スペクトル成分は(n←)fHを中
心に存在するため、前記輝度信号の場合と同様にS/N
改善効果が得られる。第9図の実施例では相関検出回路
の入力に輝度信号egを加え、輝度信号の輪郭を検出し
て減衰器2、レベル調整回路6を制御する。これは、色
副搬送波で変調された色度信号よりも輝度信号の輪郭を
検出する方が検出回路の調整が容易になるためである。
Since the vertical frequency spectral component of the color signal exists around (n←)fH, the S/N is the same as in the case of the luminance signal.
An improvement effect can be obtained. In the embodiment shown in FIG. 9, the luminance signal eg is added to the input of the correlation detection circuit, and the contour of the luminance signal is detected to control the attenuator 2 and the level adjustment circuit 6. This is because it is easier to adjust the detection circuit by detecting the contour of a luminance signal than by detecting a chromaticity signal modulated by a chrominance subcarrier.

esに色度信号を入力して輪郭を検出する場合は減衰器
9を加算器に変える。
When detecting a contour by inputting a chromaticity signal to es, the attenuator 9 is changed to an adder.

PAL方式の垂直方向エンファシスの場合、色度信号は
輝度信号に対し周波数28175fHの色副搬送波によ
F)1/4fH周波数オフセット状態で多重されB−Y
信号は水平スペクトル(n−7)fHを、R−Y信号は
同(n + a ) fHをそれぞれ中心として垂直周
波数スペクトル成分が存在する。
In the case of vertical emphasis in the PAL system, the chromaticity signal is multiplexed with the luminance signal by a color subcarrier with a frequency of 28175 fH at a frequency offset of F) 1/4 fH.
The signal has a horizontal spectrum (n-7)fH, and the RY signal has a vertical frequency spectrum component centered on (n+a)fH.

従って、その垂直方向エンファシスは第1図の構成回路
が(n±”)fHを中心とするよう補正してやる必要が
ある。すなわち、第1図におけ0.5 る1H遅延線を2H遅延線とし、283.75J’H−
の遅延補正を付加するか、その2H遅延線の出力位相を
反転させる。相関検出回路については輝度信号を入力す
る場合はNTSC方式と同様な構成で良い。色度信号を
入力する場合は1H遅0.5 延線を2H遅延線とし285.75fHの遅延補正を付
加するか、その2H遅延線の出力位相を反転させるか、
あるいは2H遅延線を用い減算器9を加算器に変えれば
よい。
Therefore, the vertical emphasis must be corrected so that the component circuit in Figure 1 is centered at (n±'')fH.In other words, the 1H delay line of 0.5 in Figure 1 is changed to a 2H delay line. , 283.75J'H-
Add delay correction or invert the output phase of that 2H delay line. The correlation detection circuit may have a configuration similar to that of the NTSC system when a luminance signal is input. When inputting a chromaticity signal, either use the 1H delay 0.5 extension line as a 2H delay line and add a delay correction of 285.75fH, or invert the output phase of the 2H delay line.
Alternatively, a 2H delay line may be used to replace the subtracter 9 with an adder.

〔発明の効果〕〔Effect of the invention〕

以上述べたように、本発明による垂直方向のエン7アシ
スをVTRなどに適用することにより、信号全帯域のS
/N改善効果が得られる。
As described above, by applying the vertical direction assist according to the present invention to a VTR, etc., it is possible to
/N improvement effect can be obtained.

特に他の手段でS/Nを改善しにくい200 KHz以
下の低周波領域においても効果があるので、画質向上に
大きく寄与する。
In particular, it is effective even in the low frequency region of 200 KHz or less, where it is difficult to improve the S/N by other means, so it greatly contributes to improving image quality.

更に本発明による垂直エンファシス回路は垂直方向の輪
郭部でそのエンファシス係数を変化させることにより、
プリエンファシスを行なわずディエンファシスを行なう
場合や、プリエン7アシスタケ行ないディエンファシス
を行なわない場合に生ずる再生出力信号の応答特性の劣
化や、過度なオーバーシュートを最小限にとどめる事が
可能である。
Further, the vertical emphasis circuit according to the present invention changes the emphasis coefficient at the vertical contour portion, so that
It is possible to minimize the deterioration of response characteristics of the reproduced output signal and excessive overshoot that occur when de-emphasis is performed without pre-emphasis or when de-emphasis is performed without pre-emphasis.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の垂直エンファシス回路の第1の実施例
を示すブロック図、第2図は従来の垂直方向の輪郭強調
回路のブロック図、第3図は第2図の入出力波形図、第
4図は第1図の回路のエンファシス特性図、第5図、第
6図、第7図、第8図は第1図の回路の入出力波形図、
第9図は本発明の第2の実施例を示すブロック図、第1
0図は第9図の回路のエンファシス特性図である。 1.8・・・1H遅延線、2・・・減衰器、6・・・レ
ベル調整回路、10・・・非線形回路。
FIG. 1 is a block diagram showing a first embodiment of the vertical emphasis circuit of the present invention, FIG. 2 is a block diagram of a conventional vertical edge enhancement circuit, and FIG. 3 is an input/output waveform diagram of FIG. 2. Figure 4 is an emphasis characteristic diagram of the circuit in Figure 1, Figures 5, 6, 7, and 8 are input/output waveform diagrams of the circuit in Figure 1,
FIG. 9 is a block diagram showing a second embodiment of the present invention;
FIG. 0 is an emphasis characteristic diagram of the circuit of FIG. 1.8... 1H delay line, 2... Attenuator, 6... Level adjustment circuit, 10... Nonlinear circuit.

Claims (1)

【特許請求の範囲】[Claims] 1、入力映像信号を遅延する第1の遅延回路と、第1の
遅延回路の出力映像信号を第1の遅延回路の入力側に正
帰還して入力映像信号と出力映像信号とを演算する第1
の演算回路1と、入力映像信号と出力映像信号の振幅差
信号を得る第2の演算回路と第2の演算回路の振幅差信
号の大きさを変化させる線形回路と、該線形回路の出力
と入力映像信号を演算する第3の演算回路と、入力映像
信号を遅延する第2の遅延回路と、第2の遅延回路の出
力映像信号と入力映像信号との振幅差信号を得る第4の
演算回路と、第4の演算回路の振幅差信号の一定振幅以
上を検出する非線形回路を有し、非線形回路出力により
上記正帰還量及び線形回路の減衰量を制御し、第3の演
算回路の出力を出力信号とすることを特徴とする垂直エ
ンファシス回路。
1. A first delay circuit that delays an input video signal, and a first delay circuit that positively feeds back the output video signal of the first delay circuit to the input side of the first delay circuit to calculate an input video signal and an output video signal. 1
an arithmetic circuit 1, a second arithmetic circuit that obtains an amplitude difference signal between an input video signal and an output video signal, a linear circuit that changes the magnitude of the amplitude difference signal of the second arithmetic circuit, and an output of the linear circuit. a third calculation circuit that calculates an input video signal; a second delay circuit that delays the input video signal; and a fourth calculation that obtains an amplitude difference signal between the output video signal of the second delay circuit and the input video signal. circuit, and a nonlinear circuit that detects a constant amplitude or more of the amplitude difference signal of the fourth arithmetic circuit, and controls the amount of positive feedback and the attenuation amount of the linear circuit by the output of the nonlinear circuit, and the output of the third arithmetic circuit. A vertical emphasis circuit characterized in that the output signal is
JP15224785A 1985-07-12 1985-07-12 Vertical emphasis circuit Pending JPS6214582A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15224785A JPS6214582A (en) 1985-07-12 1985-07-12 Vertical emphasis circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15224785A JPS6214582A (en) 1985-07-12 1985-07-12 Vertical emphasis circuit

Publications (1)

Publication Number Publication Date
JPS6214582A true JPS6214582A (en) 1987-01-23

Family

ID=15536312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15224785A Pending JPS6214582A (en) 1985-07-12 1985-07-12 Vertical emphasis circuit

Country Status (1)

Country Link
JP (1) JPS6214582A (en)

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