JPS62145338U - - Google Patents
Info
- Publication number
- JPS62145338U JPS62145338U JP3397786U JP3397786U JPS62145338U JP S62145338 U JPS62145338 U JP S62145338U JP 3397786 U JP3397786 U JP 3397786U JP 3397786 U JP3397786 U JP 3397786U JP S62145338 U JPS62145338 U JP S62145338U
- Authority
- JP
- Japan
- Prior art keywords
- resin
- wiring board
- integrated circuit
- coated
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims description 7
- 229920005989 resin Polymers 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図は本考案の一実施例を示す縦断面図、第
２図は内装樹脂にアルミナ等のフイラを混入した
混成集積回路基板の縦断面図、第３図ａ乃至ｃは
従来例を示す縦断面図である。
１１はチツプ部品、１２はサブストレート基板
、１３はモールド樹脂、１４は配線基板、１６は
バツフアコート樹脂である。
Fig. 1 is a longitudinal cross-sectional view showing an embodiment of the present invention, Fig. 2 is a longitudinal cross-sectional view of a hybrid integrated circuit board in which a filler such as alumina is mixed into the interior resin, and Fig. 3 a to c show a conventional example. FIG. 11 is a chip component, 12 is a substrate board, 13 is a mold resin, 14 is a wiring board, and 16 is a buffer coat resin.
Claims (1)
板において、上記配線基板を、該配線基板におけ
るサブストレート基板の膨張係数と略同一の膨張
係数を有するバツフアコート樹脂にて被覆し、こ
のバツフアコート樹脂をモールド樹脂にて被覆し
て成る混成集積回路基板。 In a hybrid integrated circuit board formed by coating a wiring board with a resin, the wiring board is coated with a buffer coat resin having an expansion coefficient substantially the same as that of a substrate substrate in the wiring board, and the buffer coat resin is molded. A hybrid integrated circuit board coated with resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3397786U JPS62145338U (en) | 1986-03-10 | 1986-03-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3397786U JPS62145338U (en) | 1986-03-10 | 1986-03-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62145338U true JPS62145338U (en) | 1987-09-12 |
Family
ID=30842088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3397786U Pending JPS62145338U (en) | 1986-03-10 | 1986-03-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62145338U (en) |
-
1986
- 1986-03-10 JP JP3397786U patent/JPS62145338U/ja active Pending
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