JPS62144257A - Cache memory - Google Patents

Abstract

PURPOSE:To given an access at a main memory at high speed by dividing a cache memory into plural blocks and allocating each of these blocks exclusively or in common to plural programs. CONSTITUTION:A cache memory 3A is divided into four blocks 0-3. While a program 7 includes four programs 0-3. Then the correspondence is secured between the program 7 and the block 6 of the memory 3A by the command of a CPU 1. In other words, a block 0 is allocated to a program 0 and can be used exclusively with no disturbance given from other programs. Then blocks 1 and 2 are allocated to a program 1 for the exclusive use of both blocks. A block 3 is allocated in common to both programs 2 and 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory for an electronic computer, and particularly to a cache memory that is divided into a plurality of blocks, each of which is used by a program.

[Conventional technology]

FIG. 83 is a block diagram of an electronic computer using a conventional cache memory.

In the figure, f/l is the CPU, (2) is the main memory, and (3
) is cache memory. Note that the cache memory (3) consists of a dynamic cache memory (gl) and a static cache memory (5).

A computer using conventional cache memory is configured as described above, and CPtH/l is the main memo January 2
1. When accessing something, first it is searched to see if the data to be accessed is in the cache memory (,?).

If the data to be accessed is in the cache memo (January 3), there is no need to access the main memory (January 2), and only the cache memory (3) is accessed. Conversely, if the data to be accessed is not in the cache memo January 3], the main memo January 2) is accessed. At this time, the same data is simultaneously copied to the dynamic cache memory (K+) in the cache memory (3) in preparation for the next access to the same data.

The static cache memo (January 5) is preliminarily cached by the CPU (
The data of a specific part of the main memo January =) has been copied by a command from /1, and the data is associated with a specific part of the main memo January 2] by the CPU (unless there is a command from /l). On the other hand, the dynamic cache memo January q) automatically maintains a copy of the data in the main memo January 2) that was most recently accessed without any command from the CP Uf/l. do.

By ensuring that the time required to access the cache memory (3) is much shorter than the time required to access the main memory (2), the CP
UI/) can access data in main memory (2) statistically in much less time than directly accessing main memory (2).

The correspondence between the static cache memo January j) and the main memory January =) will not change unless there is a command from CPtJM, so the part of the main memory (main memory) that is frequently accessed is stored in advance in the static cache memory. It will be effective if you respond accordingly. On the other hand, the dynamic cache memory (φ) automatically changes its association with the main memory (January 2), so the main memory (φ) changes automatically.
W4 of 21 is suitable when frequently accessed parts are not known in advance.

[Problem that the invention seeks to solve]

Conventional dynamic cache memory does not take into account multiprogramming, in which multiple programs are executed simultaneously on a computer; instead, it handles access to main memory by a specific specified program. There was a problem that it could not be done at high speed.

Furthermore, even if such programs access a portion of main memory that is associated with static cache memory, sufficient effects may not be obtained if the size of the portion of main memory that is accessed is larger than the static cache memory. There was also the problem that it was not possible.

This invention was made in order to solve the above-mentioned problems, and provides a cache that can perform high-speed access to main memory for one or several specified programs in a multiprogramming environment. The purpose is to obtain memory.

[Means for solving problems]

The cache memory according to the present invention includes '0. It is divided into several blocks, each of which has 1 block.
A block is allocated to one specified program, and is also allocated as a block shared by multiple programs.

[For production]

In this invention, a program can access the main memory at high speed without being interfered with by other programs.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a block diagram of a computer using an embodiment of the cache memory of the present invention, and FIG. 2 is a diagram showing an example of the correspondence between each block of the cache memory and a program. In the figure, (C is C
PU, (21 is the main memory, (3A) is the cache memory, (6) is a block obtained by dividing the cache memory IJ (,?A) into multiple pieces of the same size, and (wa) is the program. Fig. 2 is shown for the case where the number of blocks is ψ and the number of programs is large.

In Figure 2, the cache memory (3A) is block O
It is divided into nine blocks from block 3 to block 3. On the other hand, there is one program (wa) from program 0 to program 3''1.The correspondence between program (7) and block (6) of cache memory (3A) is C
This is done by a command from P U (/1. In FIG. 1, block 0 is assigned to program O,
For program 2ml, block 1 and blockco are respectively allocated exclusively, and block 3 is allocated as a block shared by the remaining programs, progelamco and program J.

By associating program (7) and block (6) in this way, program θ can use block 0 without being interfered with by other programs. Also, program / can use block / and blockco exclusively, and in this case, if the size of the part of main memory (2) that program l accesses is larger than the size of allocated block l and blockco, The cache memo IJ (JA) automatically changes its association with the main memory IJ (,21) within the range of the allocated block thickness.Block 3 is exclusively allocated to seven programs. It is shared by all remaining programs instead of using traditional cache memory (3
) plays the role of dynamic cache memo January.

As described above, the correspondence between programs and blocks is not fixed, but can be changed by instructions from the CPU, making it possible to perform the most efficient correspondence.

In addition, in the above embodiment, the number of blocks was q, but
It may be any number greater than or equal to two. Furthermore, although the blocks are assumed to have the same size, some blocks may have different sizes.

〔Effect of the invention〕

As explained above, the cache memory of the present invention is divided into a plurality of blocks, and by determining the correspondence between each block and a program according to a command from the CPU, each block can be dedicated to one or more programs. Because it is configured so that it can be used separately or in common, access to the main memory performed by some specific programs can be made faster without being interfered with by other programs.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an electronic computer using an embodiment of the present invention, FIG. 2 is a diagram showing an example of the correspondence between cache memory blocks of the present invention and programs, and FIG. 3 is a diagram showing a conventional cache memory. It is a block diagram of the electronic computer used. In the figure, (/l # @ CPU, L21 e
0 main memory, (31 and (3A)・φ cache memory,
(ql/φ dynamic cache memory, (S)/φ static cache memory, (mi)/φ cache memory block, (7)... program. In the figure, the same reference numerals are the same or equivalent. Show parts.

Claims (3)

[Claims] (1) It is divided into a plurality of blocks, each block is used exclusively or shared by one or more programs, and the correspondence between the blocks and the programs is determined by instructions from the CPU. A cache memory characterized by being controlled. (2) The cache memory according to claim 1, wherein each block has the same size. (3) The cache memory according to claim 1, in which each block has a different size.