JPS62144256A - 2-address port memory system - Google Patents

Abstract

PURPOSE:To reduce the deterioration of the processing speed when a cache mistake occurs by deciding the cache hit and miss of two logic addresses at a time and at the same time giving accesses individually to plural memory banks. CONSTITUTION:When the data matching processing is carried out by a processor 400, the two logic addresses sent to address registers 210 and 220 of a cache memory 100 from data access units 410 and 420 undergo the decision for the cache hit and miss through an address arrays 230. When both logic addresses have a hit, the hit data is delivered to the processor 400 from a data array 250. When one of both addresses has the hit and the other has the miss, the hit data is delivered to the processor 400 from the array 250 and at the same time a data block including the miss data is sent to the processor 400 from a main memory 300 via the array 250.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a memory system for an information processing device, and in particular, to speed up the process of accessing two pieces of data simultaneously, such as in data matching. The present invention relates to a two-address port memory system with two address input ports.

[Conventional technology]

In symbolic processing using a high-level programming language such as Prolog, the data matching function is a basic function that greatly affects the processing speed of symbolic processing.

Data matching involves accessing two pieces of data to be matched, checking the data types, and comparing data values or assigning them to variables. However, even the seemingly simple matching of data is complicated by the existence of data types consisting of multiple elements, such as strings and lists, and the existence of pointer chains caused by binding, which connects two variables using pointers, which occur when matching variables. increases the number of data accesses and data type checks.

For this reason, the processing time required for data matching occupies a large proportion of the total processing time for symbol processing. Furthermore, an increase in the number of data accesses required to match data leads to an increase in the number of access requests to the memory system. This means that there is a limit to improving the overall processing speed by simply increasing the speed of the processor, since the processing speed of the memory system becomes a bottleneck. As a means to eliminate this bottleneck in the memory system, a cache memory, which is a high-speed buffer memory, is used on the processor side.

[Problem that the invention seeks to solve]

The conventional method of adding a cache memory to the processor side allows the processor to perform high-speed processing as long as the data necessary for processing exists in the cache memory.

However, if the data required for processing does not exist in the cache memory, the access speed of the memory system is slow, so the processing speed decreases. Therefore, the probability that the required data exists in the cache memory has a large effect on the processing speed. The data you need is cached.
In order to increase the probability that data exists in memory, it is desirable that data required within a short period of time be locally consolidated in the memory area. Programming languages such as FORTRAN and C0BOL that have been used for a long time have data locality in which dynamically accessed data is locally fixed in a memory area.

In the high-level programming language Prolog, since Bontachains are frequently generated by matching variables, there is a stronger tendency for data required for processing to be scattered over a wide range of memory areas than in conventional high-level languages. Therefore, since the locality of data is less, the frequency of cache misses in which the required data does not exist in the cache memory increases. On a cache miss,
Since a swap-in process is required to transfer the required data from the main memory to the cache memory, the processor stops and waits until the required data becomes accessible. This processor stop time has a problem in that as the frequency of cache misses increases, the effect it has on the overall processing time also increases.

The purpose of the invention is to develop a high-level programming language pro
To speed up data matching in log,
Equipped with two address input ports, it is possible to receive access requests from the processor for two pieces of data to be matched at the same time, and if both pieces of data requested to be accessed are matched, the data is cached on the conventional processor side. - Outputs hit data at the same processing speed as a device equipped with memory, and if one of the requested data is a hit and the other is a miss, the hit data and miss data are output. Two addresses that can execute processing in parallel and, if both requested data misses, overlap the processing of the two missed data to minimize the processing speed drop in the event of a cache miss. The purpose is to provide a port memory system.

[Means to solve the problem]

The present invention provides a two-address port memory system consisting of a cache memory and a main memory, wherein the cache memory has a first address input port and a main memory.
simultaneous processing of cache hit/miss determination for two logical addresses held by an address register, a second address register having an address input port, the first address register and the second address register; an address array and the first cache based on the cache hit/miss determination made by the address array;
an address selection unit that determines two types of logical addresses for hit processing and miss processing from the two logical addresses held by the address register and the second address register; and a replacement unit when the cache memory misses. and a cache control unit that controls processing, and the main memory is configured to transfer a data block, which is a data management unit including the missed data, from the main memory to the cache memory when the cache memory misses. A main memory control unit that controls transfer, and a plurality of memory banks that can receive a plurality of main memory access requests from the cache control unit, and
The array simultaneously performs cache hit/miss determination for two logical addresses held by the first address register and the second address register, and when one hits and the other misses, the address array and the second address register The address selection unit simultaneously starts accessing the cache memory and the main memory, and when both miss, simultaneously processing accesses to the plurality of memory banks forming the main memory. It is said that

[Effect]

Data matching in proIQg always consists of 2
access data. These two data accesses can be processed in parallel, and even if one data access is temporarily interrupted due to a cache miss, continuing the other data access is effective in speeding up processing. be.

Therefore, the main memory consists of an address array that can accept two data access requests at the same time and can determine cache hit/miss for two data accesses, and multiple memory banks that can be accessed simultaneously.
By providing a memory, when two data access requests are both hit, the hit data is output to the processor in the order set in advance by the hardware, and one of the two data access requests is If a hit causes a miss in the other one, the output of the hit data to the processor and the swap-in processing of the data block containing the miss data are processed in parallel, reducing the processor stoppage time due to a catch miss. If two data access requests both result in cache misses and the two miss data exist in the same memory bank, swap the data blocks containing the miss data in the order set in advance by hardware.・Execute in processing, and if two data access requests result in cache misses and the two miss data exist in different memory banks, swap the data block containing the two miss data. - By overlapping in-processing, it is possible to reduce processor stoppage time due to cache misses.

〔Example〕

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a two-address port memory system of the present invention. In the figure, 100 is a cache memory,
300 is a main memory, and an example is shown in which the main memory is composed of four memory banks. In the main memory 100, 210 and 220 are address registers A and 220 that store two logical addresses for data access by an external processing unit that requires two data accesses at the same time, such as data matching. These are registers B, each having an input port.

230 is an address register that simultaneously processes cache hit/miss determination for two logical addresses held by address register A 210 and address register B 220.
It is an array. 240 determines the address based on the cache hit/miss determination made by the address array 230.
This is an address selection unit that determines two types of logical addresses, one for hit processing and one for miss processing, from two logical addresses held by register A 210 and address register B 220. 250 is a data array that holds data. 260 is a replacement control unit that provides replacement information to the address array. 2
Reference numeral 70 denotes an address translation information buffer that stores pairs of logical addresses and physical addresses in order to speed up address translation processing when a mistake occurs. 280 is cache memo 1
This is a cache control unit that controls replacement processing when a cache miss occurs, such as registering transfer data from the main memory 300 when the OO misses.

In the main memory 300, a data block 310, which is a unit of data management including the missed data when the cache memory 100 misses, is stored in the main memory 3.
This is a main memory control unit that controls the transfer from 00 to cache memory 100. 320.33
0.340.350 is an access in which cache memo January 00 is forced to wait after the cache control unit 280 requests access to main memo January 00 until the first data of the data block is received. To save time, the main
A memory bank that allows multiple memory access requests to be accepted. In the figure, IO and 20 are address buses, 30 are control buses, and 40 are f-ta.
50 is the memory address bus, 60 is the memory address bus,
Control bus 70 is a memory data bus.

FIG. 2 shows an example of the configuration of an information processing device using the two-address port memory system shown in FIG.

400 is a processor unit that processes data matching at high speed, and this processor unit 400 is composed of a matching unit 430 that processes data matching, and data access units 410 and 420 that access data to be matched. There is.

Next, the operation of this embodiment will be explained by explaining the operation of the information processing apparatus shown in FIG. When performing data matching processing on the processor section 400, the data access units 410 and 420 use the address buses 10 and 20 to access the data to be matched.
The logical address of the data storage destination is cached via
Address register A210 of memory 100 822
Send to 0. The logical addresses written in address registers A 210 and B 220 are sent to address array 230, and cache hit/miss determination is performed by address array 230.

Each case will be explained separately below.

If two logical addresses both hit If the logical addresses held by address registers A 210 and 8220 both hit, address array 230 first uses address selection unit 240 to select the address held by address register Δ 210. Send the logical address to data array 250. As a result, address register A210
The data specified by
It is output to the processor section 400 via the lotus 40. Address array 230 then addresses address selection unit 2
40 to select the logical address held by address register B 220 and send it to data array 250. As a result, data array 250 outputs the data specified by address register B 220 to processor section 400 via data bus 40.

FIG. 3 is a timing chart showing the above situation.

In the figure, 600 indicates the processing on the address register A 210 side, and 700 indicates the flow of processing on the address register B 220 side. Steps 610 and 710 are steps in which the processor section 400 sets logical addresses in the address registers A210 and 8220. 620 and 720 are steps in which the address array 230 performs cache hit/miss determination. 630 is address register A21
0 is a step in which the data array 250 outputs the specified data. 730 indicates a standby state step in which the data array 250 is outputting the data specified by the address register A 210, so outputting the data specified by the address register B 220 is stopped. 740 is a step in which the data array 250 outputs the data specified by the address register B220.

In addition, in FIG. 3, L is the address register Δ210
Alternatively, address register B 220 indicates a step in which a logical address is set, D indicates a step in which address array 230 performs cache hit/miss determination, and A indicates a step in which data array 250 outputs designated data. , and W indicates a step in a standby state.

When one of the two logical addresses is a hit and the other is a miss If one of the two logical addresses held by address registers A 210 and 8220 is a hit and the other one is a miss, the address array 230 Human data and mistakes
Start processing data at the same time.

Address array 230 processes human data.
instructs address selection unit 240 to select the logical address of the hit data and send it to data array 250. As a result, data array 250
Output data. At this time, address array 230
outputs the identification number of the address register specifying the hit data to the control bus 30, and instructs the processor section 400 to correctly receive the hit data.

To process the missed data, the address array 230 instructs the address selection unit 240 to select the logical address of the missed data and send it to the address translation information buffer 270. Further, address array 230 simultaneously instructs address selection unit 240 to send data, including miss data, to cache control unit 280.
Requests block swap-in processing. As a result,
Address translation information buffer 270 performs the translation of the miss data from a logical address to a physical address and sends the physical address via memory address bus 50 to main memory control unit 310 of main memory 300 . Further, at the same time as sending the physical address, the cache control unit 280 requests access to the main memory of the memory report IIf wholesale unit 310 via the memory control bus 60. After receiving the physical address and the main memory access request, the main memory control unit 310 sends the physical address to the memory bank corresponding to the physical address and starts accessing the data block containing the missed data. Access to the memory bank is controlled by the main memory control unit 310, and when the memory bank is ready to output data, the main memory control unit 310 transfers data including miss data to the address array 230 via the cache control unit 280. - Notify that the block can be accessed. As a result, address array 230 assigns the logical address of the missed data to address selection unit 240.
Instruct to send to array 250. Thereafter, block transfer of data from the memory bank to data array 250 via memory data bus 70 begins. When the last data is written to data array 250, address array 230 is written to replacement controller 260.
In accordance with the replacement information, processing such as holding the address corresponding to the block newly stored in the cache memory 100 is performed. When the first data is transferred from the memory bank to the data array 250, data waiting time of the processor section 400 is reduced by simultaneously sending the data to the processor section 400 that requested the data.

In Figure 4, the address register A210 side is cached.
This is a timing chart showing the flow of processing when a mistake is made. 610 and 710 (This is a step in which the processor section 400 sets logical addresses in address registers A210 and 8220. 620 and 720 are steps in which the processor unit 400 sets logical addresses in address registers A210 and 8220.
This is a step in which the array 230 performs cache hit/miss determination. 640 is address translation information buffer 2
70 is a step of converting the logical address on the address register 3220 side into a physical address. 740 is a step in which the data array 250 outputs the data specified by the address register B220. 650 is a step in which the cache control unit 280 issues an access request to the main memory control unit 310. 650
At the same step, the address register 3220 side starts listening for access to the next data. 660 is a wait step that occurs with memory bank access. 630, the miss data is sent to the data array 250 and the processor section 400.
This is the step to be transferred to. 670 is a step of writing the remaining data of the data block containing the miss data to the data array 250. On the other hand, 730 writes the data sent from the memory bank to data array 250 to write address register B2.
This is a standby step that occurs because the data array 250 cannot be used on the 20 side. It is a coincidence that 670 and 730 overlap.

In FIG. 4, T is a step for converting a logical address into a physical address, R is a step for requesting access to the main memory, and S is a step for data including miss data.
This is the step of writing the remaining data of the block to data array 250.

L, D, W, and A are the same steps as in FIG.

When two logical addresses both miss If two logical addresses held by address registers A210 and 8220 both miss, processing of the missed data is started from the address register A210 side. The processing of miss data is the same as the processing of miss data performed when one hit and the other miss, as described above. The processing flow at this time is that two pieces of miss data are stored in the same memory.
It differs depending on whether it exists on a bank or a different memory bank.

FIG. 5 is a timing chart showing the flow of processing when two pieces of miss data exist on the same memory bank. At step 640, the logical address on address register A 210 is translated to a physical address. At this time, the address register B 220 side enters a standby step 730 because the address translation information buffer 270 is in use. In step 650, the address register A 210 side requests access to the main memory. At this time, the address register B 220 side performs translation from a logical address to a physical address in step 750 since the address translation information buffer 270 has become available. 760 is address register B that occurred because address register A210 accessed the main memory.
This is a standby step on the 220 side. 770 indicates that the address register A 210 side writes the last data from the memory bank to the data array, and at the same time the address register B 220 side accesses the main memory.

This is the step of making a request.

FIG. 6 is a timing chart showing the flow of processing when two pieces of miss data exist on different memory banks. Each memory bank can accept one access request, and a memory bank cannot accept an access request to that memory bank if it is not currently processing the access request while another memory bank is processing the access request. Can be attached. The difference from when two pieces of miss data exist on the same memory bank is that the memory hang is different, so the main memory on the address register B220 side
The access request can be executed in step 770 following step 650 in which the main memory access request on the address register A 210 side is made. As a result,
Waiting steps 660 and 790 due to memory bank access can be overlapped, reducing the reduction in processing speed when a cache miss occurs.

In addition, in FIGS. 5 and 6, L, , D, and W.

A, T, R, and S are the same steps as in FIGS. 3 and 4.

[Effects of the Invention] □ According to the 2-address port memory system of the present invention,
In symbolic processing that makes extensive use of data matching and pointer chains, two data matching methods are used to address the problem of a decline in the cache memory hit rate due to the widening of the memory area, which causes a slowdown in the processing speed of information processing equipment. Focusing on the fact that data is processed between data, we developed an address array that has two address input ports, simultaneously performs cache hit/miss determination for two logical addresses, and multiple memory banks that can be accessed individually. By using a main memory configured with 2 pieces of data, it is possible to improve the data transfer speed drop in the event of a cache miss and speed up processing that processes two pieces of data at the same time, such as data matching. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of a two-address port memory system of the present invention, FIG. 2 is a block diagram of an information processing device using the two-address port memory system of the present invention, and FIG. 3 is a block diagram of two systems of access requests. Fig. 4 is a timing chart showing the flow of processing when system A misses and system B hits.
Figure 5 is a timing chart showing the processing flow when both A and B systems miss and two pieces of miss data exist in the same memory bank. Figure 6 is a timing chart when both A and B systems miss. 12 is a timing chart showing the flow of processing when two pieces of miss data exist in different memory banks. 10.20 Address bus 30
・・・・・・・・・・・・ Control bus 40
・・・・・・・・・・・・ Data bus 50 ・
・・・・・・・・・・・・ Memory address bus 60
・・・・・・・・・・・・ Memory control bus 70 ・・・・・・・・・・・・ Memory data bus 100 ・・・・・・・・・・・・ Cache Memories 210, 220... Address register 230... Address array 240... Address selection unit 250... ... Data array 2
60...... Replacement control unit 270... Address translation information buffer 280... Cache control unit 310・・・・・・・・・・・・ Main memory control unit 320 to 350... Memory・
Bank 400... Processor section 410, 420... Data access unit 430... Matching unit agent Patent attorney Yoshi Iwasa Figure 1 Figure 2

Claims (1)

[Claims] (1) Consisting of cache memory and main memory2
In the address port memory system, the cache memory includes a first address register with an address input port, a second address register with an address input port, and a first address register and the second address register. - an address array that simultaneously processes cache hit/miss determination for two logical addresses held by the register; and an address array that simultaneously processes cache hit/miss determination for two logical addresses held by the register; an address selection unit that determines two types of logical addresses for hit processing and miss processing from two logical addresses held by two address registers; and a cache control that controls replacement processing when the cache memory misses. The main memory includes a main memory unit that controls the transfer of a data block, which is a data management unit including missed data when the cache memory misses, from the main memory to the cache memory. - a memory control unit and a plurality of memory banks capable of accepting a plurality of main memory access requests from the cache control unit, the address array including the first address register and the second address;・
Cache hit/miss determination is performed simultaneously for two logical addresses held by registers, and when one hits and the other misses, the address array and the address selection unit select the cache memory and the main memory. A two-address port memory system characterized in that accesses are started at the same time, and when both fail, accesses to the plurality of memory banks constituting the main memory are processed simultaneously.