JPS62143582A - Digital data signal overlapping circuit - Google Patents

Abstract

PURPOSE:To easily input a data to a sending buffer memory circuit when a part where a data signal is overlapped is expanded over all of horizontal scanning periods by counting the synchronizing signal of an input signal, and outputting a control pulse signal at every arrival of a count value at a setting value. CONSTITUTION:The output signal of a synchronizing separator circuit 2 which samples a vertical and a horizontal synchronizing signals from a television video signal from an input terminal 1 is inputted to an overlap timing pulse generation circuit 3, and at every arrival of horizontal scanning period when a data is overlapped, the pulse signal is outputted, and the data stored at a sending buffer memory circuit 7 is outputted. The data is overlapped on a signal from the terminal 1 with a data overlapping apparatus 9 through a sending signal processor 8, and is outputted as a data signal overlapped television video signal. The synchronizing signal from the circuit 2 is counted with a counter 4, and a count pulse signal is outputted, and a control pulse generation circuit 5 outputs the control pulse signal to a data input circuit 6 at a data signal overlapping time.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a circuit for superimposing a digital data signal onto an input signal in the form of a television video signal.

Teletext broadcasting, which is an example of conventional technology in which data signals are superimposed, is a broadcasting system that transmits image information consisting of characters and graphics such as weather forecasts, news, stock information, etc., and audio information using digital data signals. .

This teletext consists of the vertical blanking period 2' of the television signal.
... Data signals are superimposed from 1oH to 21H in the horizontal scanning period and from 273H to 284H in the next field. FIG. 6 shows an example of a conventional data signal superimposition circuit, in which 17 is a terminal to which a television video signal is input;
18 is a synchronization separation circuit that extracts synchronization signals (vertical synchronization signal and horizontal synchronization signal) from the television video signal. The next counter 19 is reset by the vertical synchronizing signal of the synchronizing signal, generates a count pulse signal by counting the horizontal synchronizing signal, and generates a gate pulse from the generating circuit 2o by the counter pulse signal.

FIG. 6 shows a timing chart of the signal A of the synchronization part of the television video signal and the gate pulse signal port. A gate pulse signal is output during the periods from 10H to 21H and from 273H to 284H, when the teletext can be superimposed.

In FIG. 5, during the period in which the gate pulse signal is being output from the gate pulse generation circuit 20, the data that has already been input from the data input circuit 21 to the output buffer 7 memory circuit 22 is sent to the output buffer 7 memory circuit 3'. - Send buffer memory circuit 2 as data of memory circuit 22
2, is converted into a packet format data signal by a transmission signal processing device 23, is superimposed on a television video signal by a data signal superimposition device 24, and is output from the data signal superimposition device 24 as a television signal with the data signal superimposed thereon.

Furthermore, during the period in which the gate pulse signal of the gate pulse generation circuit 20 is not output, data from the data input circuit 21 to be superimposed and transmitted next is inputted to the transmission buffer memory circuit 22, and is transmitted to the television signal from the input terminal 17. The packet format data signal from the signal processing device 23 is not superimposed, and the same signal as input from the input terminal 17 is outputted from the output terminal 24 .

Problems to be Solved by the Invention By the way, it is possible to input the data signal not only during the horizontal scanning period of the vertical blanking period of the television video signal, but also during all the horizontal scanning periods including the portion where the normal video signal is present. There is so-called full field teletext, which is transmitted in a superimposed manner. This full-field teletext is a teletext system that transmits and services a large amount of text, graphics, and audio information, and is used in CATV networks and the like.

However, as in the case of full-field teletext broadcasting, when the part where the data signal is superimposed is expanded to include not only the horizontal scanning period of the vertical blanking period of the television video signal but also the entire horizontal scanning period, the conventional superimposing circuit 5, the period during which the gate pulse signal is output from the gate pulse generation circuit 20 in FIG. 5 becomes longer, and the data input circuit 2
Since the period for inputting data from data input circuit 1 to output buffer memory circuit 22 becomes extremely short, it becomes impossible to input sufficient data from data input circuit 21.

The present invention can be applied in a case where the portion on which a data signal is superimposed is extended not only to the horizontal scanning period of the vertical blanking period of a signal in the television video signal format, but also to other horizontal scanning periods.
This is to provide a period during which the data can be input to the sending buffer 7 memory circuit 22.

5Ba/Means for Solving the Problems The present invention superimposes a data signal on an input signal in the form of a television video signal, and at the same time superimposes a horizontal synchronization signal, a vertical synchronization signal, or both of the synchronization signal of the input signal. Each time a predetermined number is reached, a control pulse signal is output so that the timing of superimposition transmission at that point in time can be known.

Effect of the Invention The present invention, with the above-described configuration, makes it possible to know how much data has been superimposed and sent out at the time of outputting the control pulse signal, and to input the data that has been sent out again into new data. This allows you to have more time to input data, making it easier to input data.

Embodiment FIG. 1 is a block diagram showing a data signal superimposition circuit for the entire horizontal scanning period according to an embodiment of the present invention. In the figure, 1 is a television video signal input terminal 6, and 2 is a synchronization separation circuit that extracts a vertical synchronization signal and a horizontal synchronization signal from the signal from the input terminal 1. By inputting the output signal from the synchronization separation circuit 2 to the superimposition timing pulse generation circuit 3, a superimposition timing pulse signal for measuring the timing of superimposition is output every time a horizontal scanning period for superimposing data comes, and the output buffer memory The data stored in the circuit 7 is output every time 3 is output.

Furthermore, the data in the output buffer memory circuit 7 is converted into a packet-type data signal by the output signal processing device 8, and is superimposed on the signal from the input terminal by the data superimposer 9.
It is output from the output terminal 10 as a data signal superimposed television video signal.

On the other hand, in the figure, a counter 4 counts the synchronization signals from 2 and outputs a count pulse signal, and a control pulse generation circuit 5 outputs a control pulse signal to a data input circuit 6.

FIG. 2 shows an example of a timing chart of the input signal at terminal 1 in FIG. 4 is reset with the vertical synchronization signal from the synchronization separation circuit 2, the horizontal synchronization signal lf is applied, and the control pulse signal from the control pulse generation circuit 5 is transferred to 10H from the input terminal 1 in Figure 2. It is set to be output when the signal is superimposed and when the data signal is superimposed every 10H to 50H.

FIG. 3 shows an example of how to allocate a memory area for data to be sent in a superimposed manner from the sending buffer memory circuit 7 in the settings shown in FIG. Divided into two second buffer memory areas, each buffer 7 memory area has a superimposed sending data area for 50H, and superimposed timing pulses from the data signal superimposer 9 are input to the input terminal 11 according to the superimposed sending order number A. Every time a signal is input, the data portion superimposed on 1H of the first buffer memory area is outputted to the output data of the output terminal 12. data 10
After outputting 0, data 1 is output again. Note that data is input from 13 onwards.

FIG. 4 shows the temporal transition of the data input/output area in the send-out buffer 7 memory circuit in response to the control pulse signal when the buffer memory area has the shape shown in FIG. 3 with the settings shown in FIG. It is something. In FIG. 4, as the superimposed horizontal scanning period number a changes, the control pulse signal S is output, and the output area of the data C to be superimposed and sent out in the sending buffer memory circuit changes as shown in the figure.

This is the area where data is input from the data input circuit in the output buffer memory circuit of f.

The data can be changed as shown in FIG. 4, and data that has already been superimposed can be re-inputted as new data from the data input circuit.

Effects of the Invention As described above, the present invention has a simple circuit configuration when the portion on which the data signal is superimposed is extended not only to the horizontal scanning period of the vertical blanking period of the television video signal but also to the entire horizontal scanning period. The output buffer memory [
This makes it possible to input all data to four channels (9"-), and the capacity of the output buffer memory is also small, which is a significant effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a period data signal superimposition circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of a timing chart of a control pulse signal, and FIG. 3 is a diagram showing a memory area for data to be sent in a superimposed manner. FIG. 4 is a diagram showing a temporal transition of the data input/output area in the sending buffer memory circuit, FIG. 5 is a block diagram of a conventional teletext signal superimposition circuit, and FIG. This figure is a timing chart for explaining the operation of the circuit shown in FIG. 1...TV video signal, 3...Superimposed timing pulse M number, 5...Control Hals signal, 9...
...Data signal superimposed TV video signal.

Claims (1)

[Claims] Counting the horizontal synchronization signal or vertical synchronization signal of the television video signal type signal, obtaining a control pulse signal for each predetermined count value, and superimposing a digital data signal on the television video signal type signal using the control pulse signal. A digital data signal superimposition circuit characterized by: