JPS62142446A - Voice packet communication system - Google Patents

Abstract

PURPOSE:To improve the quality of a reproduced voice signal and to prevent overflow and underflow of a buffer memory by synchronizing the transmission side and the reception side while taking it as a chance when the coversation is restarted after a prescribed length of silence period regarded as intermission of the conversation. CONSTITUTION:A packet is received by a packet reception circuit 22 and its inverted state is detected, then a read counter in a read control circuit 27 is set to a head of a storage area just before the storage area in which its reception packet is written. While a read control circuit 27 advances a read address synchronously with the clock signal from a clock generating circuit 28, the circuit 27 reads sequentially the content of each storage area of the packet buffer memory 26, the result is sent to a D/A converter 29 and when a resetting command of a count is received from a start bit read circuit 23, the content of the write address counter in the write control circuit 25 is read and the read address is reset to the head value of the storage area just before.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention Industrial Application Field The present invention relates to a voice packet communication system used in a packet communication system in which a plurality of terminal devices are connected via a common packet transmission path. In particular, the present invention relates to a packet communication system in which a receiving section is equipped with a buffer memory for absorbing delay time jitter that occurs when transmitting audio packets.

2. Description of the Related Art In a packet communication system in which a plurality of terminal devices are connected via a common packet transmission path, voice packets that require immediate processing may be sent and received mixed with other data packets.

Conventionally, in the communication of such audio packets, the transmitting side bundles digital audio signals by a predetermined number of samples, and
Packets are created by assigning serial numbers to this bundle in the order of creation. In the audio signal, not only sound data during a call, but also silent data due to interruptions in conversation, etc. appear with considerable frequency. Sending such packets containing only silent data (hereinafter referred to as "silent packets") is wasteful in terms of transmission efficiency. Therefore, the transmitting side determines whether or not a part of the created packet contains sound data, and the packet containing sound data at least in part (hereinafter referred to as
``Speech packets'') are selectively sent.

On the other hand, on the receiving side, the digital audio signal in the received voice packet is written to a write address in a buffer memory that is cyclically updated in accordance with the serial number of this audio packet. In parallel with this writing of received data, the digital audio signal in the buffer memory is read out. The distance between the read address and the write address is initially set when the first sound packet is received, and thereafter, the read address is cyclically incremented at the sampling period. This read-out portion is immediately rewritten with silent data. Therefore,
During a period in which no sound packets are sent, silent data is inserted into the reproduced signal by repeating writing and reading of silent data on the receiving side.

The sending of the above-mentioned sound packets on the sending side is performed in the gaps between packet sending by other terminal devices, so the waiting time from the completion of packet creation to sending out varies from packet to packet. A phenomenon occurs in which the time interval from the end of packet creation to the end of reception on the receiving side fluctuates (hereinafter referred to as "jitter"). Such jitter is also caused by variations in propagation delay time in certain transmission systems. The buffer memory on the receiving side also has the function of absorbing such jitter.

Problems to be Solved by the Invention The conventional voice packet communication system described above has the following problems.

The analog audio signal is normally sampled at a sampling period of 125 μs (sampling frequency of 8 KHz) and converted into a digital audio signal, and on the receiving side, it is also read out from the buffer memory at a period of 125 μs, converted into digital/analog, and reproduced. If this 8KHz clock is distributed to each terminal device as a system clock within a packet communication network, sampling on the transmitting side and reading/reproducing from the buffer memory on the receiving side can be performed synchronously. .

However, in some packet switching networks and local area networks, such system clock distribution is not performed, so sampling and reproduction must be performed using clocks generated within each terminal device. In such a packet communication system, even if there is a slight speed difference because the clocks on the sending and receiving sides are not synchronized, the initial write address and read address of the buffer memory on the receiving side are There is a problem in that the distance from the address increases or decreases cumulatively in one direction as the elapsed communication time increases, resulting in overflow or underflow of the buffer memory and deterioration of the quality of the reproduced audio signal.

Means for Solving the Problems In the voice packet communication system of the present invention which solves the problems of the prior art described above, when a sound packet appears immediately after a predetermined number or more of consecutive silent packets, the transmitting side detects the sound packet. It is sent with an identifier to that effect, and each time the receiving side receives a voice packet with this identifier, the distance between the write address and read address for the buffer memory is set to the initial setting at the start of communication. Configured to be reconfigured.

In other words, in the communication method of the present invention, when a conversation is restarted after a predetermined silent period that is considered as a break in the conversation, this is used as an opportunity to synchronize the transmitting side and the receiving side, thereby preventing buffer memory overflow. It is configured to prevent underflow and improve the quality of the reproduced audio signal.

Hereinafter, the operation of the present invention will be explained in detail together with examples.

Embodiment FIG. 1 is a block diagram showing the configuration of a voice packet transmitter of a terminal device constituting a packet communication system to which a voice packet communication method according to an embodiment of the present invention is applied.

This transmitter includes a packet creation circuit 11, a sound/silence determination/control circuit 12, a packet transmission circuit 13, a continuous silence counter 14, an initialization command creation circuit 15, and a start bit inversion circuit 16.

A digital audio signal sampled at a sampling period Ts and digitized is supplied to the packet generating circuit 11 of the transmitting section at a numbering period Ts.

The packet creation circuit 11 bundles consecutive audio data samples, adds serial numbers in the order of creation, and adds a start bit to the beginning, thereby creating an audio packet in the format shown in FIG. create.

The value of the serial number modulo m is written in the packet number in the order in which the packets were created. Here, m is a number that is m-2j, where j is the number of bits of the packet number.

The sound/silence determination/control circuit 12 includes the packet creation circuit 1
It is determined whether or not the audio data portion of the packet created in step 1 contains sound data, and if it is a sound packet that includes sound data, the initialization command generation circuit is notified of this fact. , the sound packet is sent out from the packet transmission circuit 13 via the start bit inversion circuit 16, and the continuous silence count counter 14 is reset. If the packet created by the packet creation circuit 11 is a silent packet that does not include any sound data in its audio data section, the sound/silence determination control circuit 12 causes the packet to be transferred to the packet transmission circuit 13. The continuous silence counter 14 is incremented.

The initialization command generation circuit 15 includes the sound/silence determination/control unit 1
Every time a notification of the appearance of a voice packet is received from 2, the count value of the continuous silence count counter 14 is continuously counted, and only when the count value exceeds a predetermined number (n), the start bit inversion circuit 16 is activated. to invert the start bit of the transmitted voice packet. This predetermined number of continuous silences n is
The number of packets corresponds to a silent period that is regarded as a break in one conversation.

FIG. 3 is a block diagram showing the configuration of the voice packet receiving section in each terminal device.

In Fig. 3, 21 is a human transmission line, 22 is a packet receiving circuit,
23 is a start bit read control circuit, 24 is a packet number read circuit, 25 is a write control circuit, 26 is a packet buffer memory, 27 is a read control circuit, 28 is a clock generation circuit, and 29 is a D/A converter.

On the sending side, packets are created at a cycle of k T s except for silent packets, and an attempt is made to send them immediately. , arrives at the receiving side with jitter.

A packet buffer 26 is provided to absorb this jitter and reproduce a continuous audio signal.

FIG. 4 is a conceptual diagram showing the logical configuration of the packet buffer memory 5 of FIG. 3, which is shown in the form of a ring buffer. This buffer memory has three storage areas (1), (2), and (2) each capable of storing one packet.

The first received packet is written to the storage area ■ in FIG.
starts from the first address.

In other words, the distance between the write address and the read address is k
It is initialized to Ts. However, each storage area has
It is assumed that silent data has been written as an initial value, and that the contents of the buffer memory are rewritten to silent data at the same time as the writing is completed.

The number of storage areas is determined in consideration of the probability distribution of delay jitter so that packet loss due to overflow or the like is kept below a predetermined value (for example, several percent). For example, in a packet communication system where the delay jitter is less than kTs (packet generation time interval) with a 99% probability, by preparing three storage areas as shown in Figure 4, underflow and overflow can be prevented. This means that 99% of the packets can be received without any trouble.

In other words, under the above assumption, the time from the arrival of the preceding packet until the arrival of the subsequent packet (hereinafter referred to as the "arrival interval") is 0 or more and 2k with a 99% probability.
It becomes below Ts. This arrival interval has a minimum value of 0 because
This is a case where the preceding packet arrives after the minimum delay time by kTs, and the subsequent packet arrives with the minimum delay time.

Also, the arrival interval is maximum (i!'! 2 kT S) because the preceding packet arrives with the minimum delay time, and the subsequent packet that occurs kTs later is delayed by kTs than the minimum delay time. This is the case when you arrive.

In this case, since the arrival time of the above-mentioned subsequent packet is also the generation time of the further subsequent packet, this further subsequent packet will arrive after kTs with a probability of 99%. In other words, if an arrival interval exceeding kTs appears immediately after the arrival interval of the maximum value 2kTs, the read address will overtake the write address, and as a result, the probability that a part of the packet will be lost will only occur with a probability of less than 1%. do not have.

Therefore, as shown in Fig. 4, three storage areas ■ to ■ are prepared, and at the same time as writing to the first packet mentioned above,
If you start reading based on the read address that is incremented in synchronization with the clock signal, and write each subsequent packet sequentially to the storage area ■, ■, ■, ■, ■, etc., cyclically,
Buffer overflows and underflows rarely occur.

However, when writing each packet, the packet number is checked, and if there is a jump, it is determined that the packet is missing.
The storage area for writing is also skipped by the jump. For example, after the first packet is written to the storage area ■, the second packet is a silent packet and is not sent, or even if it is a sound packet, it is lost within the network and is not received. When a third packet is received next, this third packet is written to storage area ■, skipping storage area ■.

On the receiving side, the start bit of each packet is monitored, and when an inversion of the start bit is detected, the packet is written into the storage area corresponding to the packet number, and the read address is reset to the beginning of the immediately previous storage area. That is, the distance between the write address and the read address is redesigned to the state at the time of reception of the first packet.

That is, packets transferred on the human transmission path 21 are received by the packet receiving circuit 22.

The start bit reading circuit 23 reads the start bit of the received packet, and when it detects its inverted state, the start bit readout circuit 23 reads out the start bit of the received packet, and when it detects the inverted state, it reads out the start bit of the received packet. The read control circuit 27 is instructed to set the read counter in 27 to the beginning of the storage area immediately before the storage area where the received packet is written.

The number reading circuit 24 reads the packet number of the received packet and notifies the write control circuit 25 of this. The write control circuit 25 writes the storage area corresponding to the packet number! Write the audio data of the received packet into ~■.

The read control circuit 27 sequentially reads the contents of each storage area of the packet buffer memory 28 while incrementing the read address in synchronization with the clock signal from the clock generation circuit 28, and transmits the contents to the D/A converter 29. At the same time as sending, read end portion silence data is written. When the read control circuit 27 receives a counter value reset command from the start bit reading circuit 23, it reads the contents of the write address counter in the write control circuit 25 and resets the read address to the first value of the immediately previous storage area. Set.

Above, we have shown a configuration in which the read address is reset based on the write address, but conversely, the write address is selected based on the read address, and the subsequent storage area is cyclically incremented based on the relative value of the packet number. It may also be configured in such a way that the In short, the distance between the write address and the read address may be reset to a predetermined value.

Effects of the Invention As explained in detail above, the voice packet communication system of the present invention provides an identifier to that effect for a voice packet that appears immediately after a group of silent packets of a predetermined number or more that are considered to be caused by a break in conversation. A configuration in which the distance between the write address and the read address for the buffer memory is reset to the initial setting state at the start of communication each time the receiving side receives a voice packet with this identifier attached. Therefore, the receiving side and the transmitting side are synchronized as many times as there are interruptions during one conversation.

As a result, overflow and underflow of the buffer memory due to deviations in both the transmitting and receiving clock signals can be effectively prevented, and the quality of the reproduced audio signal can be significantly improved.

Furthermore, according to the present invention, the silent period is expanded or contracted as the distance between the write address and the read address is initialized, but this is different from the case where such distance is initialized while sound data appears. , deterioration in speech quality due to expansion and contraction of the silent period does not substantially occur.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a voice packet transmitter in each terminal device in a packet communication system to which a voice packet communication method according to an embodiment of the present invention is applied;
The figure is a format diagram of the packet in the above embodiment.
The figure is a block diagram showing the configuration of the voice packet receiving section in each terminal device, and FIG. 4 is a conceptual diagram showing the logical configuration of the packet buffer memory in FIG. 3. 11...Packet creation circuit, 12...Speech/silence determination.
Control circuit, 13... Packet transmission circuit, 14... Continuous silence counter, 15... Initialization command creation, 15...
Start bit inversion circuit, 21... human transmission line, 22...
Packet receiving circuit, 23... Start bit reading circuit, 24... Number reading circuit, 25... Write control circuit,
26... Packet buffer memory, 27... Read control circuit, 28... Clock generation circuit, 29... D/A converter.

Claims (1)

[Claims] Digital audio signals consisting of silent data and sound data are bundled by a predetermined sampling number, and serial numbers are assigned to the bundles in the order of creation, thereby containing silent packets containing only silent data and sound data. Create a voice packet,
a transmitter that selectively sends out only voice packets; and a transmitter that writes the digital audio signal in the received voice packet to a write address in a buffer memory that is cyclically updated in accordance with the serial number of the voice packet. , the distance between the digital audio signal in this buffer memory and the write address is initially set when the first voice packet is received, and thereafter it is cyclically stepped at a sampling period synchronized with the clock signal within the device itself. In a packet communication system in which a plurality of terminal devices are connected via a common packet transmission path, the terminal device is equipped with a receiving section that reads data using a read address read out and rewrites the read end portion with silent data. The transmitting unit of the terminal device attaches an identifier to that effect to a voice packet that appears immediately after a predetermined number or more consecutive silent packet group and sends it, and the receiving unit transmits the voice packet to which the identifier is attached. The voice packet communication system is characterized in that the distance between the write address and the read address for the buffer memory is reset to the initial setting state each time the voice packet communication method receives the voice packet.